Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 97.92 95.93 93.40 100.00 98.52 98.76 96.11


Total tests in report: 1001
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
69.59 69.59 81.68 81.68 52.31 52.31 58.48 58.48 64.29 64.29 82.42 82.42 92.29 92.29 55.65 55.65 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.3495282009
78.36 8.77 88.28 6.60 79.11 26.80 74.39 15.91 66.67 2.38 87.08 4.66 93.78 1.49 59.19 3.53 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3722961359
83.09 4.73 95.38 7.10 80.22 1.11 75.72 1.33 78.57 11.90 90.89 3.81 94.03 0.25 66.78 7.60 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.1849263146
86.00 2.91 95.79 0.41 81.79 1.57 83.30 7.58 83.33 4.76 93.01 2.12 94.28 0.25 70.49 3.71 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3885566189
87.46 1.46 96.80 1.01 85.40 3.60 83.48 0.18 83.33 0.00 94.70 1.69 95.02 0.75 73.50 3.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.118753820
88.77 1.31 97.01 0.20 87.89 2.50 83.52 0.04 83.33 0.00 95.34 0.64 96.02 1.00 78.27 4.77 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3140341155
90.04 1.27 97.01 0.00 87.89 0.00 83.52 0.00 90.48 7.14 95.34 0.00 96.02 0.00 80.04 1.77 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.2730524038
91.29 1.25 97.06 0.05 88.17 0.28 87.20 3.67 90.48 0.00 96.40 1.06 96.02 0.00 83.75 3.71 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4232196557
92.14 0.85 97.16 0.10 89.00 0.83 87.70 0.51 92.86 2.38 97.03 0.64 96.27 0.25 84.98 1.24 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1131859551
92.85 0.71 97.16 0.00 90.11 1.11 89.99 2.29 92.86 0.00 97.03 0.00 96.77 0.50 86.04 1.06 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3222891497
93.37 0.52 97.16 0.00 90.20 0.09 89.99 0.00 92.86 0.00 97.25 0.21 96.77 0.00 89.40 3.36 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3541280531
93.80 0.43 97.21 0.05 91.68 1.48 89.99 0.00 92.86 0.00 97.67 0.42 96.77 0.00 90.46 1.06 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.891657632
94.23 0.42 97.31 0.10 92.14 0.46 91.12 1.13 92.86 0.00 97.88 0.21 96.77 0.00 91.52 1.06 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.830157304
94.62 0.39 97.31 0.00 92.14 0.00 91.12 0.00 95.24 2.38 97.88 0.00 96.77 0.00 91.87 0.35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.775641314
94.96 0.34 97.31 0.00 92.14 0.00 91.12 0.00 97.62 2.38 97.88 0.00 96.77 0.00 91.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3185068407
95.30 0.34 97.31 0.00 92.14 0.00 91.12 0.00 100.00 2.38 97.88 0.00 96.77 0.00 91.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3716874700
95.63 0.33 97.41 0.10 92.24 0.09 91.22 0.10 100.00 0.00 98.31 0.42 96.77 0.00 93.46 1.59 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.677541118
95.87 0.24 97.77 0.36 93.16 0.92 91.63 0.40 100.00 0.00 98.31 0.00 96.77 0.00 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.4232323743
96.08 0.21 97.77 0.00 93.16 0.00 91.63 0.00 100.00 0.00 98.31 0.00 98.26 1.49 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1713914099
96.26 0.18 97.92 0.15 93.25 0.09 91.91 0.28 100.00 0.00 98.52 0.21 98.26 0.00 93.99 0.53 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1541139962
96.42 0.15 97.92 0.00 93.25 0.00 92.64 0.73 100.00 0.00 98.52 0.00 98.26 0.00 94.35 0.35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2205108693
96.52 0.10 97.92 0.00 93.62 0.37 92.64 0.00 100.00 0.00 98.52 0.00 98.26 0.00 94.70 0.35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.127269144
96.60 0.08 97.92 0.00 94.18 0.55 92.64 0.00 100.00 0.00 98.52 0.00 98.26 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.736222669
96.68 0.08 97.92 0.00 94.55 0.37 92.64 0.00 100.00 0.00 98.52 0.00 98.26 0.00 94.88 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.51538231
96.76 0.08 97.92 0.00 94.55 0.00 92.82 0.18 100.00 0.00 98.52 0.00 98.26 0.00 95.23 0.35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.767194240
96.81 0.05 97.92 0.00 94.92 0.37 92.82 0.00 100.00 0.00 98.52 0.00 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2774040802
96.86 0.05 97.92 0.00 94.92 0.00 93.17 0.34 100.00 0.00 98.52 0.00 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2521722670
96.91 0.05 97.92 0.00 94.92 0.00 93.32 0.15 100.00 0.00 98.52 0.00 98.26 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1434228133
96.95 0.04 97.92 0.00 95.19 0.28 93.32 0.00 100.00 0.00 98.52 0.00 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2184016491
96.98 0.04 97.92 0.00 95.19 0.00 93.32 0.00 100.00 0.00 98.52 0.00 98.51 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.62755648
97.02 0.04 97.92 0.00 95.19 0.00 93.32 0.00 100.00 0.00 98.52 0.00 98.76 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2254845188
97.04 0.03 97.92 0.00 95.19 0.00 93.34 0.02 100.00 0.00 98.52 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3845574312
97.07 0.03 97.92 0.00 95.19 0.00 93.35 0.01 100.00 0.00 98.52 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2962378603
97.10 0.03 97.92 0.00 95.38 0.18 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.393531814
97.12 0.03 97.92 0.00 95.56 0.18 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4114012872
97.15 0.03 97.92 0.00 95.56 0.00 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.635918869
97.17 0.03 97.92 0.00 95.56 0.00 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2552488549
97.19 0.01 97.92 0.00 95.66 0.09 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.818717587
97.20 0.01 97.92 0.00 95.75 0.09 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3502882009
97.21 0.01 97.92 0.00 95.84 0.09 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3676198363
97.23 0.01 97.92 0.00 95.93 0.09 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1975895946
97.23 0.01 97.92 0.00 95.93 0.00 93.39 0.04 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1554129674
97.23 0.01 97.92 0.00 95.93 0.00 93.40 0.01 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1302507331

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.78277753
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3069271195
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1547105954
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1137276399
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1779272248
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1008231831
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.179845692
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1933833701
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2375673399
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.775643839
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.295952808
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3725295086
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2450238919
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1999642844
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2184650042
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.757105601
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2231741164
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3988510682
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.485586757
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.94876337
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1811715868
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1847142920
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2561458848
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3816920779
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2784667234
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3568172698
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3582083776
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4199850067
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.402564536
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3347064799
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3414880610
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1018144944
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1014740289
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.194328371
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.407096205
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1825538294
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2788698466
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1487138337
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4043582577
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3775996727
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.939033024
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3544215502
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2324445831
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1759634111
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1065964283
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2076794974
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3678350076
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4095574641
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2990193565
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/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3559081203
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/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4224631679



Total test records in report: 1001
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2962378603 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:03 AM UTC 24 30416089 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3845574312 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:03 AM UTC 24 71383600 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.4030797915 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:03 AM UTC 24 90373084 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1554129674 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:05 AM UTC 24 90461126 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3292224565 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:10 AM UTC 24 342490480 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1541139962 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:11 AM UTC 24 366127244 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.3495282009 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:12 AM UTC 24 1191327102 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.4232323743 Sep 04 06:12:11 AM UTC 24 Sep 04 06:12:13 AM UTC 24 24373127 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3885566189 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:14 AM UTC 24 442584282 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2077730351 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:14 AM UTC 24 14551867 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.4271667487 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:14 AM UTC 24 13405940 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2542117501 Sep 04 06:12:34 AM UTC 24 Sep 04 06:12:42 AM UTC 24 1852523388 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1872078267 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:15 AM UTC 24 781996001 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1434228133 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:15 AM UTC 24 314123734 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3948976175 Sep 04 06:12:11 AM UTC 24 Sep 04 06:12:15 AM UTC 24 27656415 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2187850619 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:16 AM UTC 24 2544908969 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.2793093046 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:16 AM UTC 24 113766190 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2689434732 Sep 04 06:12:05 AM UTC 24 Sep 04 06:12:17 AM UTC 24 1009824693 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3722961359 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:18 AM UTC 24 494614602 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1788642120 Sep 04 06:12:16 AM UTC 24 Sep 04 06:12:18 AM UTC 24 14720422 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1553184966 Sep 04 06:12:16 AM UTC 24 Sep 04 06:12:18 AM UTC 24 76259368 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1302507331 Sep 04 06:12:03 AM UTC 24 Sep 04 06:12:19 AM UTC 24 300587088 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3176621885 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:19 AM UTC 24 333571203 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3283763543 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:19 AM UTC 24 652547121 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.1849263146 Sep 04 06:12:03 AM UTC 24 Sep 04 06:12:20 AM UTC 24 2155950154 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.4166321486 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:20 AM UTC 24 3055049962 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.1992807913 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:20 AM UTC 24 237815435 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.288278541 Sep 04 06:12:16 AM UTC 24 Sep 04 06:12:20 AM UTC 24 84502894 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2904444429 Sep 04 06:12:20 AM UTC 24 Sep 04 06:12:23 AM UTC 24 53121472 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1160870060 Sep 04 06:12:16 AM UTC 24 Sep 04 06:12:23 AM UTC 24 659202737 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.60314115 Sep 04 06:12:16 AM UTC 24 Sep 04 06:12:25 AM UTC 24 88414333 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.516839194 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:26 AM UTC 24 250760613 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2348289579 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:26 AM UTC 24 3941892025 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2245958746 Sep 04 06:12:21 AM UTC 24 Sep 04 06:12:26 AM UTC 24 480626559 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.677541118 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:27 AM UTC 24 1754133108 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2615672031 Sep 04 06:12:03 AM UTC 24 Sep 04 06:12:27 AM UTC 24 1361447632 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.118753820 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:28 AM UTC 24 816205144 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1535472129 Sep 04 06:12:18 AM UTC 24 Sep 04 06:12:28 AM UTC 24 216306127 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1743496683 Sep 04 06:12:27 AM UTC 24 Sep 04 06:12:29 AM UTC 24 15407974 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.1034363151 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:30 AM UTC 24 1797750064 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2527062256 Sep 04 06:12:28 AM UTC 24 Sep 04 06:12:30 AM UTC 24 15403337 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.1827368140 Sep 04 06:12:21 AM UTC 24 Sep 04 06:12:31 AM UTC 24 322282266 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4232196557 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:31 AM UTC 24 7094458810 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.950769518 Sep 04 06:12:28 AM UTC 24 Sep 04 06:12:31 AM UTC 24 104804402 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1304280566 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:31 AM UTC 24 1661850808 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1700384173 Sep 04 06:12:18 AM UTC 24 Sep 04 06:12:33 AM UTC 24 564573968 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3702427022 Sep 04 06:12:18 AM UTC 24 Sep 04 06:12:33 AM UTC 24 638987761 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.1403986570 Sep 04 06:12:16 AM UTC 24 Sep 04 06:12:33 AM UTC 24 655564273 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.2097610288 Sep 04 06:12:29 AM UTC 24 Sep 04 06:12:33 AM UTC 24 55906718 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1113265309 Sep 04 06:12:21 AM UTC 24 Sep 04 06:12:34 AM UTC 24 489788730 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.635918869 Sep 04 06:12:31 AM UTC 24 Sep 04 06:12:34 AM UTC 24 31594913 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1615397579 Sep 04 06:12:23 AM UTC 24 Sep 04 06:12:36 AM UTC 24 353064856 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.3928446045 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:36 AM UTC 24 2747183545 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1229551716 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:36 AM UTC 24 8188684523 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3497853334 Sep 04 06:12:21 AM UTC 24 Sep 04 06:12:36 AM UTC 24 395543005 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.568083501 Sep 04 06:12:31 AM UTC 24 Sep 04 06:12:36 AM UTC 24 223410707 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.3343723552 Sep 04 06:12:34 AM UTC 24 Sep 04 06:12:37 AM UTC 24 140671158 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2254845188 Sep 04 06:12:21 AM UTC 24 Sep 04 06:12:38 AM UTC 24 3125357966 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2321594651 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:38 AM UTC 24 2335592600 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3205728234 Sep 04 06:12:24 AM UTC 24 Sep 04 06:12:38 AM UTC 24 647507451 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2690366520 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:38 AM UTC 24 608582693 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2074103967 Sep 04 06:12:38 AM UTC 24 Sep 04 06:12:40 AM UTC 24 68138115 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.4261885780 Sep 04 06:12:23 AM UTC 24 Sep 04 06:12:40 AM UTC 24 441874446 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.905611280 Sep 04 06:12:29 AM UTC 24 Sep 04 06:12:41 AM UTC 24 96639150 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2560748263 Sep 04 06:12:39 AM UTC 24 Sep 04 06:12:41 AM UTC 24 40236307 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3393816616 Sep 04 06:12:39 AM UTC 24 Sep 04 06:12:42 AM UTC 24 59148632 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.847812991 Sep 04 06:12:31 AM UTC 24 Sep 04 06:12:42 AM UTC 24 248424122 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.296221871 Sep 04 06:12:23 AM UTC 24 Sep 04 06:12:44 AM UTC 24 673649719 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.928108182 Sep 04 06:12:39 AM UTC 24 Sep 04 06:12:52 AM UTC 24 313738414 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.2730524038 Sep 04 06:12:30 AM UTC 24 Sep 04 06:12:44 AM UTC 24 374164109 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1153044189 Sep 04 06:12:30 AM UTC 24 Sep 04 06:12:44 AM UTC 24 549460882 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.678056672 Sep 04 06:12:41 AM UTC 24 Sep 04 06:12:45 AM UTC 24 185166492 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1131859551 Sep 04 06:12:11 AM UTC 24 Sep 04 06:12:45 AM UTC 24 229265587 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2552488549 Sep 04 06:12:42 AM UTC 24 Sep 04 06:12:45 AM UTC 24 27460335 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1227604356 Sep 04 06:12:36 AM UTC 24 Sep 04 06:12:49 AM UTC 24 858760273 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.942561336 Sep 04 06:12:16 AM UTC 24 Sep 04 06:12:49 AM UTC 24 266372944 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1307694686 Sep 04 06:12:35 AM UTC 24 Sep 04 06:12:50 AM UTC 24 1565666851 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.4048335399 Sep 04 06:12:45 AM UTC 24 Sep 04 06:12:51 AM UTC 24 768894201 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3541280531 Sep 04 06:12:05 AM UTC 24 Sep 04 06:12:51 AM UTC 24 8762565417 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1514454375 Sep 04 06:12:34 AM UTC 24 Sep 04 06:12:51 AM UTC 24 412744237 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2406401212 Sep 04 06:12:43 AM UTC 24 Sep 04 06:12:52 AM UTC 24 2903354199 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4116649854 Sep 04 06:12:12 AM UTC 24 Sep 04 06:12:54 AM UTC 24 1371261946 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.3976741586 Sep 04 06:12:29 AM UTC 24 Sep 04 06:12:56 AM UTC 24 511792076 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3288027414 Sep 04 06:12:35 AM UTC 24 Sep 04 06:12:56 AM UTC 24 2864407098 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.3328416283 Sep 04 06:12:21 AM UTC 24 Sep 04 06:12:56 AM UTC 24 1898019045 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2332512938 Sep 04 06:12:53 AM UTC 24 Sep 04 06:12:56 AM UTC 24 39461962 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1460239980 Sep 04 06:12:54 AM UTC 24 Sep 04 06:12:56 AM UTC 24 12062059 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.1442807603 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:57 AM UTC 24 2943660882 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2095477013 Sep 04 06:12:46 AM UTC 24 Sep 04 06:12:57 AM UTC 24 552159905 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.792270559 Sep 04 06:12:42 AM UTC 24 Sep 04 06:12:57 AM UTC 24 180901720 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3331417865 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:57 AM UTC 24 8469093867 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.1109310334 Sep 04 06:12:53 AM UTC 24 Sep 04 06:12:57 AM UTC 24 104737140 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.4290557660 Sep 04 06:12:45 AM UTC 24 Sep 04 06:13:00 AM UTC 24 449039260 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.2586934113 Sep 04 06:12:33 AM UTC 24 Sep 04 06:13:00 AM UTC 24 2132750096 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2935212875 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:00 AM UTC 24 39101168 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2447124002 Sep 04 06:12:38 AM UTC 24 Sep 04 06:13:01 AM UTC 24 7176487110 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.527071546 Sep 04 06:12:12 AM UTC 24 Sep 04 06:13:01 AM UTC 24 1323382931 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.1657163794 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:02 AM UTC 24 241699078 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3591779171 Sep 04 06:12:51 AM UTC 24 Sep 04 06:13:02 AM UTC 24 767711084 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.828053632 Sep 04 06:12:41 AM UTC 24 Sep 04 06:13:02 AM UTC 24 2581518168 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.61989955 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:03 AM UTC 24 238747070 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.1802197553 Sep 04 06:12:41 AM UTC 24 Sep 04 06:13:03 AM UTC 24 415515838 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1901649245 Sep 04 06:12:26 AM UTC 24 Sep 04 06:13:03 AM UTC 24 223344289 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.892077492 Sep 04 06:12:51 AM UTC 24 Sep 04 06:13:03 AM UTC 24 564442482 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2482207993 Sep 04 06:12:45 AM UTC 24 Sep 04 06:13:04 AM UTC 24 3779971057 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.1246630153 Sep 04 06:13:01 AM UTC 24 Sep 04 06:13:06 AM UTC 24 91551047 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.3193756024 Sep 04 06:12:38 AM UTC 24 Sep 04 06:13:06 AM UTC 24 359187545 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2205108693 Sep 04 06:12:15 AM UTC 24 Sep 04 06:13:06 AM UTC 24 20614535236 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2349007262 Sep 04 06:13:05 AM UTC 24 Sep 04 06:13:07 AM UTC 24 72225165 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.767194240 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:07 AM UTC 24 223219908 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2273192647 Sep 04 06:12:51 AM UTC 24 Sep 04 06:13:07 AM UTC 24 1068421122 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.4185567180 Sep 04 06:12:34 AM UTC 24 Sep 04 06:13:07 AM UTC 24 3733538378 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3556542898 Sep 04 06:13:05 AM UTC 24 Sep 04 06:13:07 AM UTC 24 33097372 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.1053878681 Sep 04 06:13:05 AM UTC 24 Sep 04 06:13:07 AM UTC 24 21456211 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3942961935 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:08 AM UTC 24 657773427 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1879939867 Sep 04 06:13:01 AM UTC 24 Sep 04 06:13:08 AM UTC 24 599469183 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.3842507708 Sep 04 06:12:39 AM UTC 24 Sep 04 06:13:08 AM UTC 24 886149894 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.280556057 Sep 04 06:12:45 AM UTC 24 Sep 04 06:13:10 AM UTC 24 4810927980 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2347590253 Sep 04 06:13:09 AM UTC 24 Sep 04 06:13:11 AM UTC 24 76570449 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3165064270 Sep 04 06:13:03 AM UTC 24 Sep 04 06:13:11 AM UTC 24 398323613 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.139290370 Sep 04 06:13:08 AM UTC 24 Sep 04 06:13:12 AM UTC 24 55273979 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.1476484276 Sep 04 06:13:07 AM UTC 24 Sep 04 06:13:13 AM UTC 24 483954467 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1275207318 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:13 AM UTC 24 311928800 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2768976988 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:13 AM UTC 24 271518787 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.3795040877 Sep 04 06:13:03 AM UTC 24 Sep 04 06:13:14 AM UTC 24 1216001031 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3972539158 Sep 04 06:13:09 AM UTC 24 Sep 04 06:13:15 AM UTC 24 514875858 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3564678929 Sep 04 06:13:04 AM UTC 24 Sep 04 06:13:16 AM UTC 24 291951390 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.292889228 Sep 04 06:13:03 AM UTC 24 Sep 04 06:13:17 AM UTC 24 629673394 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.337510485 Sep 04 06:13:12 AM UTC 24 Sep 04 06:13:18 AM UTC 24 235643551 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.3439037426 Sep 04 06:12:44 AM UTC 24 Sep 04 06:13:37 AM UTC 24 2784359607 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1364994292 Sep 04 06:13:16 AM UTC 24 Sep 04 06:13:19 AM UTC 24 21670029 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.238306106 Sep 04 06:13:08 AM UTC 24 Sep 04 06:13:20 AM UTC 24 668066805 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3122054106 Sep 04 06:12:21 AM UTC 24 Sep 04 06:13:21 AM UTC 24 2378475786 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.157924061 Sep 04 06:13:18 AM UTC 24 Sep 04 06:13:21 AM UTC 24 19138494 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.2215156537 Sep 04 06:13:17 AM UTC 24 Sep 04 06:13:21 AM UTC 24 112504988 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.665177790 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:21 AM UTC 24 3068475352 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3246746477 Sep 04 06:13:09 AM UTC 24 Sep 04 06:13:21 AM UTC 24 666775846 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1883449653 Sep 04 06:13:08 AM UTC 24 Sep 04 06:13:23 AM UTC 24 1327383796 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.839151425 Sep 04 06:13:09 AM UTC 24 Sep 04 06:13:24 AM UTC 24 1854208663 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.3237134063 Sep 04 06:13:07 AM UTC 24 Sep 04 06:13:24 AM UTC 24 599295979 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.751058252 Sep 04 06:13:22 AM UTC 24 Sep 04 06:13:24 AM UTC 24 13250528 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3637458629 Sep 04 06:13:20 AM UTC 24 Sep 04 06:13:26 AM UTC 24 159482621 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.3360973602 Sep 04 06:13:13 AM UTC 24 Sep 04 06:13:27 AM UTC 24 825165776 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2512277803 Sep 04 06:12:52 AM UTC 24 Sep 04 06:13:28 AM UTC 24 228052090 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2840599019 Sep 04 06:13:23 AM UTC 24 Sep 04 06:13:28 AM UTC 24 553063942 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1441216466 Sep 04 06:13:11 AM UTC 24 Sep 04 06:13:28 AM UTC 24 1789519025 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3563338802 Sep 04 06:13:12 AM UTC 24 Sep 04 06:13:29 AM UTC 24 5366787635 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.138811545 Sep 04 06:13:13 AM UTC 24 Sep 04 06:13:30 AM UTC 24 1862872050 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3551342660 Sep 04 06:13:08 AM UTC 24 Sep 04 06:13:35 AM UTC 24 469524234 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2628746676 Sep 04 06:13:19 AM UTC 24 Sep 04 06:13:30 AM UTC 24 275856912 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1302463000 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:31 AM UTC 24 1356800973 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3839621852 Sep 04 06:12:46 AM UTC 24 Sep 04 06:13:31 AM UTC 24 5386823924 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4175383371 Sep 04 06:13:22 AM UTC 24 Sep 04 06:13:32 AM UTC 24 2262139553 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1797200083 Sep 04 06:13:24 AM UTC 24 Sep 04 06:13:32 AM UTC 24 229529264 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.4046343102 Sep 04 06:13:22 AM UTC 24 Sep 04 06:13:34 AM UTC 24 281930474 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.242177821 Sep 04 06:13:31 AM UTC 24 Sep 04 06:13:34 AM UTC 24 64853480 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.511517931 Sep 04 06:13:32 AM UTC 24 Sep 04 06:13:35 AM UTC 24 69495052 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.894727975 Sep 04 06:13:25 AM UTC 24 Sep 04 06:13:37 AM UTC 24 1961604344 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1975895946 Sep 04 06:13:01 AM UTC 24 Sep 04 06:13:38 AM UTC 24 3170037074 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2069370655 Sep 04 06:13:15 AM UTC 24 Sep 04 06:13:38 AM UTC 24 705379759 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3050503613 Sep 04 06:13:33 AM UTC 24 Sep 04 06:13:38 AM UTC 24 269218512 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1232924979 Sep 04 06:13:36 AM UTC 24 Sep 04 06:13:39 AM UTC 24 20589389 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.1393785558 Sep 04 06:13:32 AM UTC 24 Sep 04 06:13:40 AM UTC 24 396636873 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.53363293 Sep 04 06:13:29 AM UTC 24 Sep 04 06:13:40 AM UTC 24 4860661418 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1312928902 Sep 04 06:13:29 AM UTC 24 Sep 04 06:13:40 AM UTC 24 366555455 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.738161568 Sep 04 06:13:22 AM UTC 24 Sep 04 06:13:41 AM UTC 24 358981043 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1561204131 Sep 04 06:13:29 AM UTC 24 Sep 04 06:13:41 AM UTC 24 299489105 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.830157304 Sep 04 06:12:14 AM UTC 24 Sep 04 06:13:41 AM UTC 24 7387252292 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.844964727 Sep 04 06:13:03 AM UTC 24 Sep 04 06:13:42 AM UTC 24 1246618361 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.269092059 Sep 04 06:13:35 AM UTC 24 Sep 04 06:13:44 AM UTC 24 236213465 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1919322133 Sep 04 06:13:38 AM UTC 24 Sep 04 06:13:45 AM UTC 24 180564925 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2233797383 Sep 04 06:13:36 AM UTC 24 Sep 04 06:13:47 AM UTC 24 346570258 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.2080523651 Sep 04 06:13:24 AM UTC 24 Sep 04 06:13:48 AM UTC 24 1426679812 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1063045218 Sep 04 06:13:46 AM UTC 24 Sep 04 06:13:48 AM UTC 24 65390606 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1020713095 Sep 04 06:13:29 AM UTC 24 Sep 04 06:13:48 AM UTC 24 9151826320 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3236380351 Sep 04 06:13:04 AM UTC 24 Sep 04 06:13:49 AM UTC 24 9559658326 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.83119971 Sep 04 06:13:39 AM UTC 24 Sep 04 06:13:49 AM UTC 24 2021792077 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.277005413 Sep 04 06:13:46 AM UTC 24 Sep 04 06:13:49 AM UTC 24 76723603 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4224631679 Sep 04 06:13:48 AM UTC 24 Sep 04 06:13:50 AM UTC 24 13004496 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.2064273229 Sep 04 06:13:41 AM UTC 24 Sep 04 06:13:50 AM UTC 24 666745890 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3944043855 Sep 04 06:13:19 AM UTC 24 Sep 04 06:13:51 AM UTC 24 254675271 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1354282627 Sep 04 06:13:10 AM UTC 24 Sep 04 06:13:52 AM UTC 24 1430282932 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4263249731 Sep 04 06:13:31 AM UTC 24 Sep 04 06:13:53 AM UTC 24 263346839 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1351417886 Sep 04 06:13:40 AM UTC 24 Sep 04 06:13:53 AM UTC 24 658467784 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.1229831915 Sep 04 06:14:15 AM UTC 24 Sep 04 06:14:28 AM UTC 24 534126165 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3860558675 Sep 04 06:13:42 AM UTC 24 Sep 04 06:13:53 AM UTC 24 954226525 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3716874700 Sep 04 06:13:35 AM UTC 24 Sep 04 06:13:53 AM UTC 24 2046417307 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.2619772225 Sep 04 06:13:52 AM UTC 24 Sep 04 06:13:54 AM UTC 24 20585970 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1293859994 Sep 04 06:13:49 AM UTC 24 Sep 04 06:13:54 AM UTC 24 70423122 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.2731594207 Sep 04 06:13:42 AM UTC 24 Sep 04 06:13:55 AM UTC 24 276765380 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2521722670 Sep 04 06:12:58 AM UTC 24 Sep 04 06:13:55 AM UTC 24 7140278839 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2186893280 Sep 04 06:13:52 AM UTC 24 Sep 04 06:13:58 AM UTC 24 666767164 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3559081203 Sep 04 06:13:41 AM UTC 24 Sep 04 06:13:59 AM UTC 24 1378927795 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.1586345655 Sep 04 06:13:49 AM UTC 24 Sep 04 06:14:00 AM UTC 24 160292637 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.3932350838 Sep 04 06:13:50 AM UTC 24 Sep 04 06:14:01 AM UTC 24 738627502 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.2182738501 Sep 04 06:13:38 AM UTC 24 Sep 04 06:14:01 AM UTC 24 1088814670 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3787037705 Sep 04 06:12:33 AM UTC 24 Sep 04 06:14:02 AM UTC 24 9326259889 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2473310539 Sep 04 06:13:50 AM UTC 24 Sep 04 06:14:03 AM UTC 24 1368131135 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.868426526 Sep 04 06:14:01 AM UTC 24 Sep 04 06:14:03 AM UTC 24 16416488 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.428751836 Sep 04 06:14:02 AM UTC 24 Sep 04 06:14:05 AM UTC 24 13401107 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3131309203 Sep 04 06:13:56 AM UTC 24 Sep 04 06:14:06 AM UTC 24 1259747234 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3923233377 Sep 04 06:13:54 AM UTC 24 Sep 04 06:14:06 AM UTC 24 709380186 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1090935321 Sep 04 06:14:02 AM UTC 24 Sep 04 06:14:06 AM UTC 24 69143093 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.617935542 Sep 04 06:12:12 AM UTC 24 Sep 04 06:14:07 AM UTC 24 6839671367 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3671197709 Sep 04 06:13:09 AM UTC 24 Sep 04 06:14:07 AM UTC 24 1356379660 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1039996580 Sep 04 06:13:50 AM UTC 24 Sep 04 06:14:08 AM UTC 24 1433839118 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2654317369 Sep 04 06:13:41 AM UTC 24 Sep 04 06:14:08 AM UTC 24 6428190085 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3343042803 Sep 04 06:13:56 AM UTC 24 Sep 04 06:14:08 AM UTC 24 255286369 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1401207208 Sep 04 06:13:56 AM UTC 24 Sep 04 06:14:09 AM UTC 24 1769209340 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3222891497 Sep 04 06:12:26 AM UTC 24 Sep 04 06:14:09 AM UTC 24 34373253585 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3951691152 Sep 04 06:13:27 AM UTC 24 Sep 04 06:14:09 AM UTC 24 1664044014 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1583795259 Sep 04 06:13:54 AM UTC 24 Sep 04 06:14:09 AM UTC 24 441045763 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.937704584 Sep 04 06:14:05 AM UTC 24 Sep 04 06:14:09 AM UTC 24 147312835 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.3835639203 Sep 04 06:13:54 AM UTC 24 Sep 04 06:14:10 AM UTC 24 2810427255 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.4219188727 Sep 04 06:13:23 AM UTC 24 Sep 04 06:14:11 AM UTC 24 25654714506 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3240187147 Sep 04 06:14:04 AM UTC 24 Sep 04 06:14:11 AM UTC 24 248339506 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.1331544762 Sep 04 06:14:10 AM UTC 24 Sep 04 06:14:13 AM UTC 24 45371950 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.123653972 Sep 04 06:13:15 AM UTC 24 Sep 04 06:14:13 AM UTC 24 6427947540 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2206327251 Sep 04 06:14:12 AM UTC 24 Sep 04 06:14:14 AM UTC 24 12277905 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2734457472 Sep 04 06:13:49 AM UTC 24 Sep 04 06:14:14 AM UTC 24 681667625 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.2076305596 Sep 04 06:13:32 AM UTC 24 Sep 04 06:14:14 AM UTC 24 2502336426 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.4046186712 Sep 04 06:13:04 AM UTC 24 Sep 04 06:14:15 AM UTC 24 10880669974 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.893457312 Sep 04 06:14:10 AM UTC 24 Sep 04 06:14:16 AM UTC 24 155368540 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2411306268 Sep 04 06:14:06 AM UTC 24 Sep 04 06:14:16 AM UTC 24 961333842 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.500326890 Sep 04 06:14:11 AM UTC 24 Sep 04 06:14:17 AM UTC 24 312815335 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3610348573 Sep 04 06:14:14 AM UTC 24 Sep 04 06:14:18 AM UTC 24 62197573 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3831841321 Sep 04 06:14:07 AM UTC 24 Sep 04 06:14:18 AM UTC 24 466954301 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2981720088 Sep 04 06:14:07 AM UTC 24 Sep 04 06:14:18 AM UTC 24 7411941539 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.3920088768 Sep 04 06:14:14 AM UTC 24 Sep 04 06:14:19 AM UTC 24 121159456 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.4208778618 Sep 04 06:14:10 AM UTC 24 Sep 04 06:14:19 AM UTC 24 215559558 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1520058860 Sep 04 06:13:56 AM UTC 24 Sep 04 06:14:20 AM UTC 24 929178779 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3333309366 Sep 04 06:13:54 AM UTC 24 Sep 04 06:14:20 AM UTC 24 4174101062 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.4047997015 Sep 04 06:14:19 AM UTC 24 Sep 04 06:14:23 AM UTC 24 208525248 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.99105172 Sep 04 06:14:15 AM UTC 24 Sep 04 06:14:23 AM UTC 24 904177095 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1706896883 Sep 04 06:13:38 AM UTC 24 Sep 04 06:14:23 AM UTC 24 1152057123 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2065187455 Sep 04 06:14:15 AM UTC 24 Sep 04 06:14:24 AM UTC 24 924755630 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.479254472 Sep 04 06:14:21 AM UTC 24 Sep 04 06:14:24 AM UTC 24 16155845 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.921106071 Sep 04 06:14:08 AM UTC 24 Sep 04 06:14:26 AM UTC 24 762587579 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.235704395 Sep 04 06:14:24 AM UTC 24 Sep 04 06:14:26 AM UTC 24 65668039 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.1677000295 Sep 04 06:14:08 AM UTC 24 Sep 04 06:14:27 AM UTC 24 586256028 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.2992399021 Sep 04 06:14:10 AM UTC 24 Sep 04 06:14:27 AM UTC 24 2081341325 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3789923030 Sep 04 06:14:20 AM UTC 24 Sep 04 06:14:29 AM UTC 24 710826288 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1666000101 Sep 04 06:14:25 AM UTC 24 Sep 04 06:14:29 AM UTC 24 246746735 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.2886217859 Sep 04 06:15:07 AM UTC 24 Sep 04 06:15:18 AM UTC 24 1178833870 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.1194430903 Sep 04 06:14:25 AM UTC 24 Sep 04 06:14:29 AM UTC 24 83074346 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.3470849812 Sep 04 06:14:19 AM UTC 24 Sep 04 06:14:30 AM UTC 24 3008575997 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.4229618857 Sep 04 06:14:02 AM UTC 24 Sep 04 06:14:30 AM UTC 24 770443177 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.821500843 Sep 04 06:14:18 AM UTC 24 Sep 04 06:14:30 AM UTC 24 1857721848 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.350958098 Sep 04 06:14:10 AM UTC 24 Sep 04 06:14:32 AM UTC 24 561361068 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.4222627498 Sep 04 06:13:52 AM UTC 24 Sep 04 06:14:33 AM UTC 24 918795499 ps
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