Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62119993

1

T1

1342

T2

2209

T3

3167

auto[1]

1096100

1

T4

693

T5

198

T15

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62097867

1

T1

1342

T2

2209

T3

3167

auto[1]

1118226

1

T4

1089

T5

297

T15

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5399883	1			T1	112		T2	115		T3	1144
auto[IdleSt]	17773329	1			T1	1230		T2	76		T3	307
auto[ClkMuxSt]	29486	1			T2	1		T3	11		T4	18
auto[CntIncrSt]	29275	1			T2	1		T3	11		T4	18
auto[CntProgSt]	1380135	1			T2	752		T3	470		T4	36
auto[TransCheckSt]	23424	1			T2	1		T3	11		T5	7
auto[TokenHashSt]	16634118	1			T2	23		T3	203		T5	80
auto[FlashRmaSt]	29184	1			T3	61		T5	7		T13	21
auto[TokenCheck0St]	10351	1			T3	11		T5	7		T13	4
auto[TokenCheck1St]	7525	1			T3	11		T5	7		T13	4
auto[TransProgSt]	384610	1			T3	388		T5	183		T13	26
auto[PostTransSt]	9839969	1			T2	1240		T3	526		T4	1471
auto[ScrapSt]	255926	1			T3	13		T31	1018		T29	20
auto[EscalateSt]	4560529	1			T4	2552		T5	1203		T15	583
auto[InvalidSt]	6856951	1			T5	660		T22	354		T30	5154

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1398	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6856951	1			T5	660		T22	354		T30	5154
EscalateSt	4560529	1			T4	2552		T5	1203		T15	583
ScrapSt	255926	1			T3	13		T31	1018		T29	20
PostTransSt	9839969	1			T2	1240		T3	526		T4	1471
TransProgSt	384610	1			T3	388		T5	183		T13	26
TokenCheck1St	7525	1			T3	11		T5	7		T13	4
TokenCheck0St	10351	1			T3	11		T5	7		T13	4
FlashRmaSt	29184	1			T3	61		T5	7		T13	21
TokenHashSt	16634118	1			T2	23		T3	203		T5	80
TransCheckSt	23424	1			T2	1		T3	11		T5	7
CntProgSt	1380135	1			T2	752		T3	470		T4	36
CntIncrSt	29275	1			T2	1		T3	11		T4	18
ClkMuxSt	29486	1			T2	1		T3	11		T4	18
IdleSt	17773329	1			T1	1230		T2	76		T3	307
ResetSt	5399883	1			T1	112		T2	115		T3	1144
arcs[ResetSt=>IdleSt]	42975	1			T1	1		T2	1		T3	12
arcs[IdleSt=>ScrapSt]	258	1			T3	1		T31	1		T29	5
arcs[IdleSt=>ClkMuxSt]	29303	1			T2	1		T3	11		T4	18
arcs[ClkMuxSt=>CntIncrSt]	29275	1			T2	1		T3	11		T4	18
arcs[CntIncrSt=>PostTransSt]	1366	1			T15	12		T23	12		T24	7
arcs[CntIncrSt=>CntProgSt]	27832	1			T2	1		T3	11		T4	18
arcs[CntProgSt=>PostTransSt]	3620	1			T4	18		T15	5		T20	20
arcs[CntProgSt=>TransCheckSt]	23424	1			T2	1		T3	11		T5	7
arcs[TransCheckSt=>PostTransSt]	3170	1			T15	2		T21	38		T23	9
arcs[TransCheckSt=>TokenHashSt]	20106	1			T2	1		T3	11		T5	7
arcs[TokenHashSt=>PostTransSt]	8696	1			T2	1		T14	1		T15	24
arcs[TokenHashSt=>FlashRmaSt]	10386	1			T3	11		T5	7		T13	4
arcs[FlashRmaSt=>TokenCheck0St]	10351	1			T3	11		T5	7		T13	4
arcs[TokenCheck0St=>PostTransSt]	2766	1			T15	4		T21	20		T23	11
arcs[TokenCheck0St=>TokenCheck1St]	7525	1			T3	11		T5	7		T13	4
arcs[TokenCheck1St=>PostTransSt]	569	1			T21	3		T46	9		T24	1
arcs[TransProgSt=>PostTransSt]	6243	1			T3	11		T5	7		T13	4
arcs[IdleSt=>EscalateSt]	116	1			T16	7		T60	5		T62	4
arcs[ClkMuxSt=>EscalateSt]	28	1			T16	1		T60	1		T61	2
arcs[CntIncrSt=>EscalateSt]	77	1			T19	1		T29	5		T28	3
arcs[CntProgSt=>EscalateSt]	788	1			T19	4		T29	38		T28	3
arcs[TransCheckSt=>EscalateSt]	148	1			T19	2		T28	5		T16	3
arcs[TokenHashSt=>EscalateSt]	1024	1			T19	27		T29	9		T28	29
arcs[FlashRmaSt=>EscalateSt]	35	1			T19	1		T29	1		T60	1
arcs[TokenCheck0St=>EscalateSt]	60	1			T19	1		T29	2		T66	2
arcs[TokenCheck1St=>EscalateSt]	38	1			T19	1		T66	2		T67	1
arcs[TransProgSt=>EscalateSt]	675	1			T19	4		T29	28		T28	10
arcs[PostTransSt=>EscalateSt]	4058	1			T4	18		T15	5		T19	8
arcs[InvalidSt=>EscalateSt]	9734	1			T5	5		T22	4		T30	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5399716	1			T1	112		T2	115		T3	1144
auto[0]	auto[IdleSt]	17773251	1			T1	1230		T2	76		T3	307
auto[0]	auto[ClkMuxSt]	29470	1			T2	1		T3	11		T4	18
auto[0]	auto[CntIncrSt]	29223	1			T2	1		T3	11		T4	18
auto[0]	auto[CntProgSt]	1379610	1			T2	752		T3	470		T4	36
auto[0]	auto[TransCheckSt]	23330	1			T2	1		T3	11		T5	7
auto[0]	auto[TokenHashSt]	16633456	1			T2	23		T3	203		T5	80
auto[0]	auto[FlashRmaSt]	29164	1			T3	61		T5	7		T13	21
auto[0]	auto[TokenCheck0St]	10314	1			T3	11		T5	7		T13	4
auto[0]	auto[TokenCheck1St]	7506	1			T3	11		T5	7		T13	4
auto[0]	auto[TransProgSt]	384161	1			T3	388		T5	183		T13	26
auto[0]	auto[PostTransSt]	9837840	1			T2	1240		T3	526		T4	1464
auto[0]	auto[ScrapSt]	255877	1			T3	13		T31	1018		T29	17
auto[0]	auto[EscalateSt]	3473535	1			T4	1866		T5	1007		T15	485
auto[0]	auto[InvalidSt]	6852142	1			T5	658		T22	353		T30	5153
auto[1]	auto[ResetSt]	167	1			T19	2		T29	5		T28	3
auto[1]	auto[IdleSt]	78	1			T16	3		T60	4		T62	4
auto[1]	auto[ClkMuxSt]	16	1			T16	1		T61	2		T228	1
auto[1]	auto[CntIncrSt]	52	1			T19	1		T29	3		T28	3
auto[1]	auto[CntProgSt]	525	1			T19	1		T29	29		T28	3
auto[1]	auto[TransCheckSt]	94	1			T19	1		T28	2		T16	2
auto[1]	auto[TokenHashSt]	662	1			T19	15		T29	5		T28	19
auto[1]	auto[FlashRmaSt]	20	1			T19	1		T229	1		T230	1
auto[1]	auto[TokenCheck0St]	37	1			T19	1		T29	1		T66	2
auto[1]	auto[TokenCheck1St]	19	1			T19	1		T66	1		T231	3
auto[1]	auto[TransProgSt]	449	1			T19	3		T29	21		T28	5
auto[1]	auto[PostTransSt]	2129	1			T4	7		T15	1		T19	3
auto[1]	auto[ScrapSt]	49	1			T29	3		T28	1		T231	1
auto[1]	auto[EscalateSt]	1086994	1			T4	686		T5	196		T15	98
auto[1]	auto[InvalidSt]	4809	1			T5	2		T22	1		T30	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5399687	1			T1	112		T2	115		T3	1144
auto[0]	auto[IdleSt]	17773260	1			T1	1230		T2	76		T3	307
auto[0]	auto[ClkMuxSt]	29466	1			T2	1		T3	11		T4	18
auto[0]	auto[CntIncrSt]	29219	1			T2	1		T3	11		T4	18
auto[0]	auto[CntProgSt]	1379610	1			T2	752		T3	470		T4	36
auto[0]	auto[TransCheckSt]	23328	1			T2	1		T3	11		T5	7
auto[0]	auto[TokenHashSt]	16633405	1			T2	23		T3	203		T5	80
auto[0]	auto[FlashRmaSt]	29160	1			T3	61		T5	7		T13	21
auto[0]	auto[TokenCheck0St]	10310	1			T3	11		T5	7		T13	4
auto[0]	auto[TokenCheck1St]	7496	1			T3	11		T5	7		T13	4
auto[0]	auto[TransProgSt]	384175	1			T3	388		T5	183		T13	26
auto[0]	auto[PostTransSt]	9837905	1			T2	1240		T3	526		T4	1460
auto[0]	auto[ScrapSt]	255888	1			T3	13		T31	1018		T29	17
auto[0]	auto[EscalateSt]	3451534	1			T4	1474		T5	909		T15	191
auto[0]	auto[InvalidSt]	6852026	1			T5	657		T22	351		T30	5151
auto[1]	auto[ResetSt]	196	1			T19	4		T29	5		T28	1
auto[1]	auto[IdleSt]	69	1			T16	4		T60	2		T62	3
auto[1]	auto[ClkMuxSt]	20	1			T16	1		T60	1		T61	1
auto[1]	auto[CntIncrSt]	56	1			T29	3		T28	3		T60	3
auto[1]	auto[CntProgSt]	525	1			T19	4		T29	20		T28	1
auto[1]	auto[TransCheckSt]	96	1			T19	1		T28	3		T16	1
auto[1]	auto[TokenHashSt]	713	1			T19	19		T29	8		T28	22
auto[1]	auto[FlashRmaSt]	24	1			T19	1		T29	1		T60	1
auto[1]	auto[TokenCheck0St]	41	1			T29	1		T60	3		T67	2
auto[1]	auto[TokenCheck1St]	29	1			T19	1		T66	2		T67	1
auto[1]	auto[TransProgSt]	435	1			T19	3		T29	21		T28	7
auto[1]	auto[PostTransSt]	2064	1			T4	11		T15	4		T19	8
auto[1]	auto[ScrapSt]	38	1			T29	3		T28	1		T60	1
auto[1]	auto[EscalateSt]	1108995	1			T4	1078		T5	294		T15	392
auto[1]	auto[InvalidSt]	4925	1			T5	3		T22	3		T30	3