Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.92 95.84 93.40 100.00 98.52 98.76 96.29


Total tests in report: 1012
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.17 67.17 81.99 81.99 52.77 52.77 58.32 58.32 50.00 50.00 81.57 81.57 92.04 92.04 53.53 53.53 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1446347538
77.68 10.50 88.89 6.90 80.31 27.54 74.53 16.21 54.76 4.76 89.19 7.63 94.03 1.99 62.01 8.48 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2704675680
82.42 4.74 89.14 0.25 82.35 2.03 75.86 1.33 76.19 21.43 90.89 1.69 94.28 0.25 68.20 6.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.76096685
86.03 3.62 89.75 0.61 85.58 3.23 85.54 9.68 80.95 4.76 91.95 1.06 94.78 0.50 73.67 5.48 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3930067006
88.25 2.22 96.04 6.29 85.58 0.00 85.78 0.24 83.33 2.38 93.43 1.48 94.78 0.00 78.80 5.12 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.4065375136
89.61 1.36 96.19 0.15 85.58 0.00 85.78 0.00 90.48 7.14 94.07 0.64 94.78 0.00 80.39 1.59 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.4000134305
90.74 1.13 96.91 0.71 87.25 1.66 86.11 0.33 90.48 0.00 95.34 1.27 95.52 0.75 83.57 3.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2031583506
91.73 1.00 97.01 0.10 88.91 1.66 86.15 0.04 90.48 0.00 95.97 0.64 96.52 1.00 87.10 3.53 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2310027891
92.55 0.81 97.11 0.10 89.65 0.74 86.70 0.55 92.86 2.38 96.40 0.42 96.77 0.25 88.34 1.24 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1541443531
93.20 0.66 97.16 0.05 89.65 0.00 87.94 1.23 95.24 2.38 96.61 0.21 96.77 0.00 89.05 0.71 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1735514510
93.67 0.47 97.16 0.00 89.65 0.00 90.71 2.77 95.24 0.00 96.61 0.00 96.77 0.00 89.58 0.53 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.747487723
94.12 0.44 97.31 0.15 90.94 1.29 90.71 0.00 95.24 0.00 97.03 0.42 96.77 0.00 90.81 1.24 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1966549071
94.50 0.38 97.41 0.10 90.94 0.00 91.28 0.57 95.24 0.00 97.46 0.42 96.77 0.00 92.40 1.59 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.2207870631
94.84 0.34 97.41 0.00 90.94 0.00 91.28 0.00 97.62 2.38 97.46 0.00 96.77 0.00 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.4159968857
95.18 0.34 97.41 0.00 90.94 0.00 91.28 0.00 100.00 2.38 97.46 0.00 96.77 0.00 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.1379360968
95.41 0.23 97.41 0.00 91.04 0.09 92.06 0.79 100.00 0.00 97.67 0.21 96.77 0.00 92.93 0.53 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1813524423
95.63 0.22 97.51 0.10 91.22 0.18 92.06 0.00 100.00 0.00 97.88 0.21 96.77 0.00 93.99 1.06 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3983892332
95.85 0.21 97.87 0.36 92.14 0.92 92.29 0.22 100.00 0.00 97.88 0.00 96.77 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1460125630
96.06 0.21 97.87 0.00 92.14 0.00 92.29 0.00 100.00 0.00 97.88 0.00 98.26 1.49 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2036459619
96.22 0.16 97.87 0.00 93.07 0.92 92.29 0.00 100.00 0.00 97.88 0.00 98.26 0.00 94.17 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2349528379
96.33 0.11 97.92 0.05 93.07 0.00 92.44 0.15 100.00 0.00 98.09 0.21 98.26 0.00 94.52 0.35 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3633785156
96.43 0.10 97.92 0.00 93.44 0.37 92.44 0.00 100.00 0.00 98.09 0.00 98.26 0.00 94.88 0.35 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3616990434
96.52 0.08 97.92 0.00 93.44 0.00 92.46 0.02 100.00 0.00 98.31 0.21 98.26 0.00 95.23 0.35 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.728021123
96.58 0.07 97.92 0.00 93.44 0.00 92.93 0.47 100.00 0.00 98.31 0.00 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1423785896
96.65 0.07 97.92 0.00 93.90 0.46 92.93 0.00 100.00 0.00 98.31 0.00 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1414328241
96.71 0.07 97.92 0.00 93.90 0.00 92.93 0.00 100.00 0.00 98.52 0.21 98.51 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.995837947
96.78 0.06 97.92 0.00 94.18 0.28 92.93 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2656225378
96.82 0.04 97.92 0.00 94.45 0.28 92.93 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1050152957
96.86 0.04 97.92 0.00 94.73 0.28 92.93 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4273377474
96.89 0.04 97.92 0.00 94.73 0.00 92.93 0.00 100.00 0.00 98.52 0.00 98.76 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2883834354
96.93 0.03 97.92 0.00 94.73 0.00 93.17 0.24 100.00 0.00 98.52 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.3266890065
96.96 0.03 97.92 0.00 94.73 0.00 93.23 0.06 100.00 0.00 98.52 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1970629707
96.99 0.03 97.92 0.00 94.92 0.18 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.612922358
97.01 0.03 97.92 0.00 94.92 0.00 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.4049466614
97.04 0.03 97.92 0.00 94.92 0.00 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1665222240
97.06 0.03 97.92 0.00 94.92 0.00 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.4141049269
97.09 0.03 97.92 0.00 94.92 0.00 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.776877574
97.10 0.01 97.92 0.00 95.01 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1524443346
97.12 0.01 97.92 0.00 95.10 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1992642634
97.13 0.01 97.92 0.00 95.19 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3374642348
97.14 0.01 97.92 0.00 95.29 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.951051000
97.16 0.01 97.92 0.00 95.38 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1995479263
97.17 0.01 97.92 0.00 95.47 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2664948544
97.18 0.01 97.92 0.00 95.56 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.698516212
97.20 0.01 97.92 0.00 95.66 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2266492308
97.21 0.01 97.92 0.00 95.75 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1555567917
97.22 0.01 97.92 0.00 95.84 0.09 93.23 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1821868428
97.23 0.01 97.92 0.00 95.84 0.00 93.31 0.08 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1700966703
97.24 0.01 97.92 0.00 95.84 0.00 93.37 0.06 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1493992051
97.25 0.01 97.92 0.00 95.84 0.00 93.40 0.03 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3308261694

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3754264545
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1594864212
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4085445442
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.809758778
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3212437564
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3629920150
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.633823184
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3603936536
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.825756467
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2070701443
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4225015910
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1727490447
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1335491242
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.628932345
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.202685287
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4096166731
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2851738576
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1566045975
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2720769504
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3044711269
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2510056927
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2207207135
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3045365264
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.967172509
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1925058575
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.440486147
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.536181949
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3542948093
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3826086250
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2771886681
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1666569709
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2453795890
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4081491425
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3049483708
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2295938530
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3773194460
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1142272160
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/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3448406463
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.4177384064
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.649713822
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/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3662233312
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1007483644
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.437392655
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1884844489
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.324436375
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.585453510
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3311928756
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.2697101236
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3054846722
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/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3118301699
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3918072178
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3188968127
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3634424553
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3510062869
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1656171747
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/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1287731575



Total test records in report: 1012
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.4049466614 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:00 AM UTC 24 14011690 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.381454421 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:01 AM UTC 24 23037760 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3231256358 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:02 AM UTC 24 211206236 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2593699740 Sep 09 11:21:00 AM UTC 24 Sep 09 11:21:03 AM UTC 24 144493536 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3738559305 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:03 AM UTC 24 376565952 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1460125630 Sep 09 11:21:01 AM UTC 24 Sep 09 11:21:04 AM UTC 24 15682238 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.2073717148 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:04 AM UTC 24 282704104 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.2831134640 Sep 09 11:21:04 AM UTC 24 Sep 09 11:21:06 AM UTC 24 19440114 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1970629707 Sep 09 11:21:04 AM UTC 24 Sep 09 11:21:07 AM UTC 24 14495151 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1446347538 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:07 AM UTC 24 2728429351 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1700966703 Sep 09 11:20:59 AM UTC 24 Sep 09 11:21:08 AM UTC 24 161543375 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1735514510 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:08 AM UTC 24 179672482 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.886630606 Sep 09 11:21:04 AM UTC 24 Sep 09 11:21:08 AM UTC 24 98494917 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3755979155 Sep 09 11:21:00 AM UTC 24 Sep 09 11:21:09 AM UTC 24 649402868 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1938991265 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:10 AM UTC 24 517925958 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.1821667004 Sep 09 11:21:08 AM UTC 24 Sep 09 11:21:10 AM UTC 24 39597674 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.654951126 Sep 09 11:21:05 AM UTC 24 Sep 09 11:21:11 AM UTC 24 112469248 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.2207870631 Sep 09 11:21:01 AM UTC 24 Sep 09 11:21:11 AM UTC 24 1616996331 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3633785156 Sep 09 11:21:08 AM UTC 24 Sep 09 11:21:14 AM UTC 24 291120194 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1542697626 Sep 09 11:21:00 AM UTC 24 Sep 09 11:21:14 AM UTC 24 336414457 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2031583506 Sep 09 11:21:11 AM UTC 24 Sep 09 11:21:15 AM UTC 24 376091737 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2232700949 Sep 09 11:21:11 AM UTC 24 Sep 09 11:21:17 AM UTC 24 207106521 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2704675680 Sep 09 11:21:00 AM UTC 24 Sep 09 11:21:18 AM UTC 24 374152628 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3918108101 Sep 09 11:21:18 AM UTC 24 Sep 09 11:21:20 AM UTC 24 12872048 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1894495930 Sep 09 11:21:05 AM UTC 24 Sep 09 11:21:20 AM UTC 24 1173117872 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.76096685 Sep 09 11:21:07 AM UTC 24 Sep 09 11:21:21 AM UTC 24 320108995 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1729982502 Sep 09 11:21:19 AM UTC 24 Sep 09 11:21:21 AM UTC 24 16400297 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.270242302 Sep 09 11:21:10 AM UTC 24 Sep 09 11:21:21 AM UTC 24 1138528736 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3308261694 Sep 09 11:21:00 AM UTC 24 Sep 09 11:21:22 AM UTC 24 1792452141 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3194457996 Sep 09 11:21:20 AM UTC 24 Sep 09 11:21:22 AM UTC 24 14318950 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.4072576252 Sep 09 11:21:07 AM UTC 24 Sep 09 11:21:22 AM UTC 24 767691104 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.204129262 Sep 09 11:21:12 AM UTC 24 Sep 09 11:21:24 AM UTC 24 2104319786 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1665222240 Sep 09 11:21:23 AM UTC 24 Sep 09 11:21:25 AM UTC 24 11108630 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1282939680 Sep 09 11:21:21 AM UTC 24 Sep 09 11:21:25 AM UTC 24 230934882 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.3582830303 Sep 09 11:20:58 AM UTC 24 Sep 09 11:21:25 AM UTC 24 1334857809 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2503508964 Sep 09 11:21:00 AM UTC 24 Sep 09 11:21:26 AM UTC 24 1290436748 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3832217366 Sep 09 11:21:14 AM UTC 24 Sep 09 11:21:27 AM UTC 24 537299828 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3185023585 Sep 09 11:21:12 AM UTC 24 Sep 09 11:21:27 AM UTC 24 3445397938 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.120686995 Sep 09 11:21:01 AM UTC 24 Sep 09 11:21:29 AM UTC 24 752142184 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.3389280528 Sep 09 11:21:12 AM UTC 24 Sep 09 11:21:30 AM UTC 24 1767368176 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1328704618 Sep 09 11:21:10 AM UTC 24 Sep 09 11:21:32 AM UTC 24 1202926885 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1187766947 Sep 09 11:21:23 AM UTC 24 Sep 09 11:21:33 AM UTC 24 202298851 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.183548163 Sep 09 11:21:23 AM UTC 24 Sep 09 11:21:34 AM UTC 24 205524463 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1110884946 Sep 09 11:21:25 AM UTC 24 Sep 09 11:21:35 AM UTC 24 399836065 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.728021123 Sep 09 11:21:21 AM UTC 24 Sep 09 11:21:36 AM UTC 24 180200031 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2483563259 Sep 09 11:21:27 AM UTC 24 Sep 09 11:21:37 AM UTC 24 566908010 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.4130040040 Sep 09 11:21:23 AM UTC 24 Sep 09 11:21:37 AM UTC 24 1355305117 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.2742587501 Sep 09 11:21:35 AM UTC 24 Sep 09 11:21:37 AM UTC 24 238780339 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.525819677 Sep 09 11:21:36 AM UTC 24 Sep 09 11:21:38 AM UTC 24 14611609 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1238634376 Sep 09 11:21:28 AM UTC 24 Sep 09 11:21:39 AM UTC 24 325761993 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2958464371 Sep 09 11:21:30 AM UTC 24 Sep 09 11:21:39 AM UTC 24 233024195 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2910935180 Sep 09 11:21:35 AM UTC 24 Sep 09 11:21:39 AM UTC 24 50155722 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2649551946 Sep 09 11:21:26 AM UTC 24 Sep 09 11:21:40 AM UTC 24 2144614532 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.1579403699 Sep 09 11:21:26 AM UTC 24 Sep 09 11:21:42 AM UTC 24 2066390913 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3350936914 Sep 09 11:21:40 AM UTC 24 Sep 09 11:21:42 AM UTC 24 32878020 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.218268460 Sep 09 11:21:38 AM UTC 24 Sep 09 11:21:43 AM UTC 24 150316779 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.551396896 Sep 09 11:21:08 AM UTC 24 Sep 09 11:21:43 AM UTC 24 913583535 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3367826632 Sep 09 11:21:31 AM UTC 24 Sep 09 11:21:43 AM UTC 24 3226258650 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.2084222319 Sep 09 11:21:38 AM UTC 24 Sep 09 11:21:44 AM UTC 24 87322736 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2578804827 Sep 09 11:21:00 AM UTC 24 Sep 09 11:21:44 AM UTC 24 2947910454 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2713933164 Sep 09 11:21:28 AM UTC 24 Sep 09 11:21:45 AM UTC 24 2375715625 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1423785896 Sep 09 11:21:04 AM UTC 24 Sep 09 11:21:47 AM UTC 24 1232353006 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.995837947 Sep 09 11:21:23 AM UTC 24 Sep 09 11:21:47 AM UTC 24 2447268678 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3930067006 Sep 09 11:21:01 AM UTC 24 Sep 09 11:21:48 AM UTC 24 774241859 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1440349335 Sep 09 11:21:01 AM UTC 24 Sep 09 11:21:48 AM UTC 24 980842654 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3480437959 Sep 09 11:21:38 AM UTC 24 Sep 09 11:21:49 AM UTC 24 1701110946 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.3131937878 Sep 09 11:21:40 AM UTC 24 Sep 09 11:21:50 AM UTC 24 640508571 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.3887558442 Sep 09 11:21:45 AM UTC 24 Sep 09 11:21:51 AM UTC 24 737522429 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2426305169 Sep 09 11:21:49 AM UTC 24 Sep 09 11:21:52 AM UTC 24 46627796 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.869584646 Sep 09 11:21:51 AM UTC 24 Sep 09 11:21:53 AM UTC 24 19903123 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1541443531 Sep 09 11:21:16 AM UTC 24 Sep 09 11:21:53 AM UTC 24 260147032 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3613026823 Sep 09 11:21:50 AM UTC 24 Sep 09 11:21:53 AM UTC 24 118000841 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3791817529 Sep 09 11:21:44 AM UTC 24 Sep 09 11:21:54 AM UTC 24 2017234728 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2212863548 Sep 09 11:21:39 AM UTC 24 Sep 09 11:21:56 AM UTC 24 316280289 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.4141049269 Sep 09 11:21:55 AM UTC 24 Sep 09 11:21:57 AM UTC 24 95041958 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.2581909647 Sep 09 11:21:45 AM UTC 24 Sep 09 11:21:57 AM UTC 24 2363006655 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2135942764 Sep 09 11:21:45 AM UTC 24 Sep 09 11:21:58 AM UTC 24 658315154 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.4053587979 Sep 09 11:21:52 AM UTC 24 Sep 09 11:21:58 AM UTC 24 338513598 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.3888796529 Sep 09 11:21:53 AM UTC 24 Sep 09 11:21:58 AM UTC 24 52081389 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3621203695 Sep 09 11:21:44 AM UTC 24 Sep 09 11:21:59 AM UTC 24 309707624 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.4000134305 Sep 09 11:21:39 AM UTC 24 Sep 09 11:21:59 AM UTC 24 914530687 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.1623411906 Sep 09 11:21:44 AM UTC 24 Sep 09 11:22:00 AM UTC 24 506185170 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1878544980 Sep 09 11:21:45 AM UTC 24 Sep 09 11:22:00 AM UTC 24 315419831 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.2819948809 Sep 09 11:21:21 AM UTC 24 Sep 09 11:22:00 AM UTC 24 293479437 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2336565855 Sep 09 11:21:55 AM UTC 24 Sep 09 11:22:01 AM UTC 24 132990071 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.559027206 Sep 09 11:21:45 AM UTC 24 Sep 09 11:22:02 AM UTC 24 420053430 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1562119834 Sep 09 11:21:37 AM UTC 24 Sep 09 11:22:03 AM UTC 24 334944635 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3508693135 Sep 09 11:21:55 AM UTC 24 Sep 09 11:22:05 AM UTC 24 586605546 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1597573190 Sep 09 11:22:02 AM UTC 24 Sep 09 11:22:05 AM UTC 24 39499907 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.701853468 Sep 09 11:21:55 AM UTC 24 Sep 09 11:22:06 AM UTC 24 1010679515 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1204266853 Sep 09 11:21:59 AM UTC 24 Sep 09 11:22:06 AM UTC 24 1442742938 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1548537178 Sep 09 11:22:05 AM UTC 24 Sep 09 11:22:07 AM UTC 24 13615747 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.557397765 Sep 09 11:21:54 AM UTC 24 Sep 09 11:22:07 AM UTC 24 280704891 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.4280525540 Sep 09 11:22:04 AM UTC 24 Sep 09 11:22:08 AM UTC 24 95814730 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.4280937203 Sep 09 11:21:33 AM UTC 24 Sep 09 11:22:10 AM UTC 24 750994826 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.1694542667 Sep 09 11:21:58 AM UTC 24 Sep 09 11:22:11 AM UTC 24 322409659 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3636265272 Sep 09 11:22:08 AM UTC 24 Sep 09 11:22:11 AM UTC 24 18533484 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3807485085 Sep 09 11:22:07 AM UTC 24 Sep 09 11:22:12 AM UTC 24 184121619 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.1578054294 Sep 09 11:21:59 AM UTC 24 Sep 09 11:22:12 AM UTC 24 2427822889 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2587127233 Sep 09 11:22:06 AM UTC 24 Sep 09 11:22:13 AM UTC 24 202478647 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2417261503 Sep 09 11:22:01 AM UTC 24 Sep 09 11:22:14 AM UTC 24 481379757 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.193023046 Sep 09 11:22:01 AM UTC 24 Sep 09 11:22:15 AM UTC 24 293237330 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.370916817 Sep 09 11:22:12 AM UTC 24 Sep 09 11:22:16 AM UTC 24 782631197 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.752413280 Sep 09 11:21:10 AM UTC 24 Sep 09 11:22:17 AM UTC 24 17797552943 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2044475492 Sep 09 11:22:13 AM UTC 24 Sep 09 11:22:17 AM UTC 24 123250067 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3003154954 Sep 09 11:22:43 AM UTC 24 Sep 09 11:22:46 AM UTC 24 26614568 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3061825042 Sep 09 11:22:09 AM UTC 24 Sep 09 11:22:18 AM UTC 24 644471070 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.4214342393 Sep 09 11:22:18 AM UTC 24 Sep 09 11:22:20 AM UTC 24 35086574 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3613585564 Sep 09 11:22:14 AM UTC 24 Sep 09 11:22:20 AM UTC 24 213614982 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.4065375136 Sep 09 11:22:01 AM UTC 24 Sep 09 11:22:21 AM UTC 24 483900732 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.664885685 Sep 09 11:21:44 AM UTC 24 Sep 09 11:22:21 AM UTC 24 2145967516 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3448406463 Sep 09 11:22:19 AM UTC 24 Sep 09 11:22:22 AM UTC 24 47891800 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1421141711 Sep 09 11:21:52 AM UTC 24 Sep 09 11:22:22 AM UTC 24 333940591 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.1493356506 Sep 09 11:21:58 AM UTC 24 Sep 09 11:22:23 AM UTC 24 4826926932 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.244413532 Sep 09 11:22:21 AM UTC 24 Sep 09 11:22:23 AM UTC 24 11080296 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1813524423 Sep 09 11:20:59 AM UTC 24 Sep 09 11:22:24 AM UTC 24 33104583733 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.3293580171 Sep 09 11:22:27 AM UTC 24 Sep 09 11:22:46 AM UTC 24 637550308 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1180180617 Sep 09 11:21:58 AM UTC 24 Sep 09 11:22:24 AM UTC 24 565291613 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1712021981 Sep 09 11:22:07 AM UTC 24 Sep 09 11:22:25 AM UTC 24 755237589 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3031197893 Sep 09 11:22:07 AM UTC 24 Sep 09 11:22:26 AM UTC 24 412552215 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3841172062 Sep 09 11:22:15 AM UTC 24 Sep 09 11:22:26 AM UTC 24 216369527 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3983892332 Sep 09 11:21:26 AM UTC 24 Sep 09 11:22:26 AM UTC 24 7160546611 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.776877574 Sep 09 11:22:24 AM UTC 24 Sep 09 11:22:26 AM UTC 24 17948853 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.125377219 Sep 09 11:22:22 AM UTC 24 Sep 09 11:22:27 AM UTC 24 31464596 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.251237157 Sep 09 11:21:33 AM UTC 24 Sep 09 11:22:27 AM UTC 24 1450161491 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.1310418207 Sep 09 11:22:15 AM UTC 24 Sep 09 11:22:28 AM UTC 24 940942401 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.863445335 Sep 09 11:21:24 AM UTC 24 Sep 09 11:22:28 AM UTC 24 3283951393 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.2109803701 Sep 09 11:22:24 AM UTC 24 Sep 09 11:22:28 AM UTC 24 316818645 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2732692479 Sep 09 11:21:49 AM UTC 24 Sep 09 11:22:29 AM UTC 24 247818846 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.520332519 Sep 09 11:22:14 AM UTC 24 Sep 09 11:22:29 AM UTC 24 4973124483 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1568995925 Sep 09 11:22:12 AM UTC 24 Sep 09 11:22:30 AM UTC 24 791486319 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.2949452488 Sep 09 11:22:29 AM UTC 24 Sep 09 11:22:32 AM UTC 24 28215202 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.932359173 Sep 09 11:22:14 AM UTC 24 Sep 09 11:22:32 AM UTC 24 869291503 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.649713822 Sep 09 11:22:22 AM UTC 24 Sep 09 11:22:33 AM UTC 24 232339352 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2747231561 Sep 09 11:22:31 AM UTC 24 Sep 09 11:22:33 AM UTC 24 10892152 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.3131452064 Sep 09 11:22:06 AM UTC 24 Sep 09 11:22:33 AM UTC 24 263658847 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3311928756 Sep 09 11:22:29 AM UTC 24 Sep 09 11:22:34 AM UTC 24 49772524 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.870516832 Sep 09 11:22:24 AM UTC 24 Sep 09 11:22:35 AM UTC 24 250388571 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1062240079 Sep 09 11:22:37 AM UTC 24 Sep 09 11:22:45 AM UTC 24 800974935 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3543148728 Sep 09 11:22:08 AM UTC 24 Sep 09 11:22:35 AM UTC 24 1781610614 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1803305846 Sep 09 11:22:00 AM UTC 24 Sep 09 11:22:36 AM UTC 24 4788683441 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.1780730157 Sep 09 11:22:27 AM UTC 24 Sep 09 11:22:36 AM UTC 24 1799305566 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.4062349561 Sep 09 11:22:34 AM UTC 24 Sep 09 11:22:37 AM UTC 24 12325066 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3646493264 Sep 09 11:22:24 AM UTC 24 Sep 09 11:22:37 AM UTC 24 1090247859 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3662233312 Sep 09 11:22:33 AM UTC 24 Sep 09 11:22:37 AM UTC 24 69108683 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.473902727 Sep 09 11:22:28 AM UTC 24 Sep 09 11:22:38 AM UTC 24 770298195 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.768865375 Sep 09 11:22:02 AM UTC 24 Sep 09 11:22:39 AM UTC 24 2521958660 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3054846722 Sep 09 11:22:31 AM UTC 24 Sep 09 11:22:41 AM UTC 24 197936970 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2656225378 Sep 09 11:22:28 AM UTC 24 Sep 09 11:22:42 AM UTC 24 901441693 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1475525306 Sep 09 11:22:38 AM UTC 24 Sep 09 11:22:42 AM UTC 24 507115533 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2263387106 Sep 09 11:22:24 AM UTC 24 Sep 09 11:22:42 AM UTC 24 280383038 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1401904322 Sep 09 11:21:41 AM UTC 24 Sep 09 11:22:43 AM UTC 24 1359276383 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.781029071 Sep 09 11:22:27 AM UTC 24 Sep 09 11:22:43 AM UTC 24 1280423012 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.3599594043 Sep 09 11:22:34 AM UTC 24 Sep 09 11:22:44 AM UTC 24 4440198050 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2663125269 Sep 09 11:22:28 AM UTC 24 Sep 09 11:22:44 AM UTC 24 1975670255 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.833253220 Sep 09 11:22:28 AM UTC 24 Sep 09 11:22:45 AM UTC 24 600295276 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.2742852218 Sep 09 11:22:33 AM UTC 24 Sep 09 11:22:45 AM UTC 24 234357318 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2722913695 Sep 09 11:22:43 AM UTC 24 Sep 09 11:22:45 AM UTC 24 13486260 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.585453510 Sep 09 11:22:34 AM UTC 24 Sep 09 11:22:45 AM UTC 24 236049189 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1007483644 Sep 09 11:22:34 AM UTC 24 Sep 09 11:22:46 AM UTC 24 866880863 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.953803121 Sep 09 11:22:46 AM UTC 24 Sep 09 11:22:48 AM UTC 24 16026348 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4018819323 Sep 09 11:22:43 AM UTC 24 Sep 09 11:22:48 AM UTC 24 623837458 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3918072178 Sep 09 11:22:44 AM UTC 24 Sep 09 11:22:48 AM UTC 24 100828026 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.4177384064 Sep 09 11:22:21 AM UTC 24 Sep 09 11:22:49 AM UTC 24 239745681 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.324436375 Sep 09 11:22:39 AM UTC 24 Sep 09 11:22:51 AM UTC 24 2105395880 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3298556865 Sep 09 11:22:46 AM UTC 24 Sep 09 11:22:51 AM UTC 24 668256072 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3182377459 Sep 09 11:22:25 AM UTC 24 Sep 09 11:22:51 AM UTC 24 1024399049 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.2064539547 Sep 09 11:22:44 AM UTC 24 Sep 09 11:22:52 AM UTC 24 62995648 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.2567231002 Sep 09 11:22:49 AM UTC 24 Sep 09 11:22:53 AM UTC 24 116810600 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3571223231 Sep 09 11:22:47 AM UTC 24 Sep 09 11:22:54 AM UTC 24 1169770037 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1295832492 Sep 09 11:22:11 AM UTC 24 Sep 09 11:22:54 AM UTC 24 1641686519 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.437392655 Sep 09 11:22:38 AM UTC 24 Sep 09 11:22:55 AM UTC 24 729837132 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1315671089 Sep 09 11:22:47 AM UTC 24 Sep 09 11:22:55 AM UTC 24 363851200 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.2474880988 Sep 09 11:22:53 AM UTC 24 Sep 09 11:22:56 AM UTC 24 20722237 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1287731575 Sep 09 11:22:54 AM UTC 24 Sep 09 11:22:57 AM UTC 24 127692720 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1884844489 Sep 09 11:22:40 AM UTC 24 Sep 09 11:22:57 AM UTC 24 812669877 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2180661234 Sep 09 11:22:38 AM UTC 24 Sep 09 11:22:58 AM UTC 24 3684760925 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.901338764 Sep 09 11:22:37 AM UTC 24 Sep 09 11:22:58 AM UTC 24 1700744359 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2791484914 Sep 09 11:22:27 AM UTC 24 Sep 09 11:22:58 AM UTC 24 926766202 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3954203883 Sep 09 11:22:53 AM UTC 24 Sep 09 11:22:59 AM UTC 24 187654994 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3015451969 Sep 09 11:22:36 AM UTC 24 Sep 09 11:22:59 AM UTC 24 882347342 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1656171747 Sep 09 11:22:49 AM UTC 24 Sep 09 11:22:59 AM UTC 24 321640938 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.131310198 Sep 09 11:22:57 AM UTC 24 Sep 09 11:22:59 AM UTC 24 13543848 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1911175272 Sep 09 11:22:56 AM UTC 24 Sep 09 11:23:01 AM UTC 24 54668663 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1839752514 Sep 09 11:22:46 AM UTC 24 Sep 09 11:23:01 AM UTC 24 407354575 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3634424553 Sep 09 11:22:49 AM UTC 24 Sep 09 11:23:02 AM UTC 24 365055669 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.2697101236 Sep 09 11:22:31 AM UTC 24 Sep 09 11:23:03 AM UTC 24 1388390063 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1944836682 Sep 09 11:22:38 AM UTC 24 Sep 09 11:23:03 AM UTC 24 1893579597 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3980285779 Sep 09 11:22:45 AM UTC 24 Sep 09 11:23:04 AM UTC 24 2219536763 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2652184089 Sep 09 11:22:17 AM UTC 24 Sep 09 11:23:04 AM UTC 24 12657980341 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.305700044 Sep 09 11:22:13 AM UTC 24 Sep 09 11:23:05 AM UTC 24 6573708336 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3188968127 Sep 09 11:22:46 AM UTC 24 Sep 09 11:23:06 AM UTC 24 408226417 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3735087896 Sep 09 11:23:04 AM UTC 24 Sep 09 11:23:06 AM UTC 24 115330264 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3510062869 Sep 09 11:22:52 AM UTC 24 Sep 09 11:23:06 AM UTC 24 1370028011 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.1533326674 Sep 09 11:22:58 AM UTC 24 Sep 09 11:23:06 AM UTC 24 223043910 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.313018228 Sep 09 11:22:56 AM UTC 24 Sep 09 11:23:07 AM UTC 24 91286054 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1307495704 Sep 09 11:22:44 AM UTC 24 Sep 09 11:23:07 AM UTC 24 433836272 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1867529301 Sep 09 11:22:56 AM UTC 24 Sep 09 11:23:07 AM UTC 24 280805763 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.39030396 Sep 09 11:23:05 AM UTC 24 Sep 09 11:23:08 AM UTC 24 12818940 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.537951317 Sep 09 11:22:56 AM UTC 24 Sep 09 11:23:08 AM UTC 24 237527028 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3118301699 Sep 09 11:22:47 AM UTC 24 Sep 09 11:23:09 AM UTC 24 482490151 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.747487723 Sep 09 11:21:15 AM UTC 24 Sep 09 11:23:09 AM UTC 24 55483723425 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.185266219 Sep 09 11:23:05 AM UTC 24 Sep 09 11:23:09 AM UTC 24 70958891 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3389085726 Sep 09 11:23:07 AM UTC 24 Sep 09 11:23:10 AM UTC 24 36922538 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3232014656 Sep 09 11:23:00 AM UTC 24 Sep 09 11:23:12 AM UTC 24 863933631 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3109050029 Sep 09 11:22:25 AM UTC 24 Sep 09 11:23:12 AM UTC 24 2468965133 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2066021609 Sep 09 11:23:00 AM UTC 24 Sep 09 11:23:12 AM UTC 24 881194430 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3506924080 Sep 09 11:22:38 AM UTC 24 Sep 09 11:23:12 AM UTC 24 3254791384 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1576322483 Sep 09 11:23:01 AM UTC 24 Sep 09 11:23:13 AM UTC 24 487139896 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2600300848 Sep 09 11:22:57 AM UTC 24 Sep 09 11:23:13 AM UTC 24 457915230 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.2894479326 Sep 09 11:23:08 AM UTC 24 Sep 09 11:23:14 AM UTC 24 121178701 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4164009374 Sep 09 11:23:13 AM UTC 24 Sep 09 11:23:16 AM UTC 24 30670037 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3308407083 Sep 09 11:23:13 AM UTC 24 Sep 09 11:23:16 AM UTC 24 86972804 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.874791229 Sep 09 11:21:48 AM UTC 24 Sep 09 11:23:16 AM UTC 24 3877530617 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.781585539 Sep 09 11:23:03 AM UTC 24 Sep 09 11:23:17 AM UTC 24 253920893 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2396645969 Sep 09 11:21:32 AM UTC 24 Sep 09 11:23:17 AM UTC 24 4338866734 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2520993446 Sep 09 11:21:57 AM UTC 24 Sep 09 11:23:18 AM UTC 24 11216299582 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2905443661 Sep 09 11:23:13 AM UTC 24 Sep 09 11:23:18 AM UTC 24 335638126 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3725668059 Sep 09 11:23:06 AM UTC 24 Sep 09 11:23:19 AM UTC 24 65353890 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1778361960 Sep 09 11:23:14 AM UTC 24 Sep 09 11:23:19 AM UTC 24 50931162 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.3384093530 Sep 09 11:23:17 AM UTC 24 Sep 09 11:23:22 AM UTC 24 115687171 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1290733359 Sep 09 11:23:10 AM UTC 24 Sep 09 11:23:22 AM UTC 24 540223838 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3050861742 Sep 09 11:23:01 AM UTC 24 Sep 09 11:23:22 AM UTC 24 520068076 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.324749706 Sep 09 11:23:10 AM UTC 24 Sep 09 11:23:22 AM UTC 24 1481854618 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.394962049 Sep 09 11:23:08 AM UTC 24 Sep 09 11:23:23 AM UTC 24 958019860 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3624944100 Sep 09 11:22:49 AM UTC 24 Sep 09 11:23:23 AM UTC 24 18428316112 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1959984205 Sep 09 11:23:07 AM UTC 24 Sep 09 11:23:23 AM UTC 24 290077403 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3834680342 Sep 09 11:23:13 AM UTC 24 Sep 09 11:23:23 AM UTC 24 63184913 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1493992051 Sep 09 11:23:08 AM UTC 24 Sep 09 11:23:23 AM UTC 24 1014140761 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2179955598 Sep 09 11:22:54 AM UTC 24 Sep 09 11:23:24 AM UTC 24 666179460 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1168639562 Sep 09 11:23:08 AM UTC 24 Sep 09 11:23:24 AM UTC 24 1556747648 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.239505221 Sep 09 11:23:00 AM UTC 24 Sep 09 11:23:25 AM UTC 24 5524908823 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3847993846 Sep 09 11:23:10 AM UTC 24 Sep 09 11:23:25 AM UTC 24 722162464 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.3874006918 Sep 09 11:23:23 AM UTC 24 Sep 09 11:23:25 AM UTC 24 39021604 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.77840832 Sep 09 11:23:00 AM UTC 24 Sep 09 11:23:26 AM UTC 24 12386027584 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.70756080 Sep 09 11:23:10 AM UTC 24 Sep 09 11:23:27 AM UTC 24 487119145 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.799913817 Sep 09 11:23:25 AM UTC 24 Sep 09 11:23:27 AM UTC 24 43116657 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.4010216504 Sep 09 11:23:25 AM UTC 24 Sep 09 11:23:29 AM UTC 24 161165693 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3861439372 Sep 09 11:23:17 AM UTC 24 Sep 09 11:23:32 AM UTC 24 839040233 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3863802824 Sep 09 11:21:48 AM UTC 24 Sep 09 11:23:28 AM UTC 24 11340572461 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.765208929 Sep 09 11:23:25 AM UTC 24 Sep 09 11:23:30 AM UTC 24 61247658 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1961622967 Sep 09 11:23:00 AM UTC 24 Sep 09 11:23:30 AM UTC 24 18303387816 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.449331687 Sep 09 11:23:17 AM UTC 24 Sep 09 11:23:30 AM UTC 24 264564227 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.3502596537 Sep 09 11:23:21 AM UTC 24 Sep 09 11:23:31 AM UTC 24 570056649 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.2449233450 Sep 09 11:23:18 AM UTC 24 Sep 09 11:23:31 AM UTC 24 819207564 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.1636823968 Sep 09 11:23:26 AM UTC 24 Sep 09 11:23:32 AM UTC 24 159631108 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.4116244589 Sep 09 11:23:25 AM UTC 24 Sep 09 11:23:34 AM UTC 24 121469775 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.153024792 Sep 09 11:23:31 AM UTC 24 Sep 09 11:23:34 AM UTC 24 64794989 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.275332545 Sep 09 11:23:32 AM UTC 24 Sep 09 11:23:34 AM UTC 24 23154405 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.3670966813 Sep 09 11:23:27 AM UTC 24 Sep 09 11:23:35 AM UTC 24 1586755146 ps