Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58223025

1

T1

1280

T2

2192

T3

10124

auto[1]

1105383

1

T2

99

T4

297

T13

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58210314

1

T1

1280

T2

1994

T3

10124

auto[1]

1118094

1

T2

297

T4

297

T13

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5109571	1			T1	108		T2	464		T3	865
auto[IdleSt]	15006547	1			T1	68		T2	1078		T3	256
auto[ClkMuxSt]	27938	1			T1	1		T2	4		T3	10
auto[CntIncrSt]	27794	1			T1	1		T2	4		T3	10
auto[CntProgSt]	1773206	1			T1	3		T2	36		T3	337
auto[TransCheckSt]	22056	1			T1	1		T3	10		T4	8
auto[TokenHashSt]	17444352	1			T1	271		T3	7538		T4	151
auto[FlashRmaSt]	27334	1			T3	10		T4	33		T5	53
auto[TokenCheck0St]	9829	1			T3	10		T4	8		T5	20
auto[TokenCheck1St]	7110	1			T3	10		T4	8		T5	20
auto[TransProgSt]	453530	1			T3	370		T4	200		T5	40
auto[PostTransSt]	8520224	1			T1	827		T2	235		T3	698
auto[ScrapSt]	156558	1			T15	8		T18	199		T43	38
auto[EscalateSt]	4378144	1			T2	470		T4	1591		T13	1126
auto[InvalidSt]	6362804	1			T4	1140		T17	1036		T26	18407

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1411	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6362804	1			T4	1140		T17	1036		T26	18407
EscalateSt	4378144	1			T2	470		T4	1591		T13	1126
ScrapSt	156558	1			T15	8		T18	199		T43	38
PostTransSt	8520224	1			T1	827		T2	235		T3	698
TransProgSt	453530	1			T3	370		T4	200		T5	40
TokenCheck1St	7110	1			T3	10		T4	8		T5	20
TokenCheck0St	9829	1			T3	10		T4	8		T5	20
FlashRmaSt	27334	1			T3	10		T4	33		T5	53
TokenHashSt	17444352	1			T1	271		T3	7538		T4	151
TransCheckSt	22056	1			T1	1		T3	10		T4	8
CntProgSt	1773206	1			T1	3		T2	36		T3	337
CntIncrSt	27794	1			T1	1		T2	4		T3	10
ClkMuxSt	27938	1			T1	1		T2	4		T3	10
IdleSt	15006547	1			T1	68		T2	1078		T3	256
ResetSt	5109571	1			T1	108		T2	464		T3	865
arcs[ResetSt=>IdleSt]	41351	1			T1	1		T2	5		T3	10
arcs[IdleSt=>ScrapSt]	238	1			T15	2		T18	3		T43	1
arcs[IdleSt=>ClkMuxSt]	27830	1			T1	1		T2	4		T3	10
arcs[ClkMuxSt=>CntIncrSt]	27794	1			T1	1		T2	4		T3	10
arcs[CntIncrSt=>PostTransSt]	1222	1			T13	11		T11	11		T25	19
arcs[CntIncrSt=>CntProgSt]	26509	1			T1	1		T2	4		T3	10
arcs[CntProgSt=>PostTransSt]	3502	1			T2	4		T13	9		T10	18
arcs[CntProgSt=>TransCheckSt]	22056	1			T1	1		T3	10		T4	8
arcs[TransCheckSt=>PostTransSt]	3115	1			T13	9		T11	7		T23	35
arcs[TransCheckSt=>TokenHashSt]	18839	1			T1	1		T3	10		T4	8
arcs[TokenHashSt=>PostTransSt]	8151	1			T1	1		T13	17		T11	21
arcs[TokenHashSt=>FlashRmaSt]	9857	1			T3	10		T4	8		T5	20
arcs[FlashRmaSt=>TokenCheck0St]	9829	1			T3	10		T4	8		T5	20
arcs[TokenCheck0St=>PostTransSt]	2660	1			T13	7		T11	3		T17	7
arcs[TokenCheck0St=>TokenCheck1St]	7110	1			T3	10		T4	8		T5	20
arcs[TokenCheck1St=>PostTransSt]	581	1			T13	1		T23	10		T19	7
arcs[TransProgSt=>PostTransSt]	5781	1			T3	10		T4	8		T5	20
arcs[IdleSt=>EscalateSt]	179	1			T15	2		T55	6		T20	3
arcs[ClkMuxSt=>EscalateSt]	36	1			T15	2		T55	3		T56	1
arcs[CntIncrSt=>EscalateSt]	63	1			T55	1		T20	2		T57	3
arcs[CntProgSt=>EscalateSt]	951	1			T15	19		T55	37		T20	20
arcs[TransCheckSt=>EscalateSt]	102	1			T57	1		T65	1		T59	5
arcs[TokenHashSt=>EscalateSt]	831	1			T15	9		T55	6		T25	2
arcs[FlashRmaSt=>EscalateSt]	28	1			T55	1		T58	1		T59	1
arcs[TokenCheck0St=>EscalateSt]	59	1			T15	2		T55	3		T20	1
arcs[TokenCheck1St=>EscalateSt]	23	1			T56	1		T63	2		T64	2
arcs[TransProgSt=>EscalateSt]	725	1			T15	10		T55	26		T20	22
arcs[PostTransSt=>EscalateSt]	3858	1			T2	4		T13	9		T10	18
arcs[InvalidSt=>EscalateSt]	9893	1			T4	6		T17	14		T26	8

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5109408	1			T1	108		T2	464		T3	865
auto[0]	auto[IdleSt]	15006434	1			T1	68		T2	1078		T3	256
auto[0]	auto[ClkMuxSt]	27917	1			T1	1		T2	4		T3	10
auto[0]	auto[CntIncrSt]	27746	1			T1	1		T2	4		T3	10
auto[0]	auto[CntProgSt]	1772601	1			T1	3		T2	36		T3	337
auto[0]	auto[TransCheckSt]	21984	1			T1	1		T3	10		T4	8
auto[0]	auto[TokenHashSt]	17443794	1			T1	271		T3	7538		T4	151
auto[0]	auto[FlashRmaSt]	27316	1			T3	10		T4	33		T5	53
auto[0]	auto[TokenCheck0St]	9787	1			T3	10		T4	8		T5	20
auto[0]	auto[TokenCheck1St]	7090	1			T3	10		T4	8		T5	20
auto[0]	auto[TransProgSt]	453056	1			T3	370		T4	200		T5	40
auto[0]	auto[PostTransSt]	8518239	1			T1	827		T2	234		T3	698
auto[0]	auto[ScrapSt]	156510	1			T15	7		T18	199		T43	38
auto[0]	auto[EscalateSt]	3281833	1			T2	372		T4	1297		T13	636
auto[0]	auto[InvalidSt]	6357899	1			T4	1137		T17	1028		T26	18403
auto[1]	auto[ResetSt]	163	1			T15	1		T55	3		T20	3
auto[1]	auto[IdleSt]	113	1			T15	2		T55	6		T20	2
auto[1]	auto[ClkMuxSt]	21	1			T15	1		T55	2		T56	1
auto[1]	auto[CntIncrSt]	48	1			T20	2		T57	2		T56	1
auto[1]	auto[CntProgSt]	605	1			T15	11		T55	21		T20	13
auto[1]	auto[TransCheckSt]	72	1			T57	1		T59	2		T238	1
auto[1]	auto[TokenHashSt]	558	1			T15	5		T55	5		T20	6
auto[1]	auto[FlashRmaSt]	18	1			T58	1		T239	1		T240	1
auto[1]	auto[TokenCheck0St]	42	1			T55	2		T20	1		T241	1
auto[1]	auto[TokenCheck1St]	20	1			T56	1		T63	2		T64	2
auto[1]	auto[TransProgSt]	474	1			T15	5		T55	19		T20	17
auto[1]	auto[PostTransSt]	1985	1			T2	1		T13	5		T10	12
auto[1]	auto[ScrapSt]	48	1			T15	1		T55	3		T20	2
auto[1]	auto[EscalateSt]	1096311	1			T2	98		T4	294		T13	490
auto[1]	auto[InvalidSt]	4905	1			T4	3		T17	8		T26	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5109402	1			T1	108		T2	464		T3	865
auto[0]	auto[IdleSt]	15006420	1			T1	68		T2	1078		T3	256
auto[0]	auto[ClkMuxSt]	27913	1			T1	1		T2	4		T3	10
auto[0]	auto[CntIncrSt]	27754	1			T1	1		T2	4		T3	10
auto[0]	auto[CntProgSt]	1772582	1			T1	3		T2	36		T3	337
auto[0]	auto[TransCheckSt]	21992	1			T1	1		T3	10		T4	8
auto[0]	auto[TokenHashSt]	17443814	1			T1	271		T3	7538		T4	151
auto[0]	auto[FlashRmaSt]	27318	1			T3	10		T4	33		T5	53
auto[0]	auto[TokenCheck0St]	9787	1			T3	10		T4	8		T5	20
auto[0]	auto[TokenCheck1St]	7094	1			T3	10		T4	8		T5	20
auto[0]	auto[TransProgSt]	453037	1			T3	370		T4	200		T5	40
auto[0]	auto[PostTransSt]	8518241	1			T1	827		T2	232		T3	698
auto[0]	auto[ScrapSt]	156515	1			T15	7		T18	199		T43	38
auto[0]	auto[EscalateSt]	3269218	1			T2	176		T4	1297		T13	734
auto[0]	auto[InvalidSt]	6357816	1			T4	1137		T17	1030		T26	18403
auto[1]	auto[ResetSt]	169	1			T15	5		T55	6		T20	4
auto[1]	auto[IdleSt]	127	1			T15	1		T55	3		T20	3
auto[1]	auto[ClkMuxSt]	25	1			T15	1		T55	2		T242	1
auto[1]	auto[CntIncrSt]	40	1			T55	1		T20	1		T57	2
auto[1]	auto[CntProgSt]	624	1			T15	13		T55	27		T20	12
auto[1]	auto[TransCheckSt]	64	1			T65	1		T59	3		T243	8
auto[1]	auto[TokenHashSt]	538	1			T15	6		T55	5		T25	2
auto[1]	auto[FlashRmaSt]	16	1			T55	1		T59	1		T239	1
auto[1]	auto[TokenCheck0St]	42	1			T15	2		T55	2		T241	3
auto[1]	auto[TokenCheck1St]	16	1			T63	1		T64	2		T244	1
auto[1]	auto[TransProgSt]	493	1			T15	7		T55	15		T20	12
auto[1]	auto[PostTransSt]	1983	1			T2	3		T13	4		T10	6
auto[1]	auto[ScrapSt]	43	1			T15	1		T55	2		T20	1
auto[1]	auto[EscalateSt]	1108926	1			T2	294		T4	294		T13	392
auto[1]	auto[InvalidSt]	4988	1			T4	3		T17	6		T26	4