Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 97.92 95.29 93.40 100.00 98.52 99.00 96.11


Total tests in report: 1001
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.51 67.51 81.23 81.23 45.84 45.84 62.25 62.25 57.14 57.14 80.51 80.51 92.04 92.04 53.53 53.53 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.3785648860
80.27 12.76 88.84 7.61 74.68 28.84 78.54 16.30 73.81 16.67 89.62 9.11 94.03 1.99 62.37 8.83 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4161342466
83.79 3.52 95.43 6.60 76.25 1.57 80.40 1.86 78.57 4.76 91.95 2.33 94.28 0.25 69.61 7.24 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.327570499
85.74 1.95 96.50 1.07 82.35 6.10 83.19 2.78 78.57 0.00 93.22 1.27 94.78 0.50 71.55 1.94 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.4005858423
87.35 1.61 96.55 0.05 83.36 1.02 86.06 2.87 80.95 2.38 94.49 1.27 94.78 0.00 75.27 3.71 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3939509571
88.70 1.35 96.60 0.05 85.30 1.94 86.15 0.09 80.95 0.00 94.70 0.21 96.27 1.49 80.92 5.65 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.4210139757
89.95 1.25 96.60 0.00 85.30 0.00 86.15 0.00 88.10 7.14 94.70 0.00 96.27 0.00 82.51 1.59 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2842973213
90.80 0.85 96.75 0.15 85.77 0.46 86.72 0.57 90.48 2.38 95.34 0.64 96.27 0.00 84.28 1.77 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1555241539
91.62 0.82 96.85 0.10 86.51 0.74 87.35 0.63 92.86 2.38 95.76 0.42 96.52 0.25 85.51 1.24 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2744853083
92.27 0.65 96.96 0.10 88.54 2.03 87.47 0.12 92.86 0.00 96.19 0.42 96.77 0.25 87.10 1.59 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.4265975888
92.83 0.56 96.96 0.00 88.54 0.00 89.90 2.43 92.86 0.00 96.19 0.00 97.01 0.25 88.34 1.24 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1449066815
93.27 0.44 96.96 0.00 88.54 0.00 89.90 0.00 95.24 2.38 96.19 0.00 97.01 0.00 89.05 0.71 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1515341431
93.70 0.43 96.96 0.00 88.54 0.00 90.22 0.32 95.24 0.00 96.40 0.21 97.01 0.00 91.52 2.47 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.4278319215
94.12 0.42 97.11 0.15 89.83 1.29 90.22 0.00 95.24 0.00 96.82 0.42 97.01 0.00 92.58 1.06 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2344131617
94.46 0.34 97.11 0.00 89.83 0.00 90.22 0.00 97.62 2.38 96.82 0.00 97.01 0.00 92.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.893995863
94.80 0.34 97.11 0.00 89.83 0.00 90.22 0.00 100.00 2.38 96.82 0.00 97.01 0.00 92.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2798931511
95.09 0.29 97.31 0.20 90.20 0.37 90.22 0.00 100.00 0.00 97.25 0.42 97.01 0.00 93.64 1.06 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.3270516434
95.35 0.26 97.31 0.00 90.20 0.00 91.83 1.61 100.00 0.00 97.46 0.21 97.01 0.00 93.64 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1355196540
95.60 0.25 97.36 0.05 91.13 0.92 91.83 0.00 100.00 0.00 97.88 0.42 97.01 0.00 93.99 0.35 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1474306584
95.81 0.21 97.36 0.00 91.13 0.00 91.83 0.00 100.00 0.00 97.88 0.00 98.51 1.49 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2110923022
96.02 0.21 97.72 0.36 92.05 0.92 92.00 0.17 100.00 0.00 97.88 0.00 98.51 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.864302033
96.16 0.14 97.72 0.00 92.70 0.65 92.00 0.00 100.00 0.00 97.88 0.00 98.51 0.00 94.35 0.35 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3717857527
96.29 0.13 97.72 0.00 92.70 0.00 92.71 0.71 100.00 0.00 97.88 0.00 98.51 0.00 94.52 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.3140633078
96.41 0.12 97.72 0.00 93.53 0.83 92.71 0.00 100.00 0.00 97.88 0.00 98.51 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2985036039
96.52 0.11 97.82 0.10 93.81 0.28 92.71 0.00 100.00 0.00 98.31 0.42 98.51 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1835635188
96.63 0.10 97.92 0.10 93.81 0.00 92.77 0.06 100.00 0.00 98.52 0.21 98.51 0.00 94.88 0.35 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3802320155
96.69 0.06 97.92 0.00 94.09 0.28 92.77 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3738209219
96.76 0.06 97.92 0.00 94.09 0.00 93.22 0.45 100.00 0.00 98.52 0.00 98.51 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.476086819
96.80 0.04 97.92 0.00 94.09 0.00 93.34 0.12 100.00 0.00 98.52 0.00 98.51 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2246989880
96.84 0.04 97.92 0.00 94.09 0.00 93.34 0.00 100.00 0.00 98.52 0.00 98.76 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1913212843
96.87 0.04 97.92 0.00 94.09 0.00 93.34 0.00 100.00 0.00 98.52 0.00 99.00 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.936648377
96.90 0.03 97.92 0.00 94.09 0.00 93.36 0.02 100.00 0.00 98.52 0.00 99.00 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.685178139
96.93 0.03 97.92 0.00 94.27 0.18 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2634767114
96.95 0.03 97.92 0.00 94.45 0.18 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2529675229
96.98 0.03 97.92 0.00 94.64 0.18 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1273624961
97.00 0.03 97.92 0.00 94.82 0.18 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2791326042
97.03 0.03 97.92 0.00 95.01 0.18 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1266425155
97.06 0.03 97.92 0.00 95.01 0.00 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1388983412
97.08 0.03 97.92 0.00 95.01 0.00 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.11167560
97.11 0.03 97.92 0.00 95.01 0.00 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1979154454
97.13 0.03 97.92 0.00 95.01 0.00 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.1082063009
97.15 0.01 97.92 0.00 95.10 0.09 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2398674422
97.16 0.01 97.92 0.00 95.19 0.09 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2568641020
97.17 0.01 97.92 0.00 95.29 0.09 93.36 0.00 100.00 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2838150834
97.18 0.01 97.92 0.00 95.29 0.00 93.40 0.04 100.00 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.4076206919

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1438596089
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3558588389
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2716922492
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4214533620
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.888841397
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.478481359
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4201302912
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3330029204
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.71530055
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3848996854
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3995898474
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3451765603
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.258995548
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1693708004
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.4098491575
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2766704489
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1116756591
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.103490309
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2128903163
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1617564041
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3538755127
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3598179503
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1121662091
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2350053595
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.629372049
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2692617812
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.650661869
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3453945150
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.687182233
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.933114489
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1828956347
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1073502611
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2132784033
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2730483420
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1276115660
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1077506277
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1062510879
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.301424822
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.243865824
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.92372320
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.411162486
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.984125849
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3105983861
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4273338714
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2881725775
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Total test records in report: 1001
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1388983412 Sep 11 08:01:50 AM UTC 24 Sep 11 08:01:52 AM UTC 24 53427878 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3802320155 Sep 11 08:01:51 AM UTC 24 Sep 11 08:01:55 AM UTC 24 23398192 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2882151798 Sep 11 08:01:48 AM UTC 24 Sep 11 08:01:57 AM UTC 24 421880172 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.955315517 Sep 11 08:01:56 AM UTC 24 Sep 11 08:01:58 AM UTC 24 34838647 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.4278319215 Sep 11 08:01:50 AM UTC 24 Sep 11 08:02:02 AM UTC 24 91202856 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.259525867 Sep 11 08:01:57 AM UTC 24 Sep 11 08:02:06 AM UTC 24 4538788365 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1850733436 Sep 11 08:01:51 AM UTC 24 Sep 11 08:02:12 AM UTC 24 565027647 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.542680650 Sep 11 08:01:55 AM UTC 24 Sep 11 08:02:12 AM UTC 24 923356651 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.3785648860 Sep 11 08:01:53 AM UTC 24 Sep 11 08:02:12 AM UTC 24 311491397 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3373368472 Sep 11 08:02:09 AM UTC 24 Sep 11 08:02:14 AM UTC 24 2958114509 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.4265975888 Sep 11 08:02:06 AM UTC 24 Sep 11 08:02:16 AM UTC 24 476270997 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.864302033 Sep 11 08:02:23 AM UTC 24 Sep 11 08:02:26 AM UTC 24 58165278 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.950731447 Sep 11 08:02:00 AM UTC 24 Sep 11 08:02:26 AM UTC 24 577263205 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4161342466 Sep 11 08:02:02 AM UTC 24 Sep 11 08:02:26 AM UTC 24 1193717678 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.327570499 Sep 11 08:02:13 AM UTC 24 Sep 11 08:02:27 AM UTC 24 689131236 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.1316403899 Sep 11 08:02:14 AM UTC 24 Sep 11 08:02:27 AM UTC 24 240972384 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2859037177 Sep 11 08:02:26 AM UTC 24 Sep 11 08:02:28 AM UTC 24 27852993 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2246989880 Sep 11 08:01:59 AM UTC 24 Sep 11 08:02:30 AM UTC 24 3126734108 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.746374938 Sep 11 08:02:25 AM UTC 24 Sep 11 08:02:31 AM UTC 24 477839610 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.552873261 Sep 11 08:02:27 AM UTC 24 Sep 11 08:02:32 AM UTC 24 1063724061 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.952050275 Sep 11 08:02:31 AM UTC 24 Sep 11 08:02:33 AM UTC 24 25879689 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1555241539 Sep 11 08:02:13 AM UTC 24 Sep 11 08:02:34 AM UTC 24 940551297 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1985846224 Sep 11 08:02:32 AM UTC 24 Sep 11 08:02:35 AM UTC 24 41932657 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1418610689 Sep 11 08:02:28 AM UTC 24 Sep 11 08:02:36 AM UTC 24 98440824 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.3235867142 Sep 11 08:02:30 AM UTC 24 Sep 11 08:02:40 AM UTC 24 1594932758 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.3140633078 Sep 11 08:01:50 AM UTC 24 Sep 11 08:02:43 AM UTC 24 1564309687 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.4005858423 Sep 11 08:03:23 AM UTC 24 Sep 11 08:03:36 AM UTC 24 1099532189 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.2768659846 Sep 11 08:02:35 AM UTC 24 Sep 11 08:02:45 AM UTC 24 1092449816 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.585609396 Sep 11 08:02:13 AM UTC 24 Sep 11 08:02:45 AM UTC 24 1224091992 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2151487838 Sep 11 08:02:37 AM UTC 24 Sep 11 08:02:46 AM UTC 24 4813495813 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3223002004 Sep 11 08:02:30 AM UTC 24 Sep 11 08:02:47 AM UTC 24 947802506 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2379590623 Sep 11 08:02:41 AM UTC 24 Sep 11 08:02:47 AM UTC 24 744168596 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.893722900 Sep 11 08:02:48 AM UTC 24 Sep 11 08:02:51 AM UTC 24 54027599 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.434371180 Sep 11 08:02:49 AM UTC 24 Sep 11 08:02:52 AM UTC 24 31039183 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2777676239 Sep 11 08:02:28 AM UTC 24 Sep 11 08:02:53 AM UTC 24 612700051 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2971107813 Sep 11 08:02:45 AM UTC 24 Sep 11 08:02:54 AM UTC 24 590755750 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.466450616 Sep 11 08:02:48 AM UTC 24 Sep 11 08:02:55 AM UTC 24 325452763 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.4039452 Sep 11 08:02:34 AM UTC 24 Sep 11 08:02:58 AM UTC 24 668397727 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.448063810 Sep 11 08:02:54 AM UTC 24 Sep 11 08:02:59 AM UTC 24 80354713 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1901510369 Sep 11 08:02:45 AM UTC 24 Sep 11 08:02:59 AM UTC 24 437954082 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2000364139 Sep 11 08:02:53 AM UTC 24 Sep 11 08:02:59 AM UTC 24 85890732 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3939509571 Sep 11 08:01:58 AM UTC 24 Sep 11 08:03:02 AM UTC 24 3037235090 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3943171021 Sep 11 08:02:59 AM UTC 24 Sep 11 08:03:02 AM UTC 24 12662211 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.358876911 Sep 11 08:02:59 AM UTC 24 Sep 11 08:03:07 AM UTC 24 810543267 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3085012424 Sep 11 08:02:55 AM UTC 24 Sep 11 08:03:09 AM UTC 24 407822687 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1628396116 Sep 11 08:02:43 AM UTC 24 Sep 11 08:03:10 AM UTC 24 3146782875 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.2904806803 Sep 11 08:03:03 AM UTC 24 Sep 11 08:03:12 AM UTC 24 747718520 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3819842426 Sep 11 08:02:56 AM UTC 24 Sep 11 08:03:13 AM UTC 24 894741543 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1413044120 Sep 11 08:03:07 AM UTC 24 Sep 11 08:03:13 AM UTC 24 320956769 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1961454521 Sep 11 08:02:43 AM UTC 24 Sep 11 08:03:14 AM UTC 24 928885561 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.480244481 Sep 11 08:02:27 AM UTC 24 Sep 11 08:03:15 AM UTC 24 213207959 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3233052808 Sep 11 08:03:38 AM UTC 24 Sep 11 08:03:54 AM UTC 24 1556486002 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.3270516434 Sep 11 08:02:55 AM UTC 24 Sep 11 08:03:18 AM UTC 24 1288045572 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3345591520 Sep 11 08:03:16 AM UTC 24 Sep 11 08:03:19 AM UTC 24 16470573 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1736216975 Sep 11 08:03:01 AM UTC 24 Sep 11 08:03:19 AM UTC 24 390904923 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2744853083 Sep 11 08:02:18 AM UTC 24 Sep 11 08:03:20 AM UTC 24 876105581 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.340900655 Sep 11 08:02:36 AM UTC 24 Sep 11 08:03:20 AM UTC 24 6173462527 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.354926504 Sep 11 08:03:05 AM UTC 24 Sep 11 08:03:21 AM UTC 24 404079495 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2002527974 Sep 11 08:03:12 AM UTC 24 Sep 11 08:03:22 AM UTC 24 179630959 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.248061020 Sep 11 08:03:20 AM UTC 24 Sep 11 08:03:22 AM UTC 24 197010830 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2429226693 Sep 11 08:03:20 AM UTC 24 Sep 11 08:03:23 AM UTC 24 66894749 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.3721799306 Sep 11 08:03:21 AM UTC 24 Sep 11 08:03:25 AM UTC 24 383148172 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3937200797 Sep 11 08:03:24 AM UTC 24 Sep 11 08:03:26 AM UTC 24 13144654 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1079388567 Sep 11 08:03:13 AM UTC 24 Sep 11 08:03:26 AM UTC 24 994499383 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3353316885 Sep 11 08:03:10 AM UTC 24 Sep 11 08:03:29 AM UTC 24 677296602 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.3202716252 Sep 11 08:03:26 AM UTC 24 Sep 11 08:03:29 AM UTC 24 285145757 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1835635188 Sep 11 08:03:11 AM UTC 24 Sep 11 08:03:29 AM UTC 24 425073218 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.4054533818 Sep 11 08:03:23 AM UTC 24 Sep 11 08:03:32 AM UTC 24 428567001 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1432428159 Sep 11 08:03:21 AM UTC 24 Sep 11 08:03:37 AM UTC 24 68631763 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.435662543 Sep 11 08:03:32 AM UTC 24 Sep 11 08:03:37 AM UTC 24 317126220 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2850846068 Sep 11 08:02:47 AM UTC 24 Sep 11 08:03:38 AM UTC 24 1231471679 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.991110974 Sep 11 08:03:30 AM UTC 24 Sep 11 08:03:45 AM UTC 24 1990930748 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.390323022 Sep 11 08:03:37 AM UTC 24 Sep 11 08:03:46 AM UTC 24 203580707 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1461505587 Sep 11 08:03:22 AM UTC 24 Sep 11 08:03:48 AM UTC 24 791155065 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1408159792 Sep 11 08:03:47 AM UTC 24 Sep 11 08:03:50 AM UTC 24 110298729 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.2694415304 Sep 11 08:03:49 AM UTC 24 Sep 11 08:03:51 AM UTC 24 51900531 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2526759877 Sep 11 08:03:03 AM UTC 24 Sep 11 08:03:52 AM UTC 24 1531650148 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3959237692 Sep 11 08:03:50 AM UTC 24 Sep 11 08:03:52 AM UTC 24 91844010 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.1034418653 Sep 11 08:02:52 AM UTC 24 Sep 11 08:03:52 AM UTC 24 291328556 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.847145879 Sep 11 08:03:38 AM UTC 24 Sep 11 08:03:53 AM UTC 24 187944359 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.1673260189 Sep 11 08:03:27 AM UTC 24 Sep 11 08:03:53 AM UTC 24 4396252898 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3773508573 Sep 11 08:03:30 AM UTC 24 Sep 11 08:03:53 AM UTC 24 1164183115 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1276447721 Sep 11 08:03:36 AM UTC 24 Sep 11 08:03:55 AM UTC 24 1610097093 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2516628070 Sep 11 08:03:54 AM UTC 24 Sep 11 08:03:56 AM UTC 24 49214174 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1032976071 Sep 11 08:03:52 AM UTC 24 Sep 11 08:03:59 AM UTC 24 85591240 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.841374181 Sep 11 08:03:54 AM UTC 24 Sep 11 08:03:59 AM UTC 24 99558639 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.4018438119 Sep 11 08:03:55 AM UTC 24 Sep 11 08:03:59 AM UTC 24 920238182 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2120540725 Sep 11 08:03:20 AM UTC 24 Sep 11 08:04:01 AM UTC 24 191575986 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.2897230888 Sep 11 08:03:30 AM UTC 24 Sep 11 08:04:01 AM UTC 24 12325977759 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1815980368 Sep 11 08:03:14 AM UTC 24 Sep 11 08:04:01 AM UTC 24 421965904 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.910983478 Sep 11 08:04:00 AM UTC 24 Sep 11 08:04:03 AM UTC 24 273499334 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2812312665 Sep 11 08:03:57 AM UTC 24 Sep 11 08:04:04 AM UTC 24 918249818 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2623539011 Sep 11 08:03:13 AM UTC 24 Sep 11 08:04:06 AM UTC 24 1607199976 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3913995899 Sep 11 08:03:54 AM UTC 24 Sep 11 08:04:09 AM UTC 24 1027379684 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.131393901 Sep 11 08:04:01 AM UTC 24 Sep 11 08:04:10 AM UTC 24 1834835342 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2705894734 Sep 11 08:03:54 AM UTC 24 Sep 11 08:04:10 AM UTC 24 377161070 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.988000187 Sep 11 08:04:11 AM UTC 24 Sep 11 08:04:14 AM UTC 24 34333724 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1136533099 Sep 11 08:04:03 AM UTC 24 Sep 11 08:04:14 AM UTC 24 615678477 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.176792135 Sep 11 08:03:54 AM UTC 24 Sep 11 08:04:15 AM UTC 24 5003260362 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.634887920 Sep 11 08:04:11 AM UTC 24 Sep 11 08:04:15 AM UTC 24 97205437 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.789872784 Sep 11 08:04:02 AM UTC 24 Sep 11 08:04:15 AM UTC 24 1322317548 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1308875347 Sep 11 08:03:56 AM UTC 24 Sep 11 08:04:17 AM UTC 24 972621198 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2556592154 Sep 11 08:04:15 AM UTC 24 Sep 11 08:04:17 AM UTC 24 13322785 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.63449355 Sep 11 08:04:02 AM UTC 24 Sep 11 08:04:17 AM UTC 24 879205924 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2868827419 Sep 11 08:05:06 AM UTC 24 Sep 11 08:05:17 AM UTC 24 1503999919 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1905342057 Sep 11 08:04:02 AM UTC 24 Sep 11 08:04:18 AM UTC 24 895335189 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.592102554 Sep 11 08:02:33 AM UTC 24 Sep 11 08:04:20 AM UTC 24 2653934980 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2002742494 Sep 11 08:04:19 AM UTC 24 Sep 11 08:04:22 AM UTC 24 30388804 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1932176089 Sep 11 08:03:01 AM UTC 24 Sep 11 08:04:22 AM UTC 24 5015992075 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.2844025638 Sep 11 08:04:16 AM UTC 24 Sep 11 08:04:22 AM UTC 24 350630246 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.1656394046 Sep 11 08:03:47 AM UTC 24 Sep 11 08:04:23 AM UTC 24 110056804 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.2422688823 Sep 11 08:04:16 AM UTC 24 Sep 11 08:04:28 AM UTC 24 214195540 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.18498542 Sep 11 08:04:19 AM UTC 24 Sep 11 08:04:28 AM UTC 24 250504476 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2744169599 Sep 11 08:04:16 AM UTC 24 Sep 11 08:04:30 AM UTC 24 77797213 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3288477082 Sep 11 08:04:18 AM UTC 24 Sep 11 08:04:30 AM UTC 24 498902458 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.4292741387 Sep 11 08:04:24 AM UTC 24 Sep 11 08:04:32 AM UTC 24 356631673 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.3486254255 Sep 11 08:04:22 AM UTC 24 Sep 11 08:04:34 AM UTC 24 590299622 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2208963833 Sep 11 08:04:18 AM UTC 24 Sep 11 08:04:35 AM UTC 24 381341351 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1802879872 Sep 11 08:03:52 AM UTC 24 Sep 11 08:04:35 AM UTC 24 748007649 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.476086819 Sep 11 08:03:27 AM UTC 24 Sep 11 08:04:36 AM UTC 24 9090550090 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3898084015 Sep 11 08:04:35 AM UTC 24 Sep 11 08:04:37 AM UTC 24 30726512 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1028147822 Sep 11 08:04:36 AM UTC 24 Sep 11 08:04:39 AM UTC 24 33755494 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1005004425 Sep 11 08:03:56 AM UTC 24 Sep 11 08:05:17 AM UTC 24 6865768701 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3292316371 Sep 11 08:04:00 AM UTC 24 Sep 11 08:04:40 AM UTC 24 3288413067 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1719015051 Sep 11 08:04:28 AM UTC 24 Sep 11 08:04:42 AM UTC 24 320005166 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3532434161 Sep 11 08:04:38 AM UTC 24 Sep 11 08:04:43 AM UTC 24 75755533 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.3629293090 Sep 11 08:04:15 AM UTC 24 Sep 11 08:04:43 AM UTC 24 314874084 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1222503284 Sep 11 08:04:35 AM UTC 24 Sep 11 08:04:43 AM UTC 24 220901684 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.2172919691 Sep 11 08:04:39 AM UTC 24 Sep 11 08:04:44 AM UTC 24 225373613 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3373011172 Sep 11 08:04:25 AM UTC 24 Sep 11 08:04:44 AM UTC 24 910081741 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3896847699 Sep 11 08:04:43 AM UTC 24 Sep 11 08:04:45 AM UTC 24 18082056 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3710376451 Sep 11 08:04:10 AM UTC 24 Sep 11 08:04:49 AM UTC 24 370765759 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.3041143975 Sep 11 08:04:29 AM UTC 24 Sep 11 08:04:49 AM UTC 24 2011907129 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1662533882 Sep 11 08:04:47 AM UTC 24 Sep 11 08:04:51 AM UTC 24 183338649 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.3075145960 Sep 11 08:04:41 AM UTC 24 Sep 11 08:04:51 AM UTC 24 488892247 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3936993215 Sep 11 08:04:31 AM UTC 24 Sep 11 08:04:52 AM UTC 24 1425280632 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3119821356 Sep 11 08:04:24 AM UTC 24 Sep 11 08:04:52 AM UTC 24 5791707624 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.196191037 Sep 11 08:04:41 AM UTC 24 Sep 11 08:04:53 AM UTC 24 839494433 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1449066815 Sep 11 08:03:13 AM UTC 24 Sep 11 08:04:55 AM UTC 24 52364928652 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.2991782794 Sep 11 08:04:44 AM UTC 24 Sep 11 08:04:55 AM UTC 24 575551625 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3702378768 Sep 11 08:04:50 AM UTC 24 Sep 11 08:04:55 AM UTC 24 717265235 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2906452039 Sep 11 08:04:44 AM UTC 24 Sep 11 08:04:58 AM UTC 24 371401920 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2888117023 Sep 11 08:03:39 AM UTC 24 Sep 11 08:04:59 AM UTC 24 1377666439 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1946602957 Sep 11 08:04:57 AM UTC 24 Sep 11 08:04:59 AM UTC 24 47202934 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.980325593 Sep 11 08:04:57 AM UTC 24 Sep 11 08:04:59 AM UTC 24 11580881 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1109623361 Sep 11 08:04:21 AM UTC 24 Sep 11 08:05:01 AM UTC 24 791245669 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.1580773921 Sep 11 08:04:52 AM UTC 24 Sep 11 08:05:02 AM UTC 24 5571026175 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.4062156602 Sep 11 08:04:44 AM UTC 24 Sep 11 08:05:05 AM UTC 24 802165490 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3249483373 Sep 11 08:05:00 AM UTC 24 Sep 11 08:05:06 AM UTC 24 482288867 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2878413597 Sep 11 08:04:52 AM UTC 24 Sep 11 08:05:07 AM UTC 24 1193128131 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.11167560 Sep 11 08:05:05 AM UTC 24 Sep 11 08:05:08 AM UTC 24 14967289 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.1926821925 Sep 11 08:04:40 AM UTC 24 Sep 11 08:05:08 AM UTC 24 788915193 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3134213224 Sep 11 08:04:57 AM UTC 24 Sep 11 08:05:09 AM UTC 24 480972326 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.2147802944 Sep 11 08:04:24 AM UTC 24 Sep 11 08:05:12 AM UTC 24 2499584072 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.1523446042 Sep 11 08:05:00 AM UTC 24 Sep 11 08:05:13 AM UTC 24 57677439 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.3787166948 Sep 11 08:05:01 AM UTC 24 Sep 11 08:05:15 AM UTC 24 1397333668 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.3364718867 Sep 11 08:04:36 AM UTC 24 Sep 11 08:05:16 AM UTC 24 366815233 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3498269164 Sep 11 08:04:53 AM UTC 24 Sep 11 08:05:16 AM UTC 24 2609868659 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1939738427 Sep 11 08:05:20 AM UTC 24 Sep 11 08:05:24 AM UTC 24 52464125 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2913851002 Sep 11 08:04:51 AM UTC 24 Sep 11 08:05:18 AM UTC 24 4904058969 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3460758979 Sep 11 08:05:10 AM UTC 24 Sep 11 08:05:18 AM UTC 24 311445776 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.391912424 Sep 11 08:05:19 AM UTC 24 Sep 11 08:05:22 AM UTC 24 20167848 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.4282209932 Sep 11 08:04:19 AM UTC 24 Sep 11 08:05:25 AM UTC 24 1187399054 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.979429914 Sep 11 08:05:23 AM UTC 24 Sep 11 08:05:25 AM UTC 24 146888566 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.566403266 Sep 11 08:05:00 AM UTC 24 Sep 11 08:05:27 AM UTC 24 2715349428 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3961953700 Sep 11 08:05:03 AM UTC 24 Sep 11 08:05:27 AM UTC 24 470099468 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.685178139 Sep 11 08:04:06 AM UTC 24 Sep 11 08:05:28 AM UTC 24 1297558894 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2308311364 Sep 11 08:05:18 AM UTC 24 Sep 11 08:05:28 AM UTC 24 754145814 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1979154454 Sep 11 08:05:28 AM UTC 24 Sep 11 08:05:31 AM UTC 24 11969788 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.3507517939 Sep 11 08:05:09 AM UTC 24 Sep 11 08:05:31 AM UTC 24 2849617509 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.2818227896 Sep 11 08:05:14 AM UTC 24 Sep 11 08:05:32 AM UTC 24 1654754979 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1564540493 Sep 11 08:05:18 AM UTC 24 Sep 11 08:05:33 AM UTC 24 2922863662 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2126420901 Sep 11 08:05:26 AM UTC 24 Sep 11 08:05:33 AM UTC 24 87142000 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2842973213 Sep 11 08:06:25 AM UTC 24 Sep 11 08:06:35 AM UTC 24 250028604 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.4037253930 Sep 11 08:05:18 AM UTC 24 Sep 11 08:05:33 AM UTC 24 671932605 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1024526887 Sep 11 08:05:13 AM UTC 24 Sep 11 08:05:35 AM UTC 24 613904996 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.774473841 Sep 11 08:05:32 AM UTC 24 Sep 11 08:05:37 AM UTC 24 200069411 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3520143799 Sep 11 08:05:26 AM UTC 24 Sep 11 08:05:40 AM UTC 24 61798368 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1409936370 Sep 11 08:05:28 AM UTC 24 Sep 11 08:05:41 AM UTC 24 315664726 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.640946771 Sep 11 08:05:27 AM UTC 24 Sep 11 08:05:41 AM UTC 24 225488706 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3345076758 Sep 11 08:04:59 AM UTC 24 Sep 11 08:05:44 AM UTC 24 377743421 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.1939124528 Sep 11 08:05:28 AM UTC 24 Sep 11 08:05:48 AM UTC 24 303079621 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3043647472 Sep 11 08:05:40 AM UTC 24 Sep 11 08:05:48 AM UTC 24 1167993527 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1318527881 Sep 11 08:05:45 AM UTC 24 Sep 11 08:05:48 AM UTC 24 31483327 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3537839738 Sep 11 08:05:36 AM UTC 24 Sep 11 08:05:48 AM UTC 24 530843700 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1455162987 Sep 11 08:05:34 AM UTC 24 Sep 11 08:05:49 AM UTC 24 1505432621 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1874348015 Sep 11 08:04:53 AM UTC 24 Sep 11 08:05:49 AM UTC 24 14076536425 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.982102736 Sep 11 08:04:45 AM UTC 24 Sep 11 08:05:49 AM UTC 24 3363253133 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.4118288418 Sep 11 08:05:41 AM UTC 24 Sep 11 08:05:51 AM UTC 24 653168001 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3647777932 Sep 11 08:05:49 AM UTC 24 Sep 11 08:05:51 AM UTC 24 25142231 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.2350807691 Sep 11 08:05:10 AM UTC 24 Sep 11 08:05:51 AM UTC 24 8303574111 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3026972577 Sep 11 08:05:33 AM UTC 24 Sep 11 08:05:51 AM UTC 24 395829478 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3757839160 Sep 11 08:06:22 AM UTC 24 Sep 11 08:06:28 AM UTC 24 40774201 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1236231250 Sep 11 08:06:26 AM UTC 24 Sep 11 08:06:31 AM UTC 24 172694060 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.780478164 Sep 11 08:06:27 AM UTC 24 Sep 11 08:06:34 AM UTC 24 250526960 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2948954438 Sep 11 08:05:34 AM UTC 24 Sep 11 08:05:52 AM UTC 24 2365101952 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.4095682455 Sep 11 08:05:47 AM UTC 24 Sep 11 08:05:52 AM UTC 24 141455508 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.2042459859 Sep 11 08:05:50 AM UTC 24 Sep 11 08:05:54 AM UTC 24 46208010 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.875831677 Sep 11 08:04:44 AM UTC 24 Sep 11 08:05:54 AM UTC 24 24423692792 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.1082063009 Sep 11 08:05:51 AM UTC 24 Sep 11 08:05:54 AM UTC 24 11029407 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.105332381 Sep 11 08:05:40 AM UTC 24 Sep 11 08:05:55 AM UTC 24 265756393 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3991418434 Sep 11 08:05:16 AM UTC 24 Sep 11 08:05:56 AM UTC 24 1948747726 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1743819437 Sep 11 08:05:25 AM UTC 24 Sep 11 08:05:56 AM UTC 24 1036089678 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.849507482 Sep 11 08:05:49 AM UTC 24 Sep 11 08:06:05 AM UTC 24 138478104 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3538711331 Sep 11 08:05:52 AM UTC 24 Sep 11 08:06:05 AM UTC 24 1401619382 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.180630925 Sep 11 08:05:56 AM UTC 24 Sep 11 08:06:05 AM UTC 24 235398632 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3112096776 Sep 11 08:05:55 AM UTC 24 Sep 11 08:06:06 AM UTC 24 2312323694 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.736332447 Sep 11 08:05:55 AM UTC 24 Sep 11 08:06:06 AM UTC 24 479034665 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.4119614323 Sep 11 08:05:53 AM UTC 24 Sep 11 08:06:07 AM UTC 24 3575214224 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.466797788 Sep 11 08:06:24 AM UTC 24 Sep 11 08:06:43 AM UTC 24 1544676101 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.881024443 Sep 11 08:05:52 AM UTC 24 Sep 11 08:06:08 AM UTC 24 338312737 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.4058398405 Sep 11 08:05:50 AM UTC 24 Sep 11 08:06:08 AM UTC 24 1198513623 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.4076206919 Sep 11 08:02:47 AM UTC 24 Sep 11 08:06:09 AM UTC 24 44375322570 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2318260768 Sep 11 08:06:06 AM UTC 24 Sep 11 08:06:09 AM UTC 24 58301711 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2730737026 Sep 11 08:06:06 AM UTC 24 Sep 11 08:06:09 AM UTC 24 25754608 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.639389934 Sep 11 08:06:07 AM UTC 24 Sep 11 08:06:10 AM UTC 24 25721250 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1149626149 Sep 11 08:05:50 AM UTC 24 Sep 11 08:06:10 AM UTC 24 1711451612 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3532448736 Sep 11 08:05:50 AM UTC 24 Sep 11 08:06:10 AM UTC 24 321086277 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2400690219 Sep 11 08:05:38 AM UTC 24 Sep 11 08:06:12 AM UTC 24 8102457423 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3891607833 Sep 11 08:06:10 AM UTC 24 Sep 11 08:06:14 AM UTC 24 50449126 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1201533645 Sep 11 08:05:56 AM UTC 24 Sep 11 08:06:14 AM UTC 24 2742057793 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.439480016 Sep 11 08:05:58 AM UTC 24 Sep 11 08:06:17 AM UTC 24 429604428 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.2729609851 Sep 11 08:06:12 AM UTC 24 Sep 11 08:06:17 AM UTC 24 66792962 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.2747048216 Sep 11 08:06:10 AM UTC 24 Sep 11 08:06:18 AM UTC 24 610126589 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2720649812 Sep 11 08:05:49 AM UTC 24 Sep 11 08:06:18 AM UTC 24 701023707 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.149224418 Sep 11 08:06:19 AM UTC 24 Sep 11 08:06:22 AM UTC 24 65749295 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3356756377 Sep 11 08:04:05 AM UTC 24 Sep 11 08:06:22 AM UTC 24 4385304308 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1711990310 Sep 11 08:06:08 AM UTC 24 Sep 11 08:06:22 AM UTC 24 820955022 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2607676606 Sep 11 08:05:55 AM UTC 24 Sep 11 08:06:23 AM UTC 24 3696896679 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1642191462 Sep 11 08:06:10 AM UTC 24 Sep 11 08:06:23 AM UTC 24 4482619773 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1399910756 Sep 11 08:06:10 AM UTC 24 Sep 11 08:06:23 AM UTC 24 1343270959 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.1614172096 Sep 11 08:06:11 AM UTC 24 Sep 11 08:06:24 AM UTC 24 450366492 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4003850976 Sep 11 08:06:22 AM UTC 24 Sep 11 08:06:25 AM UTC 24 13192681 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.2306782395 Sep 11 08:06:11 AM UTC 24 Sep 11 08:06:26 AM UTC 24 1002682750 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.2306821939 Sep 11 08:05:09 AM UTC 24 Sep 11 08:06:26 AM UTC 24 6371456675 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3359686067 Sep 11 08:06:18 AM UTC 24 Sep 11 08:06:27 AM UTC 24 1072592633 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.671136139 Sep 11 08:06:24 AM UTC 24 Sep 11 08:06:28 AM UTC 24 97986838 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1461301669 Sep 11 08:06:16 AM UTC 24 Sep 11 08:06:31 AM UTC 24 548612679 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.476979579 Sep 11 08:05:53 AM UTC 24 Sep 11 08:06:36 AM UTC 24 8298536126 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2225860842 Sep 11 08:06:24 AM UTC 24 Sep 11 08:06:37 AM UTC 24 224360602 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3525013498 Sep 11 08:06:14 AM UTC 24 Sep 11 08:06:40 AM UTC 24 1814425219 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1771868530 Sep 11 08:06:32 AM UTC 24 Sep 11 08:06:41 AM UTC 24 228170529 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.480767099 Sep 11 08:06:38 AM UTC 24 Sep 11 08:06:41 AM UTC 24 26414771 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.4104313623 Sep 11 08:06:29 AM UTC 24 Sep 11 08:06:42 AM UTC 24 803850793 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2258775897 Sep 11 08:06:27 AM UTC 24 Sep 11 08:06:44 AM UTC 24 1095850414 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1842650001 Sep 11 08:06:42 AM UTC 24 Sep 11 08:06:44 AM UTC 24 59894968 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3766532193 Sep 11 08:06:11 AM UTC 24 Sep 11 08:06:45 AM UTC 24 724922530 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1467597635 Sep 11 08:06:42 AM UTC 24 Sep 11 08:06:46 AM UTC 24 54404752 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.89553280 Sep 11 08:06:44 AM UTC 24 Sep 11 08:06:47 AM UTC 24 13839543 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.2199441025 Sep 11 08:07:56 AM UTC 24 Sep 11 08:08:00 AM UTC 24 64030480 ps