Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58024462

1

T1

869

T2

2842

T3

6862

auto[1]

1107327

1

T3

396

T4

1782

T12

891

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58045939

1

T1

869

T2

2842

T3

7159

auto[1]

1085850

1

T3

99

T4

1980

T12

693

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5243777	1			T1	65		T2	913		T3	1437
auto[IdleSt]	16297527	1			T1	62		T2	218		T3	1511
auto[ClkMuxSt]	27736	1			T1	1		T2	8		T3	10
auto[CntIncrSt]	27560	1			T1	1		T2	8		T3	10
auto[CntProgSt]	1409795	1			T1	18		T2	307		T3	132
auto[TransCheckSt]	21998	1			T1	1		T2	8		T3	10
auto[TokenHashSt]	14748598	1			T1	16		T2	312		T3	1004
auto[FlashRmaSt]	26213	1			T2	8		T3	23		T13	26
auto[TokenCheck0St]	9510	1			T2	8		T3	10		T13	13
auto[TokenCheck1St]	6711	1			T2	8		T3	10		T13	7
auto[TransProgSt]	277714	1			T2	389		T3	125		T13	53
auto[PostTransSt]	9174929	1			T1	705		T2	624		T3	1725
auto[ScrapSt]	178747	1			T2	31		T5	439		T16	4
auto[EscalateSt]	4530645	1			T3	876		T4	4768		T12	2153
auto[InvalidSt]	7148992	1			T3	374		T4	2809		T11	3721

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1337	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7148992	1			T3	374		T4	2809		T11	3721
EscalateSt	4530645	1			T3	876		T4	4768		T12	2153
ScrapSt	178747	1			T2	31		T5	439		T16	4
PostTransSt	9174929	1			T1	705		T2	624		T3	1725
TransProgSt	277714	1			T2	389		T3	125		T13	53
TokenCheck1St	6711	1			T2	8		T3	10		T13	7
TokenCheck0St	9510	1			T2	8		T3	10		T13	13
FlashRmaSt	26213	1			T2	8		T3	23		T13	26
TokenHashSt	14748598	1			T1	16		T2	312		T3	1004
TransCheckSt	21998	1			T1	1		T2	8		T3	10
CntProgSt	1409795	1			T1	18		T2	307		T3	132
CntIncrSt	27560	1			T1	1		T2	8		T3	10
ClkMuxSt	27736	1			T1	1		T2	8		T3	10
IdleSt	16297527	1			T1	62		T2	218		T3	1511
ResetSt	5243777	1			T1	65		T2	913		T3	1437
arcs[ResetSt=>IdleSt]	41132	1			T1	1		T2	10		T3	16
arcs[IdleSt=>ScrapSt]	241	1			T2	2		T5	1		T16	1
arcs[IdleSt=>ClkMuxSt]	27595	1			T1	1		T2	8		T3	10
arcs[ClkMuxSt=>CntIncrSt]	27560	1			T1	1		T2	8		T3	10
arcs[CntIncrSt=>PostTransSt]	1177	1			T13	4		T23	2		T24	6
arcs[CntIncrSt=>CntProgSt]	26327	1			T1	1		T2	8		T3	10
arcs[CntProgSt=>PostTransSt]	3177	1			T12	16		T13	6		T6	4
arcs[CntProgSt=>TransCheckSt]	21998	1			T1	1		T2	8		T3	10
arcs[TransCheckSt=>PostTransSt]	3148	1			T13	6		T20	32		T23	6
arcs[TransCheckSt=>TokenHashSt]	18757	1			T1	1		T2	8		T3	10
arcs[TokenHashSt=>PostTransSt]	8472	1			T1	1		T13	23		T20	11
arcs[TokenHashSt=>FlashRmaSt]	9560	1			T2	8		T3	10		T13	13
arcs[FlashRmaSt=>TokenCheck0St]	9510	1			T2	8		T3	10		T13	13
arcs[TokenCheck0St=>PostTransSt]	2743	1			T13	6		T20	28		T22	21
arcs[TokenCheck0St=>TokenCheck1St]	6711	1			T2	8		T3	10		T13	7
arcs[TokenCheck1St=>PostTransSt]	594	1			T13	1		T20	17		T22	1
arcs[TransProgSt=>PostTransSt]	5315	1			T2	8		T3	10		T13	6
arcs[IdleSt=>EscalateSt]	144	1			T16	6		T56	3		T58	6
arcs[ClkMuxSt=>EscalateSt]	35	1			T16	2		T56	2		T57	1
arcs[CntIncrSt=>EscalateSt]	56	1			T16	1		T56	1		T58	1
arcs[CntProgSt=>EscalateSt]	1152	1			T16	25		T56	46		T58	33
arcs[TransCheckSt=>EscalateSt]	93	1			T58	2		T57	7		T59	2
arcs[TokenHashSt=>EscalateSt]	725	1			T16	7		T56	13		T58	8
arcs[FlashRmaSt=>EscalateSt]	50	1			T16	1		T56	1		T59	1
arcs[TokenCheck0St=>EscalateSt]	56	1			T56	3		T59	1		T62	1
arcs[TokenCheck1St=>EscalateSt]	19	1			T56	2		T63	1		T64	1
arcs[TransProgSt=>EscalateSt]	783	1			T16	23		T56	16		T58	25
arcs[PostTransSt=>EscalateSt]	3500	1			T12	16		T13	6		T16	2
arcs[InvalidSt=>EscalateSt]	9715	1			T3	5		T4	38		T11	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5243637	1			T1	65		T2	913		T3	1437
auto[0]	auto[IdleSt]	16297424	1			T1	62		T2	218		T3	1511
auto[0]	auto[ClkMuxSt]	27711	1			T1	1		T2	8		T3	10
auto[0]	auto[CntIncrSt]	27524	1			T1	1		T2	8		T3	10
auto[0]	auto[CntProgSt]	1409010	1			T1	18		T2	307		T3	132
auto[0]	auto[TransCheckSt]	21932	1			T1	1		T2	8		T3	10
auto[0]	auto[TokenHashSt]	14748102	1			T1	16		T2	312		T3	1004
auto[0]	auto[FlashRmaSt]	26179	1			T2	8		T3	23		T13	26
auto[0]	auto[TokenCheck0St]	9472	1			T2	8		T3	10		T13	13
auto[0]	auto[TokenCheck1St]	6700	1			T2	8		T3	10		T13	7
auto[0]	auto[TransProgSt]	277179	1			T2	389		T3	125		T13	53
auto[0]	auto[PostTransSt]	9173088	1			T1	705		T2	624		T3	1725
auto[0]	auto[ScrapSt]	178703	1			T2	31		T5	439		T16	3
auto[0]	auto[EscalateSt]	3432318	1			T3	484		T4	3004		T12	1271
auto[0]	auto[InvalidSt]	7144146	1			T3	370		T4	2791		T11	3720
auto[1]	auto[ResetSt]	140	1			T16	3		T56	6		T58	3
auto[1]	auto[IdleSt]	103	1			T16	6		T56	1		T58	3
auto[1]	auto[ClkMuxSt]	25	1			T16	2		T56	1		T57	1
auto[1]	auto[CntIncrSt]	36	1			T16	1		T56	1		T62	2
auto[1]	auto[CntProgSt]	785	1			T16	16		T56	33		T58	26
auto[1]	auto[TransCheckSt]	66	1			T58	1		T57	6		T59	2
auto[1]	auto[TokenHashSt]	496	1			T16	3		T56	7		T58	6
auto[1]	auto[FlashRmaSt]	34	1			T16	1		T56	1		T59	1
auto[1]	auto[TokenCheck0St]	38	1			T56	2		T59	1		T62	1
auto[1]	auto[TokenCheck1St]	11	1			T56	2		T214	1		T215	1
auto[1]	auto[TransProgSt]	535	1			T16	17		T56	10		T58	15
auto[1]	auto[PostTransSt]	1841	1			T12	9		T13	2		T16	1
auto[1]	auto[ScrapSt]	44	1			T16	1		T57	1		T59	1
auto[1]	auto[EscalateSt]	1098327	1			T3	392		T4	1764		T12	882
auto[1]	auto[InvalidSt]	4846	1			T3	4		T4	18		T11	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5243623	1			T1	65		T2	913		T3	1437
auto[0]	auto[IdleSt]	16297432	1			T1	62		T2	218		T3	1511
auto[0]	auto[ClkMuxSt]	27712	1			T1	1		T2	8		T3	10
auto[0]	auto[CntIncrSt]	27521	1			T1	1		T2	8		T3	10
auto[0]	auto[CntProgSt]	1409040	1			T1	18		T2	307		T3	132
auto[0]	auto[TransCheckSt]	21942	1			T1	1		T2	8		T3	10
auto[0]	auto[TokenHashSt]	14748130	1			T1	16		T2	312		T3	1004
auto[0]	auto[FlashRmaSt]	26177	1			T2	8		T3	23		T13	26
auto[0]	auto[TokenCheck0St]	9474	1			T2	8		T3	10		T13	13
auto[0]	auto[TokenCheck1St]	6697	1			T2	8		T3	10		T13	7
auto[0]	auto[TransProgSt]	277197	1			T2	389		T3	125		T13	53
auto[0]	auto[PostTransSt]	9173169	1			T1	705		T2	624		T3	1725
auto[0]	auto[ScrapSt]	178716	1			T2	31		T5	439		T16	4
auto[0]	auto[EscalateSt]	3453649	1			T3	778		T4	2808		T12	1467
auto[0]	auto[InvalidSt]	7144123	1			T3	373		T4	2789		T11	3720
auto[1]	auto[ResetSt]	154	1			T16	3		T56	3		T58	2
auto[1]	auto[IdleSt]	95	1			T16	2		T56	2		T58	4
auto[1]	auto[ClkMuxSt]	24	1			T16	1		T56	1		T57	1
auto[1]	auto[CntIncrSt]	39	1			T16	1		T58	1		T57	1
auto[1]	auto[CntProgSt]	755	1			T16	18		T56	28		T58	20
auto[1]	auto[TransCheckSt]	56	1			T58	1		T57	4		T59	1
auto[1]	auto[TokenHashSt]	468	1			T16	5		T56	8		T58	5
auto[1]	auto[FlashRmaSt]	36	1			T16	1		T62	1		T216	1
auto[1]	auto[TokenCheck0St]	36	1			T56	2		T62	1		T217	1
auto[1]	auto[TokenCheck1St]	14	1			T56	1		T63	1		T64	1
auto[1]	auto[TransProgSt]	517	1			T16	14		T56	11		T58	16
auto[1]	auto[PostTransSt]	1760	1			T12	7		T13	4		T16	2
auto[1]	auto[ScrapSt]	31	1			T59	2		T105	1		T218	1
auto[1]	auto[EscalateSt]	1076996	1			T3	98		T4	1960		T12	686
auto[1]	auto[InvalidSt]	4869	1			T3	1		T4	20		T11	1