Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 97.90 96.12 93.40 100.00 98.49 98.76 96.29


Total tests in report: 999
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.51 67.51 81.80 81.80 53.14 53.14 58.70 58.70 52.38 52.38 81.51 81.51 92.04 92.04 53.00 53.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3890846462
77.84 10.33 88.04 6.24 79.39 26.25 79.35 20.65 57.14 4.76 86.02 4.52 93.78 1.74 61.13 8.13 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3131968474
83.44 5.61 88.50 0.46 80.41 1.02 81.84 2.49 80.95 23.81 90.11 4.09 94.28 0.50 68.02 6.89 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1884659694
86.21 2.77 89.78 1.28 84.01 3.60 84.15 2.31 83.33 2.38 91.83 1.72 94.78 0.50 75.62 7.60 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3721977672
88.51 2.30 96.27 6.49 84.29 0.28 85.69 1.54 83.33 0.00 93.76 1.94 94.78 0.00 81.45 5.83 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2104416154
90.12 1.61 96.37 0.10 85.21 0.92 89.04 3.35 88.10 4.76 94.41 0.65 95.02 0.25 82.69 1.24 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1703469550
91.37 1.25 96.47 0.10 87.43 2.22 89.08 0.04 88.10 0.00 95.05 0.65 96.02 1.00 87.46 4.77 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.79965889
92.39 1.02 97.09 0.61 89.56 2.13 89.28 0.20 88.10 0.00 96.56 1.51 96.77 0.75 89.40 1.94 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2279476673
93.30 0.91 97.14 0.05 89.74 0.18 89.35 0.07 92.86 4.76 96.77 0.22 96.77 0.00 90.46 1.06 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3062839100
93.78 0.48 97.19 0.05 89.93 0.18 89.35 0.00 95.24 2.38 96.99 0.22 96.77 0.00 90.99 0.53 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3084043925
94.24 0.46 97.34 0.15 91.50 1.57 89.35 0.00 95.24 0.00 97.42 0.43 96.77 0.00 92.05 1.06 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3182241588
94.63 0.39 97.34 0.00 91.87 0.37 89.35 0.00 97.62 2.38 97.42 0.00 96.77 0.00 92.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2737896630
94.99 0.36 97.34 0.00 91.87 0.00 91.34 1.98 97.62 0.00 97.42 0.00 96.77 0.00 92.58 0.53 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2813274255
95.33 0.34 97.34 0.00 91.87 0.00 91.34 0.00 100.00 2.38 97.42 0.00 96.77 0.00 92.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1241124252
95.66 0.33 97.39 0.05 91.87 0.00 91.77 0.44 100.00 0.00 97.63 0.22 96.77 0.00 94.17 1.59 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1383878847
95.91 0.25 97.39 0.00 91.87 0.00 91.77 0.00 100.00 0.00 97.63 0.00 98.51 1.74 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2594218665
96.12 0.21 97.75 0.36 92.79 0.92 91.95 0.18 100.00 0.00 97.63 0.00 98.51 0.00 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.3838303237
96.25 0.13 97.75 0.00 92.79 0.00 92.66 0.71 100.00 0.00 97.85 0.22 98.51 0.00 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3003314389
96.36 0.12 97.75 0.00 93.25 0.46 92.66 0.00 100.00 0.00 97.85 0.00 98.51 0.00 94.52 0.35 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.41134765
96.46 0.10 97.90 0.15 93.35 0.09 92.66 0.00 100.00 0.00 98.28 0.43 98.51 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3326293923
96.55 0.09 97.90 0.00 93.81 0.46 92.66 0.00 100.00 0.00 98.28 0.00 98.51 0.00 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2595676420
96.64 0.09 97.90 0.00 93.81 0.00 92.73 0.07 100.00 0.00 98.28 0.00 98.51 0.00 95.23 0.53 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.80466961
96.72 0.08 97.90 0.00 94.36 0.55 92.73 0.00 100.00 0.00 98.28 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1247404333
96.79 0.08 97.90 0.00 94.36 0.00 93.26 0.53 100.00 0.00 98.28 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.931551748
96.84 0.05 97.90 0.00 94.55 0.18 93.39 0.13 100.00 0.00 98.28 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1189911582
96.88 0.04 97.90 0.00 94.64 0.09 93.39 0.00 100.00 0.00 98.49 0.22 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.3221730068
96.92 0.04 97.90 0.00 94.92 0.28 93.39 0.00 100.00 0.00 98.49 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2845503328
96.96 0.04 97.90 0.00 95.19 0.28 93.39 0.00 100.00 0.00 98.49 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2501525688
97.00 0.04 97.90 0.00 95.19 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3225102737
97.02 0.03 97.90 0.00 95.38 0.18 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3325234880
97.05 0.03 97.90 0.00 95.56 0.18 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2909388323
97.07 0.03 97.90 0.00 95.56 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1500508980
97.10 0.03 97.90 0.00 95.56 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2703524857
97.12 0.03 97.90 0.00 95.56 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.161275862
97.15 0.03 97.90 0.00 95.56 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2283491841
97.17 0.03 97.90 0.00 95.56 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.1502418883
97.20 0.03 97.90 0.00 95.56 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.3658398438
97.21 0.01 97.90 0.00 95.66 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3308556281
97.23 0.01 97.90 0.00 95.75 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3391130300
97.24 0.01 97.90 0.00 95.84 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2363115418
97.25 0.01 97.90 0.00 95.93 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1807205523
97.27 0.01 97.90 0.00 96.03 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.388948678
97.28 0.01 97.90 0.00 96.12 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2356220904
97.28 0.01 97.90 0.00 96.12 0.00 93.40 0.01 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2289867916

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.300044018
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2291281043
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1472202350
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.699343550
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2474998059
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2236712618
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3995091522
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.738470899
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1815541119
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1645861162
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3125819539
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2470116770
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3069403915
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1293052300
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.644317634
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2995020714
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1438101773
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1152878525
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2487023533
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.961955982
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3002466034
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4153200902
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3486101962
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1210196932
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2974562172
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3430321508
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3556549683
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4031992920
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1144942422
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1710693531
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2781841693
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2216758464
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2966970613
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3094782924
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.89983895
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1519440800
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3213262396
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.633900081
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1483188361
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.742080989
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1368477375
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1765780057
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1329811358
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.250112426
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2699190676
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2366025466
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1566014880
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/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2831358544
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4276131297
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.3966155659
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3175419185
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/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.4252702357
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/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.746668149
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3638914548
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1753535670
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.4221542519
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2466563530
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/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.3192515479
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/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3265185198
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/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1278653420



Total test records in report: 999
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2703524857 Sep 18 12:33:41 PM UTC 24 Sep 18 12:33:44 PM UTC 24 17759530 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1601699665 Sep 18 12:33:40 PM UTC 24 Sep 18 12:33:45 PM UTC 24 118519782 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.2699006272 Sep 18 12:33:45 PM UTC 24 Sep 18 12:33:57 PM UTC 24 72601911 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.680634246 Sep 18 12:33:44 PM UTC 24 Sep 18 12:34:04 PM UTC 24 287328900 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.2553624248 Sep 18 12:33:59 PM UTC 24 Sep 18 12:34:05 PM UTC 24 307921496 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3890846462 Sep 18 12:34:05 PM UTC 24 Sep 18 12:34:20 PM UTC 24 386917785 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1500508980 Sep 18 12:34:20 PM UTC 24 Sep 18 12:34:23 PM UTC 24 21891109 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1176824763 Sep 18 12:34:10 PM UTC 24 Sep 18 12:34:26 PM UTC 24 821833123 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.2501554842 Sep 18 12:34:23 PM UTC 24 Sep 18 12:34:27 PM UTC 24 185493428 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1884659694 Sep 18 12:34:06 PM UTC 24 Sep 18 12:34:31 PM UTC 24 654673361 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1189911582 Sep 18 12:34:29 PM UTC 24 Sep 18 12:34:37 PM UTC 24 518824801 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2279476673 Sep 18 12:34:32 PM UTC 24 Sep 18 12:34:43 PM UTC 24 5758730965 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1852883383 Sep 18 12:34:27 PM UTC 24 Sep 18 12:34:46 PM UTC 24 2504835757 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1545036513 Sep 18 12:34:38 PM UTC 24 Sep 18 12:35:09 PM UTC 24 1268894456 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1383878847 Sep 18 12:34:48 PM UTC 24 Sep 18 12:35:12 PM UTC 24 2077050683 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2104416154 Sep 18 12:34:44 PM UTC 24 Sep 18 12:35:13 PM UTC 24 396402022 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3895066187 Sep 18 12:35:10 PM UTC 24 Sep 18 12:35:27 PM UTC 24 1441244152 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2289867916 Sep 18 12:34:31 PM UTC 24 Sep 18 12:35:28 PM UTC 24 4698312110 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.3838303237 Sep 18 12:35:28 PM UTC 24 Sep 18 12:35:30 PM UTC 24 89484055 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2221680758 Sep 18 12:35:32 PM UTC 24 Sep 18 12:35:34 PM UTC 24 35041612 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1136621456 Sep 18 12:35:30 PM UTC 24 Sep 18 12:35:35 PM UTC 24 231101516 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.1151997176 Sep 18 12:34:37 PM UTC 24 Sep 18 12:35:38 PM UTC 24 2092832059 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.767098536 Sep 18 12:35:39 PM UTC 24 Sep 18 12:35:45 PM UTC 24 470779350 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.80466961 Sep 18 12:35:36 PM UTC 24 Sep 18 12:35:49 PM UTC 24 101199614 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1703469550 Sep 18 12:35:14 PM UTC 24 Sep 18 12:36:06 PM UTC 24 977966213 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.3608477823 Sep 18 12:35:46 PM UTC 24 Sep 18 12:36:08 PM UTC 24 406141687 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.345051506 Sep 18 12:35:35 PM UTC 24 Sep 18 12:36:08 PM UTC 24 781927940 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.1366125394 Sep 18 12:36:07 PM UTC 24 Sep 18 12:36:09 PM UTC 24 13883599 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1238319164 Sep 18 12:35:56 PM UTC 24 Sep 18 12:36:11 PM UTC 24 1066229225 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3062839100 Sep 18 12:35:49 PM UTC 24 Sep 18 12:36:13 PM UTC 24 1797177179 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3131968474 Sep 18 12:34:23 PM UTC 24 Sep 18 12:36:14 PM UTC 24 7169688962 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.2531861527 Sep 18 12:36:12 PM UTC 24 Sep 18 12:36:21 PM UTC 24 992745825 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.321974040 Sep 18 12:36:09 PM UTC 24 Sep 18 12:36:23 PM UTC 24 336192468 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3265132332 Sep 18 12:36:15 PM UTC 24 Sep 18 12:36:35 PM UTC 24 465692807 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3751912209 Sep 18 12:36:10 PM UTC 24 Sep 18 12:36:36 PM UTC 24 798282536 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.3560610655 Sep 18 12:36:21 PM UTC 24 Sep 18 12:36:39 PM UTC 24 1466096392 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2343385564 Sep 18 12:36:36 PM UTC 24 Sep 18 12:36:54 PM UTC 24 254689861 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3052651107 Sep 18 12:36:40 PM UTC 24 Sep 18 12:36:55 PM UTC 24 334632340 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2963477827 Sep 18 12:36:25 PM UTC 24 Sep 18 12:36:56 PM UTC 24 665565536 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.493528430 Sep 18 12:36:37 PM UTC 24 Sep 18 12:36:57 PM UTC 24 3290175061 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.2712712214 Sep 18 12:36:56 PM UTC 24 Sep 18 12:36:58 PM UTC 24 26256764 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3515890370 Sep 18 12:36:58 PM UTC 24 Sep 18 12:37:01 PM UTC 24 19924705 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.72467674 Sep 18 12:36:57 PM UTC 24 Sep 18 12:37:02 PM UTC 24 113324310 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2523668659 Sep 18 12:37:04 PM UTC 24 Sep 18 12:37:07 PM UTC 24 72307722 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.4102008882 Sep 18 12:37:01 PM UTC 24 Sep 18 12:37:13 PM UTC 24 328364091 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.4079397958 Sep 18 12:36:14 PM UTC 24 Sep 18 12:37:15 PM UTC 24 1576227447 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1279311460 Sep 18 12:37:16 PM UTC 24 Sep 18 12:37:18 PM UTC 24 41642674 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.4046483894 Sep 18 12:36:09 PM UTC 24 Sep 18 12:37:21 PM UTC 24 2287884885 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3721977672 Sep 18 12:35:13 PM UTC 24 Sep 18 12:37:21 PM UTC 24 7114093356 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.4150693116 Sep 18 12:37:04 PM UTC 24 Sep 18 12:37:22 PM UTC 24 563404254 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3865050039 Sep 18 12:37:19 PM UTC 24 Sep 18 12:37:23 PM UTC 24 634713066 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.952345178 Sep 18 12:37:08 PM UTC 24 Sep 18 12:37:26 PM UTC 24 316414157 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.1468831161 Sep 18 12:37:23 PM UTC 24 Sep 18 12:37:27 PM UTC 24 471274072 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2669515183 Sep 18 12:37:27 PM UTC 24 Sep 18 12:37:32 PM UTC 24 72126153 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.2513361218 Sep 18 12:36:46 PM UTC 24 Sep 18 12:37:33 PM UTC 24 543826761 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2098236495 Sep 18 12:37:14 PM UTC 24 Sep 18 12:37:33 PM UTC 24 1425655782 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.565832660 Sep 18 12:37:23 PM UTC 24 Sep 18 12:37:39 PM UTC 24 1402777612 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.375423792 Sep 18 12:36:55 PM UTC 24 Sep 18 12:37:41 PM UTC 24 436748032 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3139411690 Sep 18 12:36:59 PM UTC 24 Sep 18 12:37:42 PM UTC 24 367057038 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1026109859 Sep 18 12:37:27 PM UTC 24 Sep 18 12:37:44 PM UTC 24 3682842115 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1313241770 Sep 18 12:37:35 PM UTC 24 Sep 18 12:37:47 PM UTC 24 227962088 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.329871634 Sep 18 12:37:45 PM UTC 24 Sep 18 12:37:48 PM UTC 24 25083573 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2498414880 Sep 18 12:37:48 PM UTC 24 Sep 18 12:37:51 PM UTC 24 19870200 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.543691561 Sep 18 12:37:48 PM UTC 24 Sep 18 12:37:52 PM UTC 24 121790470 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3108551486 Sep 18 12:37:35 PM UTC 24 Sep 18 12:37:56 PM UTC 24 1636943074 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3037137055 Sep 18 12:37:32 PM UTC 24 Sep 18 12:37:56 PM UTC 24 2889814162 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.3776708306 Sep 18 12:37:53 PM UTC 24 Sep 18 12:37:58 PM UTC 24 45566875 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.1992814300 Sep 18 12:37:58 PM UTC 24 Sep 18 12:38:00 PM UTC 24 11185406 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2433956166 Sep 18 12:37:29 PM UTC 24 Sep 18 12:38:01 PM UTC 24 1418898140 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.1981368260 Sep 18 12:37:24 PM UTC 24 Sep 18 12:38:04 PM UTC 24 5580971988 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3132296908 Sep 18 12:37:53 PM UTC 24 Sep 18 12:38:04 PM UTC 24 645239009 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3670394657 Sep 18 12:37:52 PM UTC 24 Sep 18 12:38:04 PM UTC 24 73047173 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2839573665 Sep 18 12:37:59 PM UTC 24 Sep 18 12:38:05 PM UTC 24 363027026 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.841811582 Sep 18 12:37:57 PM UTC 24 Sep 18 12:38:06 PM UTC 24 179451967 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1797425333 Sep 18 12:37:42 PM UTC 24 Sep 18 12:38:06 PM UTC 24 1868031557 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3084043925 Sep 18 12:37:56 PM UTC 24 Sep 18 12:38:09 PM UTC 24 965953820 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1438215125 Sep 18 12:38:05 PM UTC 24 Sep 18 12:38:10 PM UTC 24 89811931 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.3963795808 Sep 18 12:38:06 PM UTC 24 Sep 18 12:38:10 PM UTC 24 151401757 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.872773971 Sep 18 12:37:43 PM UTC 24 Sep 18 12:38:28 PM UTC 24 1282831584 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.586969509 Sep 18 12:38:02 PM UTC 24 Sep 18 12:38:14 PM UTC 24 1810514781 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2173673121 Sep 18 12:38:05 PM UTC 24 Sep 18 12:38:19 PM UTC 24 1159649065 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.237250499 Sep 18 12:37:52 PM UTC 24 Sep 18 12:38:21 PM UTC 24 1114755962 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3716560388 Sep 18 12:38:09 PM UTC 24 Sep 18 12:38:22 PM UTC 24 964464921 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1576026628 Sep 18 12:38:22 PM UTC 24 Sep 18 12:38:24 PM UTC 24 75711229 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2099923756 Sep 18 12:38:11 PM UTC 24 Sep 18 12:38:25 PM UTC 24 922465180 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3974063839 Sep 18 12:38:23 PM UTC 24 Sep 18 12:38:26 PM UTC 24 19984194 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3734287528 Sep 18 12:38:07 PM UTC 24 Sep 18 12:38:27 PM UTC 24 5188549892 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.1511593761 Sep 18 12:38:22 PM UTC 24 Sep 18 12:38:30 PM UTC 24 137762096 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.4237808652 Sep 18 12:38:07 PM UTC 24 Sep 18 12:38:31 PM UTC 24 2817452379 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1389201805 Sep 18 12:38:27 PM UTC 24 Sep 18 12:38:32 PM UTC 24 209001119 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2283491841 Sep 18 12:38:31 PM UTC 24 Sep 18 12:38:33 PM UTC 24 68685616 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.2016186932 Sep 18 12:38:26 PM UTC 24 Sep 18 12:38:36 PM UTC 24 402302727 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3918883111 Sep 18 12:38:29 PM UTC 24 Sep 18 12:38:41 PM UTC 24 1013119458 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2757515777 Sep 18 12:38:38 PM UTC 24 Sep 18 12:38:44 PM UTC 24 98652139 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2813274255 Sep 18 12:37:40 PM UTC 24 Sep 18 12:38:47 PM UTC 24 3841079162 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3478757602 Sep 18 12:38:32 PM UTC 24 Sep 18 12:38:48 PM UTC 24 2426915043 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.477483493 Sep 18 12:38:31 PM UTC 24 Sep 18 12:38:48 PM UTC 24 524383609 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3854490156 Sep 18 12:38:28 PM UTC 24 Sep 18 12:38:49 PM UTC 24 880715807 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3233352704 Sep 18 12:38:34 PM UTC 24 Sep 18 12:38:52 PM UTC 24 1329516366 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.4158857012 Sep 18 12:37:23 PM UTC 24 Sep 18 12:38:53 PM UTC 24 1999741987 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.306938879 Sep 18 12:38:42 PM UTC 24 Sep 18 12:38:56 PM UTC 24 407997103 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3930351842 Sep 18 12:38:56 PM UTC 24 Sep 18 12:38:59 PM UTC 24 11919299 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2882592695 Sep 18 12:38:43 PM UTC 24 Sep 18 12:39:00 PM UTC 24 1119612295 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1417891244 Sep 18 12:38:01 PM UTC 24 Sep 18 12:39:02 PM UTC 24 1920688710 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2426457316 Sep 18 12:38:59 PM UTC 24 Sep 18 12:39:02 PM UTC 24 44287501 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1195700257 Sep 18 12:38:50 PM UTC 24 Sep 18 12:39:02 PM UTC 24 257963861 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.858462826 Sep 18 12:38:56 PM UTC 24 Sep 18 12:39:03 PM UTC 24 199596891 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.2674145684 Sep 18 12:39:03 PM UTC 24 Sep 18 12:39:08 PM UTC 24 36879825 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3595910951 Sep 18 12:38:49 PM UTC 24 Sep 18 12:39:08 PM UTC 24 729633031 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.3880365907 Sep 18 12:38:20 PM UTC 24 Sep 18 12:39:08 PM UTC 24 204171908 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.457253136 Sep 18 12:38:25 PM UTC 24 Sep 18 12:39:09 PM UTC 24 314562420 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3601448351 Sep 18 12:38:41 PM UTC 24 Sep 18 12:39:10 PM UTC 24 1908134057 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.1388029858 Sep 18 12:38:05 PM UTC 24 Sep 18 12:39:10 PM UTC 24 2196631493 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2908739990 Sep 18 12:39:03 PM UTC 24 Sep 18 12:39:12 PM UTC 24 275445895 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2622413761 Sep 18 12:39:09 PM UTC 24 Sep 18 12:39:12 PM UTC 24 11350278 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2705680510 Sep 18 12:39:04 PM UTC 24 Sep 18 12:39:15 PM UTC 24 597075655 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3474673193 Sep 18 12:38:44 PM UTC 24 Sep 18 12:39:15 PM UTC 24 1417217821 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.116350376 Sep 18 12:38:49 PM UTC 24 Sep 18 12:39:16 PM UTC 24 391870006 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.181506395 Sep 18 12:39:13 PM UTC 24 Sep 18 12:39:17 PM UTC 24 295313312 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2268743784 Sep 18 12:39:26 PM UTC 24 Sep 18 12:39:57 PM UTC 24 6256177093 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.299014049 Sep 18 12:39:09 PM UTC 24 Sep 18 12:39:18 PM UTC 24 1429226896 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2259446101 Sep 18 12:39:11 PM UTC 24 Sep 18 12:39:18 PM UTC 24 151680792 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.383609087 Sep 18 12:39:03 PM UTC 24 Sep 18 12:39:21 PM UTC 24 678392169 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.362197418 Sep 18 12:39:20 PM UTC 24 Sep 18 12:39:23 PM UTC 24 28742053 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2945447806 Sep 18 12:38:54 PM UTC 24 Sep 18 12:39:25 PM UTC 24 118105423 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.528824963 Sep 18 12:39:23 PM UTC 24 Sep 18 12:39:26 PM UTC 24 13232734 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1728347755 Sep 18 12:39:01 PM UTC 24 Sep 18 12:39:27 PM UTC 24 208454757 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1163117889 Sep 18 12:35:13 PM UTC 24 Sep 18 12:39:27 PM UTC 24 15743172187 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.2067283548 Sep 18 12:39:11 PM UTC 24 Sep 18 12:39:27 PM UTC 24 609367622 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.832076801 Sep 18 12:39:15 PM UTC 24 Sep 18 12:39:29 PM UTC 24 648916483 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3200926009 Sep 18 12:39:09 PM UTC 24 Sep 18 12:39:29 PM UTC 24 321427331 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.2738678996 Sep 18 12:39:28 PM UTC 24 Sep 18 12:39:31 PM UTC 24 25571994 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.536301608 Sep 18 12:39:17 PM UTC 24 Sep 18 12:39:31 PM UTC 24 212726740 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2812779415 Sep 18 12:39:22 PM UTC 24 Sep 18 12:39:32 PM UTC 24 373241486 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.1502418883 Sep 18 12:39:29 PM UTC 24 Sep 18 12:39:32 PM UTC 24 12625185 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2170366003 Sep 18 12:39:18 PM UTC 24 Sep 18 12:39:33 PM UTC 24 1162779209 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3325508262 Sep 18 12:39:19 PM UTC 24 Sep 18 12:39:35 PM UTC 24 855120679 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.2955016940 Sep 18 12:39:33 PM UTC 24 Sep 18 12:39:38 PM UTC 24 753502626 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.844888047 Sep 18 12:39:28 PM UTC 24 Sep 18 12:39:39 PM UTC 24 1144082761 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.3770653273 Sep 18 12:39:41 PM UTC 24 Sep 18 12:40:01 PM UTC 24 331871970 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3745354431 Sep 18 12:39:27 PM UTC 24 Sep 18 12:39:40 PM UTC 24 216255435 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.418204910 Sep 18 12:39:34 PM UTC 24 Sep 18 12:39:40 PM UTC 24 169872340 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.3256002833 Sep 18 12:39:29 PM UTC 24 Sep 18 12:39:41 PM UTC 24 237260035 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2761951338 Sep 18 12:38:50 PM UTC 24 Sep 18 12:39:42 PM UTC 24 1927842218 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1887039977 Sep 18 12:38:32 PM UTC 24 Sep 18 12:39:42 PM UTC 24 1366858426 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.2264556407 Sep 18 12:39:33 PM UTC 24 Sep 18 12:39:44 PM UTC 24 605932897 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3326293923 Sep 18 12:39:28 PM UTC 24 Sep 18 12:39:44 PM UTC 24 3817520652 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.191017547 Sep 18 12:39:42 PM UTC 24 Sep 18 12:39:45 PM UTC 24 20719419 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1790869011 Sep 18 12:39:45 PM UTC 24 Sep 18 12:39:47 PM UTC 24 10897481 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2079174548 Sep 18 12:39:33 PM UTC 24 Sep 18 12:39:48 PM UTC 24 555241278 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3441420679 Sep 18 12:39:43 PM UTC 24 Sep 18 12:39:48 PM UTC 24 53933738 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3718873023 Sep 18 12:39:36 PM UTC 24 Sep 18 12:39:50 PM UTC 24 578021035 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.1086397556 Sep 18 12:39:46 PM UTC 24 Sep 18 12:39:51 PM UTC 24 60725660 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2807663854 Sep 18 12:39:40 PM UTC 24 Sep 18 12:39:51 PM UTC 24 1466264525 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.3725190102 Sep 18 12:39:51 PM UTC 24 Sep 18 12:39:53 PM UTC 24 22963769 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2831358544 Sep 18 12:39:48 PM UTC 24 Sep 18 12:39:54 PM UTC 24 103243888 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.3640774215 Sep 18 12:39:11 PM UTC 24 Sep 18 12:39:55 PM UTC 24 4660741334 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.507638468 Sep 18 12:39:51 PM UTC 24 Sep 18 12:39:57 PM UTC 24 1197599403 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.3896783364 Sep 18 12:39:49 PM UTC 24 Sep 18 12:40:02 PM UTC 24 1917414252 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3055154927 Sep 18 12:39:41 PM UTC 24 Sep 18 12:40:00 PM UTC 24 302787162 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.3441542591 Sep 18 12:41:08 PM UTC 24 Sep 18 12:41:26 PM UTC 24 1874530297 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.490700980 Sep 18 12:39:12 PM UTC 24 Sep 18 12:40:05 PM UTC 24 4331818879 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.4252702357 Sep 18 12:39:49 PM UTC 24 Sep 18 12:40:05 PM UTC 24 1648395543 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.524656339 Sep 18 12:39:58 PM UTC 24 Sep 18 12:40:06 PM UTC 24 466059928 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1136058653 Sep 18 12:39:38 PM UTC 24 Sep 18 12:40:07 PM UTC 24 1201069698 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4276131297 Sep 18 12:39:49 PM UTC 24 Sep 18 12:40:08 PM UTC 24 237175577 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.4280208877 Sep 18 12:40:07 PM UTC 24 Sep 18 12:40:09 PM UTC 24 14978280 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.4221995751 Sep 18 12:39:55 PM UTC 24 Sep 18 12:40:10 PM UTC 24 1920018071 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2521995860 Sep 18 12:40:09 PM UTC 24 Sep 18 12:40:11 PM UTC 24 114325107 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1117370588 Sep 18 12:40:03 PM UTC 24 Sep 18 12:40:12 PM UTC 24 394032366 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.637551915 Sep 18 12:39:34 PM UTC 24 Sep 18 12:40:15 PM UTC 24 6664369878 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.4157648614 Sep 18 12:39:46 PM UTC 24 Sep 18 12:40:15 PM UTC 24 1648450668 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.746668149 Sep 18 12:40:13 PM UTC 24 Sep 18 12:40:17 PM UTC 24 83315897 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4000178195 Sep 18 12:40:08 PM UTC 24 Sep 18 12:40:17 PM UTC 24 318801358 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.153336699 Sep 18 12:40:01 PM UTC 24 Sep 18 12:40:17 PM UTC 24 670704984 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.3658398438 Sep 18 12:40:16 PM UTC 24 Sep 18 12:40:19 PM UTC 24 75361520 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1693675756 Sep 18 12:39:58 PM UTC 24 Sep 18 12:40:19 PM UTC 24 682899702 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.2289739497 Sep 18 12:40:10 PM UTC 24 Sep 18 12:40:23 PM UTC 24 111004310 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.3966155659 Sep 18 12:40:02 PM UTC 24 Sep 18 12:40:24 PM UTC 24 2451279917 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1190329813 Sep 18 12:39:33 PM UTC 24 Sep 18 12:40:27 PM UTC 24 3806750789 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.624703889 Sep 18 12:40:17 PM UTC 24 Sep 18 12:40:27 PM UTC 24 294303090 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3175419185 Sep 18 12:40:06 PM UTC 24 Sep 18 12:40:28 PM UTC 24 1895396019 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.1566679579 Sep 18 12:40:13 PM UTC 24 Sep 18 12:40:30 PM UTC 24 266525819 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1560426353 Sep 18 12:40:16 PM UTC 24 Sep 18 12:40:31 PM UTC 24 4262904164 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1414797765 Sep 18 12:40:18 PM UTC 24 Sep 18 12:40:33 PM UTC 24 1735506296 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.2369980594 Sep 18 12:39:55 PM UTC 24 Sep 18 12:40:33 PM UTC 24 4005267674 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.931551748 Sep 18 12:40:10 PM UTC 24 Sep 18 12:40:35 PM UTC 24 962158257 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3774186005 Sep 18 12:40:24 PM UTC 24 Sep 18 12:40:36 PM UTC 24 1761785169 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3713226174 Sep 18 12:40:34 PM UTC 24 Sep 18 12:40:37 PM UTC 24 97153566 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2466563530 Sep 18 12:40:29 PM UTC 24 Sep 18 12:40:38 PM UTC 24 472427131 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1536835289 Sep 18 12:40:34 PM UTC 24 Sep 18 12:40:39 PM UTC 24 34549346 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1278653420 Sep 18 12:40:36 PM UTC 24 Sep 18 12:40:39 PM UTC 24 15181317 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.4221542519 Sep 18 12:40:30 PM UTC 24 Sep 18 12:40:39 PM UTC 24 737706327 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.1252709610 Sep 18 12:40:26 PM UTC 24 Sep 18 12:40:41 PM UTC 24 5766501172 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3003314389 Sep 18 12:38:11 PM UTC 24 Sep 18 12:40:43 PM UTC 24 5006422087 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1753535670 Sep 18 12:40:28 PM UTC 24 Sep 18 12:40:43 PM UTC 24 161351005 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.2180282378 Sep 18 12:40:42 PM UTC 24 Sep 18 12:40:44 PM UTC 24 13472992 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1611420495 Sep 18 12:40:39 PM UTC 24 Sep 18 12:40:45 PM UTC 24 270926568 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3638914548 Sep 18 12:40:16 PM UTC 24 Sep 18 12:40:50 PM UTC 24 5521000529 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.4047408844 Sep 18 12:40:44 PM UTC 24 Sep 18 12:40:50 PM UTC 24 844833415 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.4141435341 Sep 18 12:40:40 PM UTC 24 Sep 18 12:40:50 PM UTC 24 276221270 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.807143058 Sep 18 12:40:28 PM UTC 24 Sep 18 12:40:51 PM UTC 24 3790858530 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2075725302 Sep 18 12:40:38 PM UTC 24 Sep 18 12:40:52 PM UTC 24 258055739 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3969759928 Sep 18 12:40:19 PM UTC 24 Sep 18 12:40:53 PM UTC 24 820804883 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1056037520 Sep 18 12:40:41 PM UTC 24 Sep 18 12:40:54 PM UTC 24 1029434464 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2734435262 Sep 18 12:39:42 PM UTC 24 Sep 18 12:40:56 PM UTC 24 4422136096 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3024908869 Sep 18 12:40:52 PM UTC 24 Sep 18 12:41:00 PM UTC 24 175293012 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3558575598 Sep 18 12:40:39 PM UTC 24 Sep 18 12:41:00 PM UTC 24 791205651 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1652724166 Sep 18 12:40:46 PM UTC 24 Sep 18 12:41:00 PM UTC 24 2016821251 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3860732903 Sep 18 12:40:52 PM UTC 24 Sep 18 12:41:01 PM UTC 24 1362675750 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3164765303 Sep 18 12:40:20 PM UTC 24 Sep 18 12:41:25 PM UTC 24 8774080094 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3665707520 Sep 18 12:41:02 PM UTC 24 Sep 18 12:41:04 PM UTC 24 12014537 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3440600229 Sep 18 12:41:01 PM UTC 24 Sep 18 12:41:04 PM UTC 24 23695719 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.4031967003 Sep 18 12:41:01 PM UTC 24 Sep 18 12:41:05 PM UTC 24 131113357 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.3192515479 Sep 18 12:40:45 PM UTC 24 Sep 18 12:41:07 PM UTC 24 2875435189 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1893515973 Sep 18 12:40:54 PM UTC 24 Sep 18 12:41:09 PM UTC 24 379503263 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.303827198 Sep 18 12:40:55 PM UTC 24 Sep 18 12:41:10 PM UTC 24 326745635 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3878992023 Sep 18 12:41:05 PM UTC 24 Sep 18 12:41:10 PM UTC 24 69397673 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3953997463 Sep 18 12:40:06 PM UTC 24 Sep 18 12:41:10 PM UTC 24 745175951 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.838238119 Sep 18 12:39:52 PM UTC 24 Sep 18 12:41:12 PM UTC 24 5302767444 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2968631338 Sep 18 12:40:37 PM UTC 24 Sep 18 12:41:12 PM UTC 24 1269306953 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.4081216606 Sep 18 12:41:06 PM UTC 24 Sep 18 12:41:13 PM UTC 24 224516445 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.161275862 Sep 18 12:41:05 PM UTC 24 Sep 18 12:41:14 PM UTC 24 364824190 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.788251880 Sep 18 12:41:03 PM UTC 24 Sep 18 12:41:15 PM UTC 24 227179520 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2263042755 Sep 18 12:41:10 PM UTC 24 Sep 18 12:41:16 PM UTC 24 265108341 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.716177605 Sep 18 12:39:57 PM UTC 24 Sep 18 12:41:16 PM UTC 24 2977701415 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3265185198 Sep 18 12:40:54 PM UTC 24 Sep 18 12:41:16 PM UTC 24 1045773862 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3730807549 Sep 18 12:40:52 PM UTC 24 Sep 18 12:41:17 PM UTC 24 5290533290 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2693940555 Sep 18 12:41:16 PM UTC 24 Sep 18 12:41:19 PM UTC 24 24770336 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.2210841577 Sep 18 12:41:11 PM UTC 24 Sep 18 12:41:19 PM UTC 24 284734757 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.61313792 Sep 18 12:41:17 PM UTC 24 Sep 18 12:41:19 PM UTC 24 12945492 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.3578773343 Sep 18 12:39:41 PM UTC 24 Sep 18 12:41:21 PM UTC 24 8348077363 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3080787292 Sep 18 12:41:17 PM UTC 24 Sep 18 12:41:21 PM UTC 24 38468740 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.4177912179 Sep 18 12:41:19 PM UTC 24 Sep 18 12:41:22 PM UTC 24 170842981 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.1492816199 Sep 18 12:41:17 PM UTC 24 Sep 18 12:41:23 PM UTC 24 154917238 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2567384666 Sep 18 12:41:05 PM UTC 24 Sep 18 12:41:23 PM UTC 24 269927860 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.3673239307 Sep 18 12:41:03 PM UTC 24 Sep 18 12:41:23 PM UTC 24 185406895 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1004876984 Sep 18 12:41:14 PM UTC 24 Sep 18 12:41:27 PM UTC 24 1224810167 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.16771378 Sep 18 12:41:24 PM UTC 24 Sep 18 12:41:29 PM UTC 24 278609848 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.2457593897 Sep 18 12:41:22 PM UTC 24 Sep 18 12:41:30 PM UTC 24 842081723 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2146219846 Sep 18 12:41:24 PM UTC 24 Sep 18 12:41:31 PM UTC 24 208025921 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3329016907 Sep 18 12:41:20 PM UTC 24 Sep 18 12:41:33 PM UTC 24 1205082678 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3267491484 Sep 18 12:40:17 PM UTC 24 Sep 18 12:41:33 PM UTC 24 3446988685 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3752571541 Sep 18 12:41:12 PM UTC 24 Sep 18 12:41:34 PM UTC 24 1225456543 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1973701332 Sep 18 12:40:33 PM UTC 24 Sep 18 12:41:34 PM UTC 24 7424551755 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.999852953 Sep 18 12:41:32 PM UTC 24 Sep 18 12:41:34 PM UTC 24 41837504 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.189527461 Sep 18 12:41:33 PM UTC 24 Sep 18 12:41:37 PM UTC 24 91365846 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4102538457 Sep 18 12:41:35 PM UTC 24 Sep 18 12:41:37 PM UTC 24 45319486 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.2913393364 Sep 18 12:41:26 PM UTC 24 Sep 18 12:41:38 PM UTC 24 284197399 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.1810452796 Sep 18 12:41:36 PM UTC 24 Sep 18 12:41:39 PM UTC 24 40009263 ps
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