Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58359017

1

T1

1296

T2

1230

T3

1142

auto[1]

1144397

1

T3

99

T22

495

T23

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58365203

1

T1

1296

T2

1230

T3

1241

auto[1]

1138211

1

T22

99

T23

297

T21

990

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5589466	1			T1	77		T2	95		T3	210
auto[IdleSt]	16274944	1			T1	16		T2	1135		T3	875
auto[ClkMuxSt]	29073	1			T1	1		T3	1		T4	9
auto[CntIncrSt]	28913	1			T1	1		T3	1		T4	9
auto[CntProgSt]	1245782	1			T1	16		T3	2		T4	18
auto[TransCheckSt]	22833	1			T1	1		T4	9		T5	8
auto[TokenHashSt]	14382992	1			T1	32		T4	517		T5	340
auto[FlashRmaSt]	29105	1			T4	9		T5	37		T13	9
auto[TokenCheck0St]	10317	1			T4	9		T5	8		T13	9
auto[TokenCheck1St]	7410	1			T4	9		T5	8		T13	9
auto[TransProgSt]	301483	1			T4	18		T5	155		T13	18
auto[PostTransSt]	8621421	1			T1	1152		T3	51		T4	1155
auto[ScrapSt]	105035	1			T13	33		T34	902		T18	16
auto[EscalateSt]	4880844	1			T3	101		T22	1362		T23	1767
auto[InvalidSt]	7972404	1			T22	998		T23	1272		T10	15149

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1392	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7972404	1			T22	998		T23	1272		T10	15149
EscalateSt	4880844	1			T3	101		T22	1362		T23	1767
ScrapSt	105035	1			T13	33		T34	902		T18	16
PostTransSt	8621421	1			T1	1152		T3	51		T4	1155
TransProgSt	301483	1			T4	18		T5	155		T13	18
TokenCheck1St	7410	1			T4	9		T5	8		T13	9
TokenCheck0St	10317	1			T4	9		T5	8		T13	9
FlashRmaSt	29105	1			T4	9		T5	37		T13	9
TokenHashSt	14382992	1			T1	32		T4	517		T5	340
TransCheckSt	22833	1			T1	1		T4	9		T5	8
CntProgSt	1245782	1			T1	16		T3	2		T4	18
CntIncrSt	28913	1			T1	1		T3	1		T4	9
ClkMuxSt	29073	1			T1	1		T3	1		T4	9
IdleSt	16274944	1			T1	16		T2	1135		T3	875
ResetSt	5589466	1			T1	77		T2	95		T3	210
arcs[ResetSt=>IdleSt]	42833	1			T1	1		T2	1		T3	2
arcs[IdleSt=>ScrapSt]	254	1			T13	3		T34	1		T18	4
arcs[IdleSt=>ClkMuxSt]	28963	1			T1	1		T3	1		T4	9
arcs[ClkMuxSt=>CntIncrSt]	28913	1			T1	1		T3	1		T4	9
arcs[CntIncrSt=>PostTransSt]	1309	1			T19	5		T15	13		T28	10
arcs[CntIncrSt=>CntProgSt]	27524	1			T1	1		T3	1		T4	9
arcs[CntProgSt=>PostTransSt]	3653	1			T3	1		T21	18		T19	14
arcs[CntProgSt=>TransCheckSt]	22833	1			T1	1		T4	9		T5	8
arcs[TransCheckSt=>PostTransSt]	3087	1			T19	9		T15	6		T25	29
arcs[TransCheckSt=>TokenHashSt]	19653	1			T1	1		T4	9		T5	8
arcs[TokenHashSt=>PostTransSt]	8549	1			T1	1		T12	1		T19	25
arcs[TokenHashSt=>FlashRmaSt]	10361	1			T4	9		T5	8		T13	9
arcs[FlashRmaSt=>TokenCheck0St]	10317	1			T4	9		T5	8		T13	9
arcs[TokenCheck0St=>PostTransSt]	2843	1			T19	3		T15	11		T25	14
arcs[TokenCheck0St=>TokenCheck1St]	7410	1			T4	9		T5	8		T13	9
arcs[TokenCheck1St=>PostTransSt]	611	1			T19	1		T15	1		T25	9
arcs[TransProgSt=>PostTransSt]	5939	1			T4	9		T5	8		T13	9
arcs[IdleSt=>EscalateSt]	189	1			T18	6		T16	3		T58	4
arcs[ClkMuxSt=>EscalateSt]	50	1			T18	1		T16	2		T58	2
arcs[CntIncrSt=>EscalateSt]	80	1			T16	1		T58	3		T59	3
arcs[CntProgSt=>EscalateSt]	1038	1			T18	2		T16	29		T58	6
arcs[TransCheckSt=>EscalateSt]	93	1			T18	2		T58	3		T59	1
arcs[TokenHashSt=>EscalateSt]	742	1			T18	26		T16	7		T58	30
arcs[FlashRmaSt=>EscalateSt]	44	1			T59	1		T60	2		T61	1
arcs[TokenCheck0St=>EscalateSt]	64	1			T58	1		T59	4		T60	2
arcs[TokenCheck1St=>EscalateSt]	24	1			T65	2		T66	1		T67	1
arcs[TransProgSt=>EscalateSt]	836	1			T18	9		T16	22		T58	7
arcs[PostTransSt=>EscalateSt]	3991	1			T3	1		T21	18		T18	20
arcs[InvalidSt=>EscalateSt]	9977	1			T22	6		T23	7		T10	7

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5589323	1			T1	77		T2	95		T3	210
auto[0]	auto[IdleSt]	16274818	1			T1	16		T2	1135		T3	875
auto[0]	auto[ClkMuxSt]	29037	1			T1	1		T3	1		T4	9
auto[0]	auto[CntIncrSt]	28860	1			T1	1		T3	1		T4	9
auto[0]	auto[CntProgSt]	1245080	1			T1	16		T3	2		T4	18
auto[0]	auto[TransCheckSt]	22774	1			T1	1		T4	9		T5	8
auto[0]	auto[TokenHashSt]	14382509	1			T1	32		T4	517		T5	340
auto[0]	auto[FlashRmaSt]	29070	1			T4	9		T5	37		T13	9
auto[0]	auto[TokenCheck0St]	10270	1			T4	9		T5	8		T13	9
auto[0]	auto[TokenCheck1St]	7392	1			T4	9		T5	8		T13	9
auto[0]	auto[TransProgSt]	300936	1			T4	18		T5	155		T13	18
auto[0]	auto[PostTransSt]	8619343	1			T1	1152		T3	50		T4	1155
auto[0]	auto[ScrapSt]	104996	1			T13	33		T34	902		T18	14
auto[0]	auto[EscalateSt]	3745800	1			T3	3		T22	872		T23	1375
auto[0]	auto[InvalidSt]	7967417	1			T22	993		T23	1268		T10	15146
auto[1]	auto[ResetSt]	143	1			T18	6		T16	3		T58	1
auto[1]	auto[IdleSt]	126	1			T18	5		T16	2		T58	3
auto[1]	auto[ClkMuxSt]	36	1			T18	1		T58	1		T59	3
auto[1]	auto[CntIncrSt]	53	1			T16	1		T58	1		T59	3
auto[1]	auto[CntProgSt]	702	1			T18	2		T16	24		T58	3
auto[1]	auto[TransCheckSt]	59	1			T18	1		T58	2		T59	1
auto[1]	auto[TokenHashSt]	483	1			T18	19		T16	3		T58	21
auto[1]	auto[FlashRmaSt]	35	1			T60	2		T100	1		T225	1
auto[1]	auto[TokenCheck0St]	47	1			T58	1		T59	1		T60	2
auto[1]	auto[TokenCheck1St]	18	1			T65	1		T66	1		T67	1
auto[1]	auto[TransProgSt]	547	1			T18	4		T16	17		T58	6
auto[1]	auto[PostTransSt]	2078	1			T3	1		T21	8		T18	17
auto[1]	auto[ScrapSt]	39	1			T18	2		T58	1		T59	1
auto[1]	auto[EscalateSt]	1135044	1			T3	98		T22	490		T23	392
auto[1]	auto[InvalidSt]	4987	1			T22	5		T23	4		T10	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5589308	1			T1	77		T2	95		T3	210
auto[0]	auto[IdleSt]	16274826	1			T1	16		T2	1135		T3	875
auto[0]	auto[ClkMuxSt]	29039	1			T1	1		T3	1		T4	9
auto[0]	auto[CntIncrSt]	28863	1			T1	1		T3	1		T4	9
auto[0]	auto[CntProgSt]	1245100	1			T1	16		T3	2		T4	18
auto[0]	auto[TransCheckSt]	22765	1			T1	1		T4	9		T5	8
auto[0]	auto[TokenHashSt]	14382497	1			T1	32		T4	517		T5	340
auto[0]	auto[FlashRmaSt]	29078	1			T4	9		T5	37		T13	9
auto[0]	auto[TokenCheck0St]	10278	1			T4	9		T5	8		T13	9
auto[0]	auto[TokenCheck1St]	7396	1			T4	9		T5	8		T13	9
auto[0]	auto[TransProgSt]	300933	1			T4	18		T5	155		T13	18
auto[0]	auto[PostTransSt]	8619405	1			T1	1152		T3	51		T4	1155
auto[0]	auto[ScrapSt]	104997	1			T13	33		T34	902		T18	13
auto[0]	auto[EscalateSt]	3751912	1			T3	101		T22	1264		T23	1473
auto[0]	auto[InvalidSt]	7967414	1			T22	997		T23	1269		T10	15145
auto[1]	auto[ResetSt]	158	1			T18	4		T16	1		T58	4
auto[1]	auto[IdleSt]	118	1			T18	4		T16	1		T58	3
auto[1]	auto[ClkMuxSt]	34	1			T18	1		T16	2		T58	1
auto[1]	auto[CntIncrSt]	50	1			T16	1		T58	2		T60	1
auto[1]	auto[CntProgSt]	682	1			T18	1		T16	17		T58	3
auto[1]	auto[TransCheckSt]	68	1			T18	2		T58	2		T100	2
auto[1]	auto[TokenHashSt]	495	1			T18	14		T16	5		T58	19
auto[1]	auto[FlashRmaSt]	27	1			T59	1		T60	2		T61	1
auto[1]	auto[TokenCheck0St]	39	1			T59	3		T60	1		T100	1
auto[1]	auto[TokenCheck1St]	14	1			T65	1		T226	2		T227	1
auto[1]	auto[TransProgSt]	550	1			T18	7		T16	13		T58	6
auto[1]	auto[PostTransSt]	2016	1			T21	10		T18	10		T19	9
auto[1]	auto[ScrapSt]	38	1			T18	3		T58	1		T60	3
auto[1]	auto[EscalateSt]	1128932	1			T22	98		T23	294		T21	980
auto[1]	auto[InvalidSt]	4990	1			T22	1		T23	3		T10	4