Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 97.90 95.38 93.40 100.00 98.49 98.76 96.29


Total tests in report: 1004
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.46 60.46 79.96 79.96 51.66 51.66 46.97 46.97 35.71 35.71 68.17 68.17 91.79 91.79 48.94 48.94 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2377304728
72.83 12.37 87.32 7.36 79.67 28.00 68.77 21.79 40.48 4.76 79.14 10.97 94.53 2.74 59.89 10.95 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3031339532
80.46 7.63 89.52 2.20 81.15 1.48 76.82 8.06 64.29 23.81 90.32 11.18 95.02 0.50 66.08 6.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.157393340
85.01 4.55 96.37 6.85 82.16 1.02 84.09 7.27 71.43 7.14 93.55 3.23 95.02 0.00 72.44 6.36 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3543409878
88.71 3.70 96.68 0.31 85.58 3.42 87.25 3.16 80.95 9.52 94.84 1.29 95.27 0.25 80.39 7.95 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1818487486
90.32 1.61 96.68 0.00 85.77 0.18 87.25 0.00 90.48 9.52 94.84 0.00 95.27 0.00 81.98 1.59 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3502427082
91.50 1.18 96.83 0.15 87.62 1.85 87.29 0.04 90.48 0.00 95.05 0.22 96.52 1.24 86.75 4.77 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1732742270
92.32 0.82 96.93 0.10 88.35 0.74 87.87 0.59 92.86 2.38 95.48 0.43 96.77 0.25 87.99 1.24 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.53094076
92.90 0.58 97.09 0.15 89.65 1.29 88.02 0.14 92.86 0.00 96.13 0.65 97.01 0.25 89.58 1.59 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3259982779
93.42 0.52 97.19 0.10 89.74 0.09 90.00 1.98 92.86 0.00 96.34 0.22 97.01 0.00 90.81 1.24 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1952698731
93.79 0.37 97.19 0.00 89.74 0.00 90.00 0.00 95.24 2.38 96.34 0.00 97.01 0.00 90.99 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3405010244
94.13 0.34 97.24 0.05 90.76 1.02 90.00 0.00 95.24 0.00 96.77 0.43 97.01 0.00 91.87 0.88 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1212969012
94.47 0.34 97.24 0.00 90.76 0.00 90.00 0.00 97.62 2.38 96.77 0.00 97.01 0.00 91.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.1472170589
94.81 0.34 97.24 0.00 90.76 0.00 90.00 0.00 100.00 2.38 96.77 0.00 97.01 0.00 91.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.1430957960
95.15 0.34 97.29 0.05 90.85 0.09 90.43 0.43 100.00 0.00 96.99 0.22 97.01 0.00 93.46 1.59 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1658363807
95.37 0.22 97.65 0.36 91.77 0.92 90.70 0.27 100.00 0.00 96.99 0.00 97.01 0.00 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.619547138
95.58 0.21 97.65 0.00 91.77 0.00 90.70 0.00 100.00 0.00 96.99 0.00 98.51 1.49 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.366261966
95.79 0.20 97.65 0.00 91.77 0.00 92.12 1.42 100.00 0.00 96.99 0.00 98.51 0.00 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1550909219
95.99 0.20 97.70 0.05 92.70 0.92 92.12 0.00 100.00 0.00 97.42 0.43 98.51 0.00 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2011850110
96.12 0.13 97.80 0.10 92.70 0.00 92.18 0.06 100.00 0.00 97.63 0.22 98.51 0.00 93.99 0.53 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.2040359476
96.24 0.12 97.90 0.10 92.70 0.00 92.30 0.12 100.00 0.00 98.28 0.65 98.51 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1739728287
96.36 0.12 97.90 0.00 92.98 0.28 92.30 0.00 100.00 0.00 98.28 0.00 98.51 0.00 94.52 0.53 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1446357826
96.45 0.10 97.90 0.00 92.98 0.00 92.97 0.67 100.00 0.00 98.28 0.00 98.51 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.195795185
96.50 0.05 97.90 0.00 93.16 0.18 92.97 0.00 100.00 0.00 98.28 0.00 98.51 0.00 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.665118737
96.55 0.05 97.90 0.00 93.16 0.00 92.97 0.00 100.00 0.00 98.28 0.00 98.51 0.00 95.05 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.1359340912
96.60 0.05 97.90 0.00 93.25 0.09 92.99 0.02 100.00 0.00 98.49 0.22 98.51 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.4087184872
96.64 0.04 97.90 0.00 93.25 0.00 93.27 0.28 100.00 0.00 98.49 0.00 98.51 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2160373036
96.68 0.04 97.90 0.00 93.25 0.00 93.37 0.10 100.00 0.00 98.49 0.00 98.51 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1122025920
96.72 0.04 97.90 0.00 93.53 0.28 93.37 0.00 100.00 0.00 98.49 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4199588315
96.76 0.04 97.90 0.00 93.81 0.28 93.37 0.00 100.00 0.00 98.49 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3505418616
96.80 0.04 97.90 0.00 94.09 0.28 93.37 0.00 100.00 0.00 98.49 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.3169255363
96.83 0.04 97.90 0.00 94.09 0.00 93.37 0.00 100.00 0.00 98.49 0.00 98.76 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1656189921
96.86 0.03 97.90 0.00 94.09 0.00 93.39 0.02 100.00 0.00 98.49 0.00 98.76 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3618667937
96.89 0.03 97.90 0.00 94.09 0.00 93.40 0.01 100.00 0.00 98.49 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3333943270
96.92 0.03 97.90 0.00 94.27 0.18 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2192189699
96.94 0.03 97.90 0.00 94.45 0.18 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.390007628
96.97 0.03 97.90 0.00 94.64 0.18 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1756281999
96.99 0.03 97.90 0.00 94.64 0.00 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.889683022
97.02 0.03 97.90 0.00 94.64 0.00 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3189535777
97.04 0.03 97.90 0.00 94.64 0.00 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2560683826
97.07 0.03 97.90 0.00 94.64 0.00 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3640001679
97.08 0.01 97.90 0.00 94.73 0.09 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3789978938
97.10 0.01 97.90 0.00 94.82 0.09 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2829373282
97.11 0.01 97.90 0.00 94.92 0.09 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.218468532
97.12 0.01 97.90 0.00 95.01 0.09 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3114301825
97.14 0.01 97.90 0.00 95.10 0.09 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1671224341
97.15 0.01 97.90 0.00 95.19 0.09 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.329419003
97.16 0.01 97.90 0.00 95.29 0.09 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2809411982
97.17 0.01 97.90 0.00 95.38 0.09 93.40 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.2829071306

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.622630938
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1102062450
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2985839877
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1725627603
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.263201839
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.251816615
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3044153858
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.38579872
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1550680651
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2597263720
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4035887216
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1628097851
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1380237005
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.731916520
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.167007322
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3027313711
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3464727492
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3604650503
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1436901108
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2242971908
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2738374717
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1573054224
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.401838317
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2209359965
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3759959292
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2990326969
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.374451449
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.364580281
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1726306544
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.463700811
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3689901950
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3880188981
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3284204747
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3846569753
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.490523345
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.940795119
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4007187314
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.475006165
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Total test records in report: 1004
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.889683022 Sep 24 12:36:45 PM UTC 24 Sep 24 12:36:47 PM UTC 24 13963958 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3333943270 Sep 24 12:36:45 PM UTC 24 Sep 24 12:36:47 PM UTC 24 12324823 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1594649503 Sep 24 12:36:45 PM UTC 24 Sep 24 12:36:48 PM UTC 24 51757668 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.4051117224 Sep 24 12:36:45 PM UTC 24 Sep 24 12:36:49 PM UTC 24 30691981 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.619547138 Sep 24 12:36:47 PM UTC 24 Sep 24 12:36:50 PM UTC 24 116638214 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1025596597 Sep 24 12:36:47 PM UTC 24 Sep 24 12:36:51 PM UTC 24 124157196 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1185052019 Sep 24 12:36:45 PM UTC 24 Sep 24 12:36:51 PM UTC 24 217971639 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1885424355 Sep 24 12:36:49 PM UTC 24 Sep 24 12:36:51 PM UTC 24 23893583 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1739728287 Sep 24 12:36:49 PM UTC 24 Sep 24 12:36:53 PM UTC 24 74807645 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2377304728 Sep 24 12:36:45 PM UTC 24 Sep 24 12:36:53 PM UTC 24 248142812 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1523537240 Sep 24 12:36:49 PM UTC 24 Sep 24 12:36:53 PM UTC 24 64647741 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2603384386 Sep 24 12:36:51 PM UTC 24 Sep 24 12:36:54 PM UTC 24 10591853 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.1715778080 Sep 24 12:36:45 PM UTC 24 Sep 24 12:36:54 PM UTC 24 279800585 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1122025920 Sep 24 12:36:49 PM UTC 24 Sep 24 12:36:56 PM UTC 24 66492759 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.157393340 Sep 24 12:36:45 PM UTC 24 Sep 24 12:36:56 PM UTC 24 1043392497 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3259982779 Sep 24 12:36:55 PM UTC 24 Sep 24 12:37:00 PM UTC 24 211198245 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3127747356 Sep 24 12:36:45 PM UTC 24 Sep 24 12:37:01 PM UTC 24 2319380091 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3031339532 Sep 24 12:36:45 PM UTC 24 Sep 24 12:37:01 PM UTC 24 2377238116 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2170995368 Sep 24 12:36:47 PM UTC 24 Sep 24 12:37:01 PM UTC 24 1006146233 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3257604882 Sep 24 12:36:47 PM UTC 24 Sep 24 12:37:01 PM UTC 24 1465510340 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2868925509 Sep 24 12:36:50 PM UTC 24 Sep 24 12:37:03 PM UTC 24 301043646 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1658363807 Sep 24 12:36:47 PM UTC 24 Sep 24 12:37:04 PM UTC 24 1974152969 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2295483557 Sep 24 12:36:51 PM UTC 24 Sep 24 12:37:05 PM UTC 24 1575415030 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3543409878 Sep 24 12:36:47 PM UTC 24 Sep 24 12:37:05 PM UTC 24 323929261 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.2610190600 Sep 24 12:36:52 PM UTC 24 Sep 24 12:37:06 PM UTC 24 415495530 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1207297934 Sep 24 12:36:47 PM UTC 24 Sep 24 12:37:06 PM UTC 24 1495429587 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1446419436 Sep 24 12:36:49 PM UTC 24 Sep 24 12:37:09 PM UTC 24 416597345 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1623314409 Sep 24 12:37:06 PM UTC 24 Sep 24 12:37:09 PM UTC 24 21170507 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1501912025 Sep 24 12:37:06 PM UTC 24 Sep 24 12:37:09 PM UTC 24 55717501 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3189535777 Sep 24 12:37:08 PM UTC 24 Sep 24 12:37:10 PM UTC 24 17528279 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1579755123 Sep 24 12:37:06 PM UTC 24 Sep 24 12:37:11 PM UTC 24 36423238 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3618667937 Sep 24 12:37:06 PM UTC 24 Sep 24 12:37:11 PM UTC 24 120208005 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.4009478868 Sep 24 12:36:51 PM UTC 24 Sep 24 12:37:12 PM UTC 24 995959797 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.195795185 Sep 24 12:36:45 PM UTC 24 Sep 24 12:37:12 PM UTC 24 345559644 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2623580340 Sep 24 12:36:57 PM UTC 24 Sep 24 12:37:12 PM UTC 24 566294437 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.3263075263 Sep 24 12:37:06 PM UTC 24 Sep 24 12:37:12 PM UTC 24 47184260 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.3752175170 Sep 24 12:36:56 PM UTC 24 Sep 24 12:37:13 PM UTC 24 2451417076 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.366995060 Sep 24 12:36:57 PM UTC 24 Sep 24 12:37:14 PM UTC 24 1602250737 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.2040359476 Sep 24 12:36:55 PM UTC 24 Sep 24 12:37:14 PM UTC 24 9611183063 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1917667955 Sep 24 12:36:45 PM UTC 24 Sep 24 12:37:15 PM UTC 24 4013032812 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.134234553 Sep 24 12:37:16 PM UTC 24 Sep 24 12:37:43 PM UTC 24 116139321 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2356540283 Sep 24 12:37:09 PM UTC 24 Sep 24 12:37:15 PM UTC 24 741889092 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.3596387641 Sep 24 12:37:12 PM UTC 24 Sep 24 12:37:17 PM UTC 24 216377263 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.4213155225 Sep 24 12:37:16 PM UTC 24 Sep 24 12:37:18 PM UTC 24 23712496 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1052420692 Sep 24 12:36:47 PM UTC 24 Sep 24 12:37:18 PM UTC 24 277924775 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.1701652805 Sep 24 12:37:13 PM UTC 24 Sep 24 12:37:19 PM UTC 24 1400553187 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1233677537 Sep 24 12:37:13 PM UTC 24 Sep 24 12:37:20 PM UTC 24 140511337 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2080004195 Sep 24 12:37:16 PM UTC 24 Sep 24 12:37:20 PM UTC 24 51601055 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1121407857 Sep 24 12:37:18 PM UTC 24 Sep 24 12:37:21 PM UTC 24 15088890 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.4134261505 Sep 24 12:37:08 PM UTC 24 Sep 24 12:37:23 PM UTC 24 324424983 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3834817730 Sep 24 12:36:55 PM UTC 24 Sep 24 12:37:24 PM UTC 24 701810803 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3052920629 Sep 24 12:36:55 PM UTC 24 Sep 24 12:37:24 PM UTC 24 6750327771 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3951964981 Sep 24 12:37:08 PM UTC 24 Sep 24 12:37:25 PM UTC 24 234067812 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3158346081 Sep 24 12:37:06 PM UTC 24 Sep 24 12:37:25 PM UTC 24 1189915062 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.4152498146 Sep 24 12:37:14 PM UTC 24 Sep 24 12:37:25 PM UTC 24 1296343630 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2560683826 Sep 24 12:37:24 PM UTC 24 Sep 24 12:37:26 PM UTC 24 36583594 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1480884961 Sep 24 12:37:20 PM UTC 24 Sep 24 12:37:26 PM UTC 24 99587318 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.238210961 Sep 24 12:37:13 PM UTC 24 Sep 24 12:37:28 PM UTC 24 238892594 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.942471531 Sep 24 12:37:08 PM UTC 24 Sep 24 12:37:28 PM UTC 24 1681609975 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2346545980 Sep 24 12:36:45 PM UTC 24 Sep 24 12:37:28 PM UTC 24 4935823411 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.2929606744 Sep 24 12:37:10 PM UTC 24 Sep 24 12:37:30 PM UTC 24 1468585219 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.4084655694 Sep 24 12:37:13 PM UTC 24 Sep 24 12:37:31 PM UTC 24 3762424136 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.2446988150 Sep 24 12:37:19 PM UTC 24 Sep 24 12:37:31 PM UTC 24 2106135109 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.2625660643 Sep 24 12:37:21 PM UTC 24 Sep 24 12:37:31 PM UTC 24 253593890 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3413699119 Sep 24 12:37:06 PM UTC 24 Sep 24 12:37:32 PM UTC 24 173001676 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1724910882 Sep 24 12:37:26 PM UTC 24 Sep 24 12:37:33 PM UTC 24 242086139 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3040397472 Sep 24 12:36:56 PM UTC 24 Sep 24 12:37:33 PM UTC 24 978311437 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.96263326 Sep 24 12:37:25 PM UTC 24 Sep 24 12:37:34 PM UTC 24 2663445922 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.4066208337 Sep 24 12:37:27 PM UTC 24 Sep 24 12:37:34 PM UTC 24 646710718 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1013249365 Sep 24 12:37:20 PM UTC 24 Sep 24 12:37:35 PM UTC 24 307823126 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2429276594 Sep 24 12:37:14 PM UTC 24 Sep 24 12:37:35 PM UTC 24 792222960 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.3085506994 Sep 24 12:37:33 PM UTC 24 Sep 24 12:37:36 PM UTC 24 28409430 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1245135072 Sep 24 12:37:34 PM UTC 24 Sep 24 12:37:37 PM UTC 24 67803065 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.2072599024 Sep 24 12:37:33 PM UTC 24 Sep 24 12:37:39 PM UTC 24 111420251 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3403028685 Sep 24 12:36:45 PM UTC 24 Sep 24 12:37:40 PM UTC 24 4167671030 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1818487486 Sep 24 12:36:47 PM UTC 24 Sep 24 12:37:40 PM UTC 24 9054796372 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.3368726583 Sep 24 12:37:37 PM UTC 24 Sep 24 12:37:40 PM UTC 24 37280575 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1311726386 Sep 24 12:37:13 PM UTC 24 Sep 24 12:37:40 PM UTC 24 1623477529 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1408150099 Sep 24 12:37:35 PM UTC 24 Sep 24 12:37:41 PM UTC 24 166680413 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.53094076 Sep 24 12:37:06 PM UTC 24 Sep 24 12:37:43 PM UTC 24 271082462 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1396699581 Sep 24 12:37:29 PM UTC 24 Sep 24 12:37:44 PM UTC 24 1697076455 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3654044677 Sep 24 12:37:29 PM UTC 24 Sep 24 12:37:44 PM UTC 24 3296129293 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.3935375614 Sep 24 12:37:27 PM UTC 24 Sep 24 12:37:45 PM UTC 24 3171190783 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2477289279 Sep 24 12:37:41 PM UTC 24 Sep 24 12:37:45 PM UTC 24 102894891 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2719477317 Sep 24 12:37:22 PM UTC 24 Sep 24 12:37:46 PM UTC 24 631705628 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.369258548 Sep 24 12:37:35 PM UTC 24 Sep 24 12:37:46 PM UTC 24 75678352 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3329262783 Sep 24 12:37:12 PM UTC 24 Sep 24 12:37:47 PM UTC 24 7065341230 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2745884609 Sep 24 12:37:36 PM UTC 24 Sep 24 12:37:48 PM UTC 24 485942216 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2160343881 Sep 24 12:37:41 PM UTC 24 Sep 24 12:37:48 PM UTC 24 232582234 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3240138849 Sep 24 12:37:35 PM UTC 24 Sep 24 12:37:48 PM UTC 24 3775192970 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.413836838 Sep 24 12:37:26 PM UTC 24 Sep 24 12:37:49 PM UTC 24 396708879 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.331309344 Sep 24 12:36:53 PM UTC 24 Sep 24 12:37:49 PM UTC 24 2834174680 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1887181980 Sep 24 12:37:47 PM UTC 24 Sep 24 12:37:50 PM UTC 24 33640037 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.3173778704 Sep 24 12:37:47 PM UTC 24 Sep 24 12:37:50 PM UTC 24 55069971 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.358516259 Sep 24 12:37:48 PM UTC 24 Sep 24 12:37:50 PM UTC 24 11749242 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2614682756 Sep 24 12:37:42 PM UTC 24 Sep 24 12:37:51 PM UTC 24 2154686371 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.547021594 Sep 24 12:37:50 PM UTC 24 Sep 24 12:37:53 PM UTC 24 13257770 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1684770062 Sep 24 12:37:45 PM UTC 24 Sep 24 12:37:53 PM UTC 24 242019471 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.1455001053 Sep 24 12:37:49 PM UTC 24 Sep 24 12:37:54 PM UTC 24 226337953 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.2620300998 Sep 24 12:37:45 PM UTC 24 Sep 24 12:37:55 PM UTC 24 281587886 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1899074023 Sep 24 12:37:46 PM UTC 24 Sep 24 12:37:55 PM UTC 24 587893177 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.2673018325 Sep 24 12:37:36 PM UTC 24 Sep 24 12:37:55 PM UTC 24 430403732 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1936170509 Sep 24 12:37:19 PM UTC 24 Sep 24 12:37:58 PM UTC 24 1396531695 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3283395969 Sep 24 12:37:29 PM UTC 24 Sep 24 12:37:59 PM UTC 24 5150071880 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3393643842 Sep 24 12:37:45 PM UTC 24 Sep 24 12:38:00 PM UTC 24 265942638 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2678016899 Sep 24 12:37:51 PM UTC 24 Sep 24 12:38:00 PM UTC 24 994290912 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2746650187 Sep 24 12:37:30 PM UTC 24 Sep 24 12:38:00 PM UTC 24 996079182 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.771306280 Sep 24 12:37:49 PM UTC 24 Sep 24 12:38:03 PM UTC 24 78857648 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3696650974 Sep 24 12:37:55 PM UTC 24 Sep 24 12:38:03 PM UTC 24 1758538288 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3516369776 Sep 24 12:37:56 PM UTC 24 Sep 24 12:38:04 PM UTC 24 321585890 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.232459877 Sep 24 12:38:01 PM UTC 24 Sep 24 12:38:04 PM UTC 24 18404661 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.841465660 Sep 24 12:37:50 PM UTC 24 Sep 24 12:38:04 PM UTC 24 3319128595 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2048949446 Sep 24 12:37:41 PM UTC 24 Sep 24 12:38:04 PM UTC 24 1918432054 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1963682000 Sep 24 12:38:03 PM UTC 24 Sep 24 12:38:06 PM UTC 24 55792414 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1096019006 Sep 24 12:37:54 PM UTC 24 Sep 24 12:38:06 PM UTC 24 1810935287 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.4106336299 Sep 24 12:37:33 PM UTC 24 Sep 24 12:38:09 PM UTC 24 231064826 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.670660636 Sep 24 12:38:04 PM UTC 24 Sep 24 12:38:09 PM UTC 24 57009167 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2598297565 Sep 24 12:38:03 PM UTC 24 Sep 24 12:38:09 PM UTC 24 43623830 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2399715021 Sep 24 12:37:50 PM UTC 24 Sep 24 12:38:09 PM UTC 24 6047716197 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1156506531 Sep 24 12:37:34 PM UTC 24 Sep 24 12:38:11 PM UTC 24 219210595 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1243930878 Sep 24 12:37:49 PM UTC 24 Sep 24 12:38:11 PM UTC 24 776592773 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4000804262 Sep 24 12:38:10 PM UTC 24 Sep 24 12:38:12 PM UTC 24 24887769 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.4139269946 Sep 24 12:38:01 PM UTC 24 Sep 24 12:38:12 PM UTC 24 206187537 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3987072603 Sep 24 12:38:04 PM UTC 24 Sep 24 12:38:13 PM UTC 24 207523168 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.2199152621 Sep 24 12:37:49 PM UTC 24 Sep 24 12:38:13 PM UTC 24 270506921 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.610517650 Sep 24 12:37:26 PM UTC 24 Sep 24 12:38:14 PM UTC 24 6725434695 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.280003885 Sep 24 12:37:56 PM UTC 24 Sep 24 12:38:14 PM UTC 24 336152577 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.1734250633 Sep 24 12:37:59 PM UTC 24 Sep 24 12:38:19 PM UTC 24 1327038335 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.2606663530 Sep 24 12:38:06 PM UTC 24 Sep 24 12:38:19 PM UTC 24 237771243 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.118291977 Sep 24 12:38:12 PM UTC 24 Sep 24 12:38:21 PM UTC 24 498861490 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.3293117696 Sep 24 12:37:52 PM UTC 24 Sep 24 12:38:21 PM UTC 24 2700951316 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2673554739 Sep 24 12:37:56 PM UTC 24 Sep 24 12:38:22 PM UTC 24 2175748843 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.4087841927 Sep 24 12:38:08 PM UTC 24 Sep 24 12:38:22 PM UTC 24 425508567 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.4179043723 Sep 24 12:38:07 PM UTC 24 Sep 24 12:38:22 PM UTC 24 2439030336 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3031412311 Sep 24 12:37:06 PM UTC 24 Sep 24 12:38:23 PM UTC 24 15889115019 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2629547696 Sep 24 12:37:41 PM UTC 24 Sep 24 12:38:23 PM UTC 24 5686295902 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1155692743 Sep 24 12:38:10 PM UTC 24 Sep 24 12:38:24 PM UTC 24 308250329 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.4083884045 Sep 24 12:38:10 PM UTC 24 Sep 24 12:38:24 PM UTC 24 1282216004 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.2200394461 Sep 24 12:36:47 PM UTC 24 Sep 24 12:38:25 PM UTC 24 45717456727 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2993200756 Sep 24 12:37:45 PM UTC 24 Sep 24 12:38:25 PM UTC 24 1774601284 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3546374931 Sep 24 12:38:32 PM UTC 24 Sep 24 12:38:35 PM UTC 24 59609032 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3533338381 Sep 24 12:38:14 PM UTC 24 Sep 24 12:38:35 PM UTC 24 2644635449 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2797692757 Sep 24 12:38:15 PM UTC 24 Sep 24 12:38:26 PM UTC 24 623377148 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1213048066 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:27 PM UTC 24 20310687 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.517156360 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:27 PM UTC 24 100024135 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.3161196338 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:27 PM UTC 24 12361162 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.1703863371 Sep 24 12:38:14 PM UTC 24 Sep 24 12:38:28 PM UTC 24 3146756984 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2177124010 Sep 24 12:37:46 PM UTC 24 Sep 24 12:38:28 PM UTC 24 358587022 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.4068047298 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:28 PM UTC 24 305681565 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1699980837 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:29 PM UTC 24 48832224 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2140753153 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:32 PM UTC 24 223448455 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.532488295 Sep 24 12:38:26 PM UTC 24 Sep 24 12:38:32 PM UTC 24 667125697 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2608154259 Sep 24 12:38:14 PM UTC 24 Sep 24 12:38:33 PM UTC 24 1101686556 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.2871198134 Sep 24 12:38:26 PM UTC 24 Sep 24 12:38:33 PM UTC 24 357375737 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.952157132 Sep 24 12:38:28 PM UTC 24 Sep 24 12:38:34 PM UTC 24 639194379 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2160373036 Sep 24 12:37:09 PM UTC 24 Sep 24 12:38:34 PM UTC 24 2639934504 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1218965231 Sep 24 12:38:13 PM UTC 24 Sep 24 12:38:34 PM UTC 24 3106112406 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2368760444 Sep 24 12:38:15 PM UTC 24 Sep 24 12:38:34 PM UTC 24 1989726595 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1407081030 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:38 PM UTC 24 259763772 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3179202811 Sep 24 12:38:34 PM UTC 24 Sep 24 12:38:36 PM UTC 24 36814791 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.475531274 Sep 24 12:38:34 PM UTC 24 Sep 24 12:38:38 PM UTC 24 295047030 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1901377987 Sep 24 12:38:28 PM UTC 24 Sep 24 12:38:38 PM UTC 24 964383911 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.611876631 Sep 24 12:38:29 PM UTC 24 Sep 24 12:38:38 PM UTC 24 261986489 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1866008872 Sep 24 12:38:36 PM UTC 24 Sep 24 12:38:39 PM UTC 24 17793960 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1601415600 Sep 24 12:38:35 PM UTC 24 Sep 24 12:38:40 PM UTC 24 49695552 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2029664266 Sep 24 12:38:04 PM UTC 24 Sep 24 12:38:41 PM UTC 24 674943412 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.2273581384 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:42 PM UTC 24 392591093 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1181354982 Sep 24 12:38:29 PM UTC 24 Sep 24 12:38:43 PM UTC 24 867207532 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.758582174 Sep 24 12:37:41 PM UTC 24 Sep 24 12:38:43 PM UTC 24 28556521153 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.655443033 Sep 24 12:38:35 PM UTC 24 Sep 24 12:38:43 PM UTC 24 319631825 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2051664261 Sep 24 12:38:39 PM UTC 24 Sep 24 12:38:44 PM UTC 24 148345787 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2511475452 Sep 24 12:38:29 PM UTC 24 Sep 24 12:38:45 PM UTC 24 895281385 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1650730359 Sep 24 12:38:35 PM UTC 24 Sep 24 12:38:45 PM UTC 24 744217032 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3060803063 Sep 24 12:38:36 PM UTC 24 Sep 24 12:38:46 PM UTC 24 210765721 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3411246108 Sep 24 12:38:36 PM UTC 24 Sep 24 12:38:46 PM UTC 24 2262085925 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3465035332 Sep 24 12:37:25 PM UTC 24 Sep 24 12:38:46 PM UTC 24 2389209880 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3486798708 Sep 24 12:38:45 PM UTC 24 Sep 24 12:38:47 PM UTC 24 62283764 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3554416494 Sep 24 12:38:46 PM UTC 24 Sep 24 12:38:49 PM UTC 24 25743055 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1550909219 Sep 24 12:37:52 PM UTC 24 Sep 24 12:38:49 PM UTC 24 1606352666 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.913838227 Sep 24 12:38:40 PM UTC 24 Sep 24 12:38:50 PM UTC 24 968735615 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.615697878 Sep 24 12:38:26 PM UTC 24 Sep 24 12:38:50 PM UTC 24 7610751687 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.2300076090 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:51 PM UTC 24 12963868480 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.994391272 Sep 24 12:38:35 PM UTC 24 Sep 24 12:38:52 PM UTC 24 5604281840 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3640001679 Sep 24 12:38:50 PM UTC 24 Sep 24 12:38:52 PM UTC 24 10217565 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1676982567 Sep 24 12:38:45 PM UTC 24 Sep 24 12:38:52 PM UTC 24 568004647 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1180774643 Sep 24 12:38:48 PM UTC 24 Sep 24 12:38:53 PM UTC 24 64180532 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.1250976126 Sep 24 12:38:25 PM UTC 24 Sep 24 12:38:53 PM UTC 24 2792785155 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1132832502 Sep 24 12:38:42 PM UTC 24 Sep 24 12:38:53 PM UTC 24 311826633 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.1898830191 Sep 24 12:38:51 PM UTC 24 Sep 24 12:38:55 PM UTC 24 654459097 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.4127797499 Sep 24 12:37:54 PM UTC 24 Sep 24 12:38:55 PM UTC 24 3935932120 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.528059009 Sep 24 12:38:40 PM UTC 24 Sep 24 12:38:56 PM UTC 24 1592611226 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.2393827060 Sep 24 12:38:42 PM UTC 24 Sep 24 12:38:58 PM UTC 24 384364326 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2296090622 Sep 24 12:38:52 PM UTC 24 Sep 24 12:38:58 PM UTC 24 204066576 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1002633973 Sep 24 12:38:39 PM UTC 24 Sep 24 12:38:59 PM UTC 24 1904154586 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.643053827 Sep 24 12:38:48 PM UTC 24 Sep 24 12:39:00 PM UTC 24 344242387 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3164003429 Sep 24 12:38:41 PM UTC 24 Sep 24 12:39:00 PM UTC 24 1548739016 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3796888552 Sep 24 12:38:10 PM UTC 24 Sep 24 12:39:00 PM UTC 24 1653449299 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.1473855529 Sep 24 12:38:46 PM UTC 24 Sep 24 12:39:01 PM UTC 24 82207902 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1246113526 Sep 24 12:38:28 PM UTC 24 Sep 24 12:39:01 PM UTC 24 1042706590 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.1131469555 Sep 24 12:38:59 PM UTC 24 Sep 24 12:39:01 PM UTC 24 46201815 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.3567325278 Sep 24 12:38:52 PM UTC 24 Sep 24 12:39:01 PM UTC 24 2039112013 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1952698731 Sep 24 12:37:33 PM UTC 24 Sep 24 12:39:02 PM UTC 24 8699734590 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.816913833 Sep 24 12:38:44 PM UTC 24 Sep 24 12:39:02 PM UTC 24 1411917088 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.141115763 Sep 24 12:38:50 PM UTC 24 Sep 24 12:39:03 PM UTC 24 367341116 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1015074085 Sep 24 12:39:01 PM UTC 24 Sep 24 12:39:03 PM UTC 24 34968441 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.2680288291 Sep 24 12:38:54 PM UTC 24 Sep 24 12:39:05 PM UTC 24 1611850845 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.499153513 Sep 24 12:38:48 PM UTC 24 Sep 24 12:39:06 PM UTC 24 9604624839 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1359674164 Sep 24 12:39:03 PM UTC 24 Sep 24 12:39:07 PM UTC 24 94406047 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.4081498371 Sep 24 12:39:01 PM UTC 24 Sep 24 12:39:08 PM UTC 24 102131932 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3396864069 Sep 24 12:37:06 PM UTC 24 Sep 24 12:39:08 PM UTC 24 3452506509 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3304316098 Sep 24 12:38:34 PM UTC 24 Sep 24 12:39:09 PM UTC 24 180226388 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1558548451 Sep 24 12:39:00 PM UTC 24 Sep 24 12:39:09 PM UTC 24 172778385 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.4025582586 Sep 24 12:38:12 PM UTC 24 Sep 24 12:39:09 PM UTC 24 7593404680 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.11546414 Sep 24 12:38:54 PM UTC 24 Sep 24 12:39:09 PM UTC 24 19987653864 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1211564487 Sep 24 12:38:55 PM UTC 24 Sep 24 12:39:09 PM UTC 24 494327913 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3868527448 Sep 24 12:38:56 PM UTC 24 Sep 24 12:39:09 PM UTC 24 736499233 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.27563871 Sep 24 12:37:46 PM UTC 24 Sep 24 12:39:12 PM UTC 24 9235084853 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.1004700191 Sep 24 12:39:04 PM UTC 24 Sep 24 12:39:12 PM UTC 24 248958611 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2865258654 Sep 24 12:39:11 PM UTC 24 Sep 24 12:39:13 PM UTC 24 54043819 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3702559782 Sep 24 12:39:11 PM UTC 24 Sep 24 12:39:13 PM UTC 24 49799128 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.1110677899 Sep 24 12:38:01 PM UTC 24 Sep 24 12:39:14 PM UTC 24 1665098340 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3772363419 Sep 24 12:39:11 PM UTC 24 Sep 24 12:39:14 PM UTC 24 28862807 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.10336308 Sep 24 12:39:06 PM UTC 24 Sep 24 12:39:16 PM UTC 24 9489397418 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.4259765685 Sep 24 12:39:03 PM UTC 24 Sep 24 12:39:16 PM UTC 24 722971807 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.3674611767 Sep 24 12:39:13 PM UTC 24 Sep 24 12:39:17 PM UTC 24 123794971 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2007921086 Sep 24 12:39:03 PM UTC 24 Sep 24 12:39:17 PM UTC 24 2024277851 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.3485647493 Sep 24 12:39:03 PM UTC 24 Sep 24 12:39:18 PM UTC 24 6255994075 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1163288006 Sep 24 12:38:56 PM UTC 24 Sep 24 12:39:18 PM UTC 24 1176404290 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.4112132987 Sep 24 12:39:09 PM UTC 24 Sep 24 12:39:19 PM UTC 24 220764373 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.4162611325 Sep 24 12:39:04 PM UTC 24 Sep 24 12:39:22 PM UTC 24 257885360 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.1733076524 Sep 24 12:39:11 PM UTC 24 Sep 24 12:39:23 PM UTC 24 270106359 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.154747390 Sep 24 12:39:18 PM UTC 24 Sep 24 12:39:25 PM UTC 24 890835671 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.1542710662 Sep 24 12:38:46 PM UTC 24 Sep 24 12:39:25 PM UTC 24 1355836925 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.3687783998 Sep 24 12:39:24 PM UTC 24 Sep 24 12:39:27 PM UTC 24 24674746 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.4232958461 Sep 24 12:39:10 PM UTC 24 Sep 24 12:39:27 PM UTC 24 1397450242 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.2512160915 Sep 24 12:38:37 PM UTC 24 Sep 24 12:39:27 PM UTC 24 1110852675 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.2762468954 Sep 24 12:39:15 PM UTC 24 Sep 24 12:39:28 PM UTC 24 1852395191 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1743257451 Sep 24 12:39:26 PM UTC 24 Sep 24 12:39:28 PM UTC 24 44879429 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2160143385 Sep 24 12:39:26 PM UTC 24 Sep 24 12:39:29 PM UTC 24 39144479 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1780854185 Sep 24 12:38:54 PM UTC 24 Sep 24 12:39:29 PM UTC 24 9797742769 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3502427082 Sep 24 12:39:15 PM UTC 24 Sep 24 12:39:30 PM UTC 24 330787599 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.886709147 Sep 24 12:39:13 PM UTC 24 Sep 24 12:39:31 PM UTC 24 1774386743 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3478045575 Sep 24 12:39:09 PM UTC 24 Sep 24 12:39:31 PM UTC 24 1615831448 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.821049109 Sep 24 12:39:18 PM UTC 24 Sep 24 12:39:31 PM UTC 24 1139565419 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.2224741847 Sep 24 12:38:54 PM UTC 24 Sep 24 12:39:33 PM UTC 24 1949929014 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.238765578 Sep 24 12:37:46 PM UTC 24 Sep 24 12:39:34 PM UTC 24 2301554330 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.4259088320 Sep 24 12:39:28 PM UTC 24 Sep 24 12:39:34 PM UTC 24 46891504 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.3868632817 Sep 24 12:39:20 PM UTC 24 Sep 24 12:39:34 PM UTC 24 256535007 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.1266268803 Sep 24 12:38:28 PM UTC 24 Sep 24 12:39:34 PM UTC 24 2366130786 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.3580844964 Sep 24 12:39:20 PM UTC 24 Sep 24 12:39:35 PM UTC 24 214035191 ps
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