Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57917662

1

T1

1769

T2

1410

T3

11633

auto[1]

1174181

1

T3

1089

T4

297

T12

9552

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57931182

1

T1

1769

T2

1410

T3

11930

auto[1]

1160661

1

T3

792

T12

7888

T14

1980

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5405214	1			T1	99		T2	176		T3	2081
auto[IdleSt]	15938845	1			T1	40		T2	55		T3	1044
auto[ClkMuxSt]	29343	1			T1	1		T2	1		T3	19
auto[CntIncrSt]	29167	1			T1	1		T2	1		T3	19
auto[CntProgSt]	1176943	1			T1	388		T2	2		T3	5859
auto[TransCheckSt]	22983	1			T1	1		T2	1		T4	5
auto[TokenHashSt]	15589399	1			T1	18		T2	572		T4	330
auto[FlashRmaSt]	29836	1			T2	1		T4	34		T12	77
auto[TokenCheck0St]	10395	1			T2	1		T4	5		T12	26
auto[TokenCheck1St]	7481	1			T2	1		T4	5		T12	25
auto[TransProgSt]	316259	1			T2	2		T4	1249		T12	194
auto[PostTransSt]	8620907	1			T1	1221		T2	3		T3	1181
auto[ScrapSt]	69632	1			T2	594		T12	4		T5	3114
auto[EscalateSt]	4669727	1			T3	2519		T4	534		T12	13134
auto[InvalidSt]	7174357	1			T4	220		T14	3201		T11	9842

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1355	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7174357	1			T4	220		T14	3201		T11	9842
EscalateSt	4669727	1			T3	2519		T4	534		T12	13134
ScrapSt	69632	1			T2	594		T12	4		T5	3114
PostTransSt	8620907	1			T1	1221		T2	3		T3	1181
TransProgSt	316259	1			T2	2		T4	1249		T12	194
TokenCheck1St	7481	1			T2	1		T4	5		T12	25
TokenCheck0St	10395	1			T2	1		T4	5		T12	26
FlashRmaSt	29836	1			T2	1		T4	34		T12	77
TokenHashSt	15589399	1			T1	18		T2	572		T4	330
TransCheckSt	22983	1			T1	1		T2	1		T4	5
CntProgSt	1176943	1			T1	388		T2	2		T3	5859
CntIncrSt	29167	1			T1	1		T2	1		T3	19
ClkMuxSt	29343	1			T1	1		T2	1		T3	19
IdleSt	15938845	1			T1	40		T2	55		T3	1044
ResetSt	5405214	1			T1	99		T2	176		T3	2081
arcs[ResetSt=>IdleSt]	43043	1			T1	1		T2	2		T3	20
arcs[IdleSt=>ScrapSt]	222	1			T2	1		T12	1		T5	1
arcs[IdleSt=>ClkMuxSt]	29201	1			T1	1		T2	1		T3	19
arcs[ClkMuxSt=>CntIncrSt]	29167	1			T1	1		T2	1		T3	19
arcs[CntIncrSt=>PostTransSt]	1228	1			T15	11		T18	9		T24	8
arcs[CntIncrSt=>CntProgSt]	27874	1			T1	1		T2	1		T3	19
arcs[CntProgSt=>PostTransSt]	3796	1			T3	19		T15	14		T6	7
arcs[CntProgSt=>TransCheckSt]	22983	1			T1	1		T2	1		T4	5
arcs[TransCheckSt=>PostTransSt]	3163	1			T15	19		T23	46		T18	8
arcs[TransCheckSt=>TokenHashSt]	19697	1			T1	1		T2	1		T4	5
arcs[TokenHashSt=>PostTransSt]	8476	1			T1	1		T15	17		T19	9
arcs[TokenHashSt=>FlashRmaSt]	10435	1			T2	1		T4	5		T12	28
arcs[FlashRmaSt=>TokenCheck0St]	10395	1			T2	1		T4	5		T12	26
arcs[TokenCheck0St=>PostTransSt]	2848	1			T15	4		T19	12		T23	22
arcs[TokenCheck0St=>TokenCheck1St]	7481	1			T2	1		T4	5		T12	25
arcs[TokenCheck1St=>PostTransSt]	629	1			T19	1		T23	13		T39	14
arcs[TransProgSt=>PostTransSt]	6008	1			T2	1		T4	5		T12	1
arcs[IdleSt=>EscalateSt]	198	1			T55	5		T60	5		T61	5
arcs[ClkMuxSt=>EscalateSt]	34	1			T55	1		T56	1		T57	5
arcs[CntIncrSt=>EscalateSt]	65	1			T55	1		T58	2		T59	1
arcs[CntProgSt=>EscalateSt]	1095	1			T12	38		T55	5		T58	22
arcs[TransCheckSt=>EscalateSt]	123	1			T55	7		T58	1		T60	4
arcs[TokenHashSt=>EscalateSt]	785	1			T12	8		T55	22		T58	7
arcs[FlashRmaSt=>EscalateSt]	40	1			T12	2		T55	1		T58	2
arcs[TokenCheck0St=>EscalateSt]	66	1			T12	1		T55	1		T58	1
arcs[TokenCheck1St=>EscalateSt]	30	1			T12	1		T55	1		T60	1
arcs[TransProgSt=>EscalateSt]	814	1			T12	23		T55	8		T58	15
arcs[PostTransSt=>EscalateSt]	4166	1			T3	19		T12	1		T15	14
arcs[InvalidSt=>EscalateSt]	10101	1			T4	3		T14	43		T11	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5405036	1			T1	99		T2	176		T3	2081
auto[0]	auto[IdleSt]	15938717	1			T1	40		T2	55		T3	1044
auto[0]	auto[ClkMuxSt]	29319	1			T1	1		T2	1		T3	19
auto[0]	auto[CntIncrSt]	29127	1			T1	1		T2	1		T3	19
auto[0]	auto[CntProgSt]	1176250	1			T1	388		T2	2		T3	5859
auto[0]	auto[TransCheckSt]	22896	1			T1	1		T2	1		T4	5
auto[0]	auto[TokenHashSt]	15588861	1			T1	18		T2	572		T4	330
auto[0]	auto[FlashRmaSt]	29814	1			T2	1		T4	34		T12	76
auto[0]	auto[TokenCheck0St]	10351	1			T2	1		T4	5		T12	25
auto[0]	auto[TokenCheck1St]	7463	1			T2	1		T4	5		T12	24
auto[0]	auto[TransProgSt]	315719	1			T2	2		T4	1249		T12	176
auto[0]	auto[PostTransSt]	8618733	1			T1	1221		T2	3		T3	1170
auto[0]	auto[ScrapSt]	69600	1			T2	594		T12	4		T5	3114
auto[0]	auto[EscalateSt]	3505135	1			T3	1441		T4	240		T12	3640
auto[0]	auto[InvalidSt]	7169286	1			T4	217		T14	3178		T11	9840
auto[1]	auto[ResetSt]	178	1			T12	5		T55	3		T58	1
auto[1]	auto[IdleSt]	128	1			T55	4		T60	3		T61	4
auto[1]	auto[ClkMuxSt]	24	1			T55	1		T56	1		T57	2
auto[1]	auto[CntIncrSt]	40	1			T55	1		T61	1		T242	3
auto[1]	auto[CntProgSt]	693	1			T12	27		T55	4		T58	12
auto[1]	auto[TransCheckSt]	87	1			T55	5		T60	4		T61	6
auto[1]	auto[TokenHashSt]	538	1			T12	5		T55	12		T58	4
auto[1]	auto[FlashRmaSt]	22	1			T12	1		T59	1		T243	1
auto[1]	auto[TokenCheck0St]	44	1			T12	1		T55	1		T58	1
auto[1]	auto[TokenCheck1St]	18	1			T12	1		T61	1		T243	1
auto[1]	auto[TransProgSt]	540	1			T12	18		T55	5		T58	12
auto[1]	auto[PostTransSt]	2174	1			T3	11		T15	4		T6	3
auto[1]	auto[ScrapSt]	32	1			T58	2		T59	1		T61	1
auto[1]	auto[EscalateSt]	1164592	1			T3	1078		T4	294		T12	9494
auto[1]	auto[InvalidSt]	5071	1			T4	3		T14	23		T11	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5405038	1			T1	99		T2	176		T3	2081
auto[0]	auto[IdleSt]	15938715	1			T1	40		T2	55		T3	1044
auto[0]	auto[ClkMuxSt]	29321	1			T1	1		T2	1		T3	19
auto[0]	auto[CntIncrSt]	29122	1			T1	1		T2	1		T3	19
auto[0]	auto[CntProgSt]	1176215	1			T1	388		T2	2		T3	5859
auto[0]	auto[TransCheckSt]	22901	1			T1	1		T2	1		T4	5
auto[0]	auto[TokenHashSt]	15588901	1			T1	18		T2	572		T4	330
auto[0]	auto[FlashRmaSt]	29807	1			T2	1		T4	34		T12	75
auto[0]	auto[TokenCheck0St]	10353	1			T2	1		T4	5		T12	26
auto[0]	auto[TokenCheck1St]	7463	1			T2	1		T4	5		T12	25
auto[0]	auto[TransProgSt]	315753	1			T2	2		T4	1249		T12	182
auto[0]	auto[PostTransSt]	8618789	1			T1	1221		T2	3		T3	1173
auto[0]	auto[ScrapSt]	69595	1			T2	594		T12	3		T5	3114
auto[0]	auto[EscalateSt]	3518527	1			T3	1735		T4	534		T12	5294
auto[0]	auto[InvalidSt]	7169327	1			T4	220		T14	3181		T11	9840
auto[1]	auto[ResetSt]	176	1			T12	3		T55	4		T58	1
auto[1]	auto[IdleSt]	130	1			T55	2		T60	3		T61	3
auto[1]	auto[ClkMuxSt]	22	1			T56	1		T57	4		T244	1
auto[1]	auto[CntIncrSt]	45	1			T58	2		T59	1		T60	1
auto[1]	auto[CntProgSt]	728	1			T12	22		T55	5		T58	14
auto[1]	auto[TransCheckSt]	82	1			T55	6		T58	1		T60	2
auto[1]	auto[TokenHashSt]	498	1			T12	7		T55	15		T58	3
auto[1]	auto[FlashRmaSt]	29	1			T12	2		T55	1		T58	2
auto[1]	auto[TokenCheck0St]	42	1			T55	1		T61	1		T243	1
auto[1]	auto[TokenCheck1St]	18	1			T55	1		T60	1		T61	1
auto[1]	auto[TransProgSt]	506	1			T12	12		T55	5		T58	10
auto[1]	auto[PostTransSt]	2118	1			T3	8		T12	1		T15	10
auto[1]	auto[ScrapSt]	37	1			T12	1		T55	1		T58	2
auto[1]	auto[EscalateSt]	1151200	1			T3	784		T12	7840		T14	1960
auto[1]	auto[InvalidSt]	5030	1			T14	20		T11	2		T19	14