Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.98 97.90 96.12 93.40 97.62 98.49 99.00 96.29


Total tests in report: 1011
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.79 67.79 81.54 81.54 45.56 45.56 55.63 55.63 61.90 61.90 83.01 83.01 92.29 92.29 54.59 54.59 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1398342887
78.71 10.92 88.70 7.16 74.12 28.56 69.65 14.02 73.81 11.90 89.25 6.24 93.78 1.49 61.66 7.07 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2931041423
82.81 4.10 95.35 6.65 75.79 1.66 72.60 2.96 80.95 7.14 91.83 2.58 94.28 0.50 68.90 7.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.128516688
85.42 2.60 95.40 0.05 81.15 5.36 80.62 8.02 80.95 0.00 92.90 1.08 94.28 0.00 72.61 3.71 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.897058837
87.37 1.95 95.50 0.10 81.61 0.46 81.31 0.69 90.48 9.52 93.33 0.43 94.28 0.00 75.09 2.47 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2346177186
88.84 1.47 96.52 1.02 85.30 3.70 81.61 0.30 90.48 0.00 94.62 1.29 95.27 1.00 78.09 3.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3515743929
90.02 1.17 96.73 0.20 85.40 0.09 85.16 3.55 90.48 0.00 95.27 0.65 95.27 0.00 81.80 3.71 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.2588135626
91.08 1.07 96.83 0.10 87.06 1.66 85.20 0.04 90.48 0.00 95.70 0.43 96.27 1.00 86.04 4.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3896297706
91.89 0.81 96.93 0.10 87.80 0.74 85.73 0.53 92.86 2.38 96.13 0.43 96.52 0.25 87.28 1.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1993901717
92.64 0.75 97.03 0.10 88.91 1.11 85.77 0.04 95.24 2.38 96.34 0.22 97.01 0.50 88.16 0.88 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1343392554
93.31 0.67 97.14 0.10 89.09 0.18 87.95 2.18 95.24 0.00 96.99 0.65 97.01 0.00 89.75 1.59 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2636016981
93.78 0.47 97.29 0.15 90.57 1.48 87.95 0.00 95.24 0.00 97.42 0.43 97.01 0.00 90.99 1.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1168783191
94.25 0.47 97.29 0.00 90.57 0.00 87.95 0.00 97.62 2.38 97.42 0.00 97.01 0.00 91.87 0.88 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3967850697
94.70 0.45 97.29 0.00 90.67 0.09 90.28 2.34 97.62 0.00 97.42 0.00 97.01 0.00 92.58 0.71 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3400652570
94.97 0.28 97.65 0.36 91.59 0.92 90.95 0.67 97.62 0.00 97.42 0.00 97.01 0.00 92.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.3865541534
95.19 0.21 97.65 0.00 91.59 0.00 90.95 0.00 97.62 0.00 97.42 0.00 98.51 1.49 92.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.291535082
95.39 0.20 97.80 0.15 91.59 0.00 91.45 0.50 97.62 0.00 97.63 0.22 98.51 0.00 93.11 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2292504328
95.58 0.20 97.80 0.00 92.79 1.20 91.45 0.00 97.62 0.00 97.63 0.00 98.51 0.00 93.29 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2345309948
95.77 0.19 97.90 0.10 92.88 0.09 91.95 0.51 97.62 0.00 98.06 0.43 98.51 0.00 93.46 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.1639008098
95.91 0.14 97.90 0.00 93.53 0.65 91.95 0.00 97.62 0.00 98.06 0.00 98.51 0.00 93.82 0.35 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4148889239
96.04 0.13 97.90 0.00 93.53 0.00 92.84 0.89 97.62 0.00 98.06 0.00 98.51 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2254128
96.16 0.12 97.90 0.00 93.53 0.00 92.84 0.00 97.62 0.00 98.28 0.22 98.76 0.25 94.17 0.35 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.182336009
96.23 0.08 97.90 0.00 93.53 0.00 93.20 0.35 97.62 0.00 98.28 0.00 98.76 0.00 94.35 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.43710362
96.31 0.08 97.90 0.00 93.53 0.00 93.20 0.00 97.62 0.00 98.28 0.00 98.76 0.00 94.88 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1364456598
96.37 0.06 97.90 0.00 93.81 0.28 93.20 0.00 97.62 0.00 98.28 0.00 98.76 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.1079721052
96.43 0.05 97.90 0.00 94.18 0.37 93.20 0.00 97.62 0.00 98.28 0.00 98.76 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1200475880
96.47 0.04 97.90 0.00 94.27 0.09 93.20 0.00 97.62 0.00 98.49 0.22 98.76 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.838181034
96.51 0.04 97.90 0.00 94.36 0.09 93.23 0.03 97.62 0.00 98.49 0.00 98.76 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.3599583471
96.55 0.04 97.90 0.00 94.64 0.28 93.23 0.00 97.62 0.00 98.49 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1580399727
96.59 0.04 97.90 0.00 94.92 0.28 93.23 0.00 97.62 0.00 98.49 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3748244120
96.63 0.04 97.90 0.00 94.92 0.00 93.23 0.00 97.62 0.00 98.49 0.00 99.00 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2412671920
96.66 0.03 97.90 0.00 94.92 0.00 93.28 0.05 97.62 0.00 98.49 0.00 99.00 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3986624248
96.69 0.03 97.90 0.00 95.10 0.18 93.30 0.02 97.62 0.00 98.49 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3146854457
96.72 0.03 97.90 0.00 95.10 0.00 93.32 0.02 97.62 0.00 98.49 0.00 99.00 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2874727022
96.74 0.03 97.90 0.00 95.10 0.00 93.33 0.01 97.62 0.00 98.49 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3126926336
96.77 0.03 97.90 0.00 95.29 0.18 93.33 0.00 97.62 0.00 98.49 0.00 99.00 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4028265093
96.80 0.03 97.90 0.00 95.47 0.18 93.33 0.00 97.62 0.00 98.49 0.00 99.00 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1356688470
96.82 0.03 97.90 0.00 95.47 0.00 93.33 0.00 97.62 0.00 98.49 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.187770605
96.85 0.03 97.90 0.00 95.47 0.00 93.33 0.00 97.62 0.00 98.49 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.744929102
96.87 0.03 97.90 0.00 95.47 0.00 93.33 0.00 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4051547285
96.89 0.02 97.90 0.00 95.56 0.09 93.37 0.04 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.1810736494
96.91 0.01 97.90 0.00 95.66 0.09 93.37 0.00 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1397093991
96.92 0.01 97.90 0.00 95.75 0.09 93.37 0.00 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2459043564
96.93 0.01 97.90 0.00 95.84 0.09 93.37 0.00 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4224228920
96.95 0.01 97.90 0.00 95.93 0.09 93.37 0.00 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3164620719
96.96 0.01 97.90 0.00 96.03 0.09 93.37 0.00 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2856605054
96.97 0.01 97.90 0.00 96.12 0.09 93.37 0.00 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.302426423
96.97 0.01 97.90 0.00 96.12 0.00 93.39 0.02 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3416180814
96.98 0.01 97.90 0.00 96.12 0.00 93.40 0.01 97.62 0.00 98.49 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3912227942

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1528364772
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.865265843
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1388611810
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2433437540
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.527113250
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1965728115
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.985276765
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3802904251
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4022149676
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3537952359
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2324551812
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3904316600
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2833037973
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2513950406
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.143559285
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1304520053
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4113023195
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3902439645
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1511812398
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3195548673
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.964273961
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.11805597
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.55267115
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1716539822
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1437623704
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3139365319
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.503467474
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1731412302
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2971204721
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1512690298
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.646081989
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2241677843
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.585457651
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3425871196
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1955315235
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1726528025
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3798830697
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3973685264
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2453780241
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Total test records in report: 1011
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2874727022 Oct 03 10:16:12 AM UTC 24 Oct 03 10:16:15 AM UTC 24 17710686 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1063006909 Oct 03 10:16:12 AM UTC 24 Oct 03 10:16:15 AM UTC 24 61332767 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3561056346 Oct 03 10:16:16 AM UTC 24 Oct 03 10:16:24 AM UTC 24 508889684 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.43710362 Oct 03 10:16:16 AM UTC 24 Oct 03 10:16:28 AM UTC 24 448632238 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1398342887 Oct 03 10:16:24 AM UTC 24 Oct 03 10:16:38 AM UTC 24 1482528568 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3986624248 Oct 03 10:16:39 AM UTC 24 Oct 03 10:16:41 AM UTC 24 12836869 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4052349803 Oct 03 10:16:16 AM UTC 24 Oct 03 10:16:43 AM UTC 24 155712934 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3416180814 Oct 03 10:16:24 AM UTC 24 Oct 03 10:16:44 AM UTC 24 323709985 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.2756651160 Oct 03 10:16:41 AM UTC 24 Oct 03 10:16:49 AM UTC 24 853401550 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3217906371 Oct 03 10:16:28 AM UTC 24 Oct 03 10:16:49 AM UTC 24 472070249 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.936228717 Oct 03 10:16:43 AM UTC 24 Oct 03 10:16:50 AM UTC 24 154381468 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3515743929 Oct 03 10:16:49 AM UTC 24 Oct 03 10:17:07 AM UTC 24 8049812956 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3912227942 Oct 03 10:16:42 AM UTC 24 Oct 03 10:17:10 AM UTC 24 2643754575 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.128516688 Oct 03 10:16:59 AM UTC 24 Oct 03 10:17:17 AM UTC 24 361633838 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.1545682550 Oct 03 10:16:50 AM UTC 24 Oct 03 10:17:20 AM UTC 24 2756409242 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.3865541534 Oct 03 10:17:20 AM UTC 24 Oct 03 10:17:23 AM UTC 24 71967969 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.559444914 Oct 03 10:17:08 AM UTC 24 Oct 03 10:17:27 AM UTC 24 1510898399 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3039252781 Oct 03 10:17:23 AM UTC 24 Oct 03 10:17:28 AM UTC 24 48532475 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.4145441149 Oct 03 10:17:11 AM UTC 24 Oct 03 10:17:29 AM UTC 24 316448587 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2231302586 Oct 03 10:17:28 AM UTC 24 Oct 03 10:17:30 AM UTC 24 51184548 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2292504328 Oct 03 10:16:52 AM UTC 24 Oct 03 10:17:30 AM UTC 24 3227151475 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3042785732 Oct 03 10:17:30 AM UTC 24 Oct 03 10:17:33 AM UTC 24 49898611 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3716066691 Oct 03 10:17:34 AM UTC 24 Oct 03 10:17:37 AM UTC 24 38870994 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.49483068 Oct 03 10:17:30 AM UTC 24 Oct 03 10:17:43 AM UTC 24 341968324 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2346177186 Oct 03 10:17:31 AM UTC 24 Oct 03 10:17:45 AM UTC 24 330348350 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3783169003 Oct 03 10:17:20 AM UTC 24 Oct 03 10:17:52 AM UTC 24 713679066 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.3599583471 Oct 03 10:17:31 AM UTC 24 Oct 03 10:17:53 AM UTC 24 781600427 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.231151804 Oct 03 10:17:37 AM UTC 24 Oct 03 10:17:56 AM UTC 24 1742079741 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2931041423 Oct 03 10:16:45 AM UTC 24 Oct 03 10:18:01 AM UTC 24 47417348529 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3126926336 Oct 03 10:17:46 AM UTC 24 Oct 03 10:18:03 AM UTC 24 324847974 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.897058837 Oct 03 10:17:29 AM UTC 24 Oct 03 10:18:03 AM UTC 24 507101964 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2903411516 Oct 03 10:17:32 AM UTC 24 Oct 03 10:18:04 AM UTC 24 1556858495 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.923629063 Oct 03 10:17:53 AM UTC 24 Oct 03 10:18:04 AM UTC 24 2481277927 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1242967712 Oct 03 10:17:57 AM UTC 24 Oct 03 10:18:12 AM UTC 24 409594381 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.117106312 Oct 03 10:18:06 AM UTC 24 Oct 03 10:18:18 AM UTC 24 211039693 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.630905364 Oct 03 10:18:02 AM UTC 24 Oct 03 10:18:18 AM UTC 24 404347707 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.2373909663 Oct 03 10:18:19 AM UTC 24 Oct 03 10:18:21 AM UTC 24 14869305 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2636016981 Oct 03 10:18:04 AM UTC 24 Oct 03 10:18:22 AM UTC 24 1891960544 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1240311772 Oct 03 10:18:19 AM UTC 24 Oct 03 10:18:23 AM UTC 24 20207824 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3673977356 Oct 03 10:18:21 AM UTC 24 Oct 03 10:18:24 AM UTC 24 27199029 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.173897737 Oct 03 10:18:04 AM UTC 24 Oct 03 10:18:28 AM UTC 24 485000660 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.970405978 Oct 03 10:18:24 AM UTC 24 Oct 03 10:18:29 AM UTC 24 133079427 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.472429846 Oct 03 10:17:54 AM UTC 24 Oct 03 10:18:30 AM UTC 24 4295780703 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3975786846 Oct 03 10:16:42 AM UTC 24 Oct 03 10:18:31 AM UTC 24 2316113851 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.391307386 Oct 03 10:18:31 AM UTC 24 Oct 03 10:18:33 AM UTC 24 21610079 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3509732520 Oct 03 10:18:22 AM UTC 24 Oct 03 10:18:34 AM UTC 24 947734694 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3400971231 Oct 03 10:18:31 AM UTC 24 Oct 03 10:18:38 AM UTC 24 504254313 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2519812660 Oct 03 10:18:29 AM UTC 24 Oct 03 10:18:39 AM UTC 24 651953359 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.1810736494 Oct 03 10:18:30 AM UTC 24 Oct 03 10:18:41 AM UTC 24 668303954 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1993901717 Oct 03 10:18:13 AM UTC 24 Oct 03 10:18:43 AM UTC 24 619429649 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1022993378 Oct 03 10:18:25 AM UTC 24 Oct 03 10:18:44 AM UTC 24 1843714728 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.974564680 Oct 03 10:18:22 AM UTC 24 Oct 03 10:18:44 AM UTC 24 205141484 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.789762898 Oct 03 10:18:40 AM UTC 24 Oct 03 10:18:45 AM UTC 24 328036263 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1690078308 Oct 03 10:18:42 AM UTC 24 Oct 03 10:18:45 AM UTC 24 441954255 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2066247460 Oct 03 10:17:44 AM UTC 24 Oct 03 10:18:48 AM UTC 24 4811550758 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.2311858210 Oct 03 10:18:49 AM UTC 24 Oct 03 10:18:52 AM UTC 24 32634490 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2984678310 Oct 03 10:18:52 AM UTC 24 Oct 03 10:18:54 AM UTC 24 67403963 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.2847849767 Oct 03 10:18:34 AM UTC 24 Oct 03 10:18:56 AM UTC 24 280517773 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.386407689 Oct 03 10:18:49 AM UTC 24 Oct 03 10:18:56 AM UTC 24 780801182 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1381984501 Oct 03 10:18:04 AM UTC 24 Oct 03 10:18:57 AM UTC 24 1330302092 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3248237348 Oct 03 10:18:45 AM UTC 24 Oct 03 10:18:58 AM UTC 24 1110653637 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.4035429668 Oct 03 10:18:56 AM UTC 24 Oct 03 10:18:59 AM UTC 24 46030331 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.1803117670 Oct 03 10:18:37 AM UTC 24 Oct 03 10:19:00 AM UTC 24 3065692366 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3059947219 Oct 03 10:18:44 AM UTC 24 Oct 03 10:19:00 AM UTC 24 1393093104 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2063307141 Oct 03 10:18:45 AM UTC 24 Oct 03 10:19:01 AM UTC 24 244839546 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.187770605 Oct 03 10:19:01 AM UTC 24 Oct 03 10:19:03 AM UTC 24 49328076 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1419396775 Oct 03 10:18:55 AM UTC 24 Oct 03 10:19:05 AM UTC 24 309284431 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1948563715 Oct 03 10:18:47 AM UTC 24 Oct 03 10:19:10 AM UTC 24 599306437 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2357154843 Oct 03 10:19:07 AM UTC 24 Oct 03 10:19:11 AM UTC 24 125969149 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1670194659 Oct 03 10:18:56 AM UTC 24 Oct 03 10:19:11 AM UTC 24 2630801631 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2572638342 Oct 03 10:18:59 AM UTC 24 Oct 03 10:19:11 AM UTC 24 290877082 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3065669679 Oct 03 10:18:57 AM UTC 24 Oct 03 10:19:14 AM UTC 24 1686811401 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.2588135626 Oct 03 10:17:15 AM UTC 24 Oct 03 10:19:15 AM UTC 24 21641680025 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.2687345967 Oct 03 10:19:02 AM UTC 24 Oct 03 10:19:16 AM UTC 24 596769517 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3412256800 Oct 03 10:19:04 AM UTC 24 Oct 03 10:19:24 AM UTC 24 414402328 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2643990624 Oct 03 10:19:07 AM UTC 24 Oct 03 10:19:18 AM UTC 24 279467918 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.1383686566 Oct 03 10:19:01 AM UTC 24 Oct 03 10:19:18 AM UTC 24 368425064 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2449365078 Oct 03 10:19:19 AM UTC 24 Oct 03 10:19:21 AM UTC 24 27582929 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2026858195 Oct 03 10:18:52 AM UTC 24 Oct 03 10:19:22 AM UTC 24 365245670 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3201597336 Oct 03 10:19:20 AM UTC 24 Oct 03 10:19:25 AM UTC 24 417881103 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1730071819 Oct 03 10:19:22 AM UTC 24 Oct 03 10:19:24 AM UTC 24 138594810 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4253572080 Oct 03 10:18:43 AM UTC 24 Oct 03 10:19:25 AM UTC 24 3252152787 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.766391137 Oct 03 10:19:12 AM UTC 24 Oct 03 10:19:26 AM UTC 24 1144775989 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1674177186 Oct 03 10:19:13 AM UTC 24 Oct 03 10:19:28 AM UTC 24 1458487454 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.2008140880 Oct 03 10:19:25 AM UTC 24 Oct 03 10:19:30 AM UTC 24 184099011 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1733402766 Oct 03 10:19:25 AM UTC 24 Oct 03 10:19:30 AM UTC 24 50886420 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.4198408667 Oct 03 10:19:29 AM UTC 24 Oct 03 10:19:32 AM UTC 24 37389970 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2114944482 Oct 03 10:19:29 AM UTC 24 Oct 03 10:19:33 AM UTC 24 251762146 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.725907721 Oct 03 10:19:12 AM UTC 24 Oct 03 10:19:37 AM UTC 24 10425715991 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.279659438 Oct 03 10:19:12 AM UTC 24 Oct 03 10:19:37 AM UTC 24 405069127 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.3210519188 Oct 03 10:19:26 AM UTC 24 Oct 03 10:19:40 AM UTC 24 272707823 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.1678372993 Oct 03 10:19:06 AM UTC 24 Oct 03 10:19:41 AM UTC 24 7197630952 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2797935796 Oct 03 10:19:37 AM UTC 24 Oct 03 10:19:41 AM UTC 24 504585771 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.4154182999 Oct 03 10:19:26 AM UTC 24 Oct 03 10:19:43 AM UTC 24 582927511 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.952079058 Oct 03 10:19:26 AM UTC 24 Oct 03 10:19:43 AM UTC 24 635690509 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2511389224 Oct 03 10:18:34 AM UTC 24 Oct 03 10:19:45 AM UTC 24 2632383698 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3093728706 Oct 03 10:19:33 AM UTC 24 Oct 03 10:19:46 AM UTC 24 938796163 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2934025813 Oct 03 10:19:16 AM UTC 24 Oct 03 10:19:48 AM UTC 24 481666714 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2785262744 Oct 03 10:19:47 AM UTC 24 Oct 03 10:19:50 AM UTC 24 36063487 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.552052980 Oct 03 10:19:50 AM UTC 24 Oct 03 10:19:52 AM UTC 24 22841916 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2455724257 Oct 03 10:18:39 AM UTC 24 Oct 03 10:19:53 AM UTC 24 9846940188 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2816210171 Oct 03 10:19:51 AM UTC 24 Oct 03 10:19:53 AM UTC 24 13805629 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1641505619 Oct 03 10:19:24 AM UTC 24 Oct 03 10:19:57 AM UTC 24 2201832596 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3866914437 Oct 03 10:19:31 AM UTC 24 Oct 03 10:19:57 AM UTC 24 1185224323 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.1270579310 Oct 03 10:19:54 AM UTC 24 Oct 03 10:19:57 AM UTC 24 58674235 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2160480812 Oct 03 10:19:42 AM UTC 24 Oct 03 10:19:59 AM UTC 24 1751545545 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1825100458 Oct 03 10:18:45 AM UTC 24 Oct 03 10:19:59 AM UTC 24 2827789562 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1414211837 Oct 03 10:19:42 AM UTC 24 Oct 03 10:20:00 AM UTC 24 839913839 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2632292659 Oct 03 10:19:44 AM UTC 24 Oct 03 10:20:01 AM UTC 24 1345500172 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.3771628386 Oct 03 10:19:54 AM UTC 24 Oct 03 10:20:02 AM UTC 24 128824359 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.744929102 Oct 03 10:19:59 AM UTC 24 Oct 03 10:20:02 AM UTC 24 13373273 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.972933055 Oct 03 10:19:58 AM UTC 24 Oct 03 10:20:08 AM UTC 24 592768194 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2794615860 Oct 03 10:19:38 AM UTC 24 Oct 03 10:20:12 AM UTC 24 7058841894 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.781137410 Oct 03 10:19:40 AM UTC 24 Oct 03 10:20:13 AM UTC 24 3130178701 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.627132648 Oct 03 10:19:47 AM UTC 24 Oct 03 10:20:14 AM UTC 24 248025938 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3967850697 Oct 03 10:19:58 AM UTC 24 Oct 03 10:20:15 AM UTC 24 552163778 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3695040041 Oct 03 10:19:58 AM UTC 24 Oct 03 10:20:16 AM UTC 24 462904759 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2697548811 Oct 03 10:20:02 AM UTC 24 Oct 03 10:20:17 AM UTC 24 1121421178 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.838161986 Oct 03 10:19:34 AM UTC 24 Oct 03 10:20:55 AM UTC 24 3030572396 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.4020567846 Oct 03 10:20:17 AM UTC 24 Oct 03 10:20:20 AM UTC 24 36192624 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3146854457 Oct 03 10:18:09 AM UTC 24 Oct 03 10:20:20 AM UTC 24 2158612149 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.4078155821 Oct 03 10:20:01 AM UTC 24 Oct 03 10:20:20 AM UTC 24 2618368676 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.707234653 Oct 03 10:20:12 AM UTC 24 Oct 03 10:20:21 AM UTC 24 897672674 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.3807186575 Oct 03 10:20:02 AM UTC 24 Oct 03 10:20:22 AM UTC 24 1551544040 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1681208242 Oct 03 10:20:21 AM UTC 24 Oct 03 10:20:23 AM UTC 24 77768893 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.820230066 Oct 03 10:19:31 AM UTC 24 Oct 03 10:20:24 AM UTC 24 1608538802 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2956348186 Oct 03 10:20:14 AM UTC 24 Oct 03 10:20:26 AM UTC 24 650818683 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.245103216 Oct 03 10:20:22 AM UTC 24 Oct 03 10:20:27 AM UTC 24 65452060 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1429382246 Oct 03 10:20:21 AM UTC 24 Oct 03 10:20:28 AM UTC 24 57913073 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4051547285 Oct 03 10:20:26 AM UTC 24 Oct 03 10:20:28 AM UTC 24 27597714 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2319129363 Oct 03 10:20:13 AM UTC 24 Oct 03 10:20:28 AM UTC 24 796543082 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.2163087429 Oct 03 10:19:54 AM UTC 24 Oct 03 10:20:29 AM UTC 24 1449122560 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.2336847192 Oct 03 10:19:02 AM UTC 24 Oct 03 10:20:32 AM UTC 24 19459851068 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.394305947 Oct 03 10:20:24 AM UTC 24 Oct 03 10:20:34 AM UTC 24 258285138 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3005246576 Oct 03 10:20:22 AM UTC 24 Oct 03 10:20:34 AM UTC 24 139579226 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.274320295 Oct 03 10:20:22 AM UTC 24 Oct 03 10:20:35 AM UTC 24 466107709 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3408975584 Oct 03 10:20:15 AM UTC 24 Oct 03 10:20:35 AM UTC 24 2216714760 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3400652570 Oct 03 10:18:47 AM UTC 24 Oct 03 10:20:37 AM UTC 24 9121154722 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1585691992 Oct 03 10:20:27 AM UTC 24 Oct 03 10:20:37 AM UTC 24 1519170811 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3161804872 Oct 03 10:19:15 AM UTC 24 Oct 03 10:20:38 AM UTC 24 5496734328 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.1375178932 Oct 03 10:20:08 AM UTC 24 Oct 03 10:20:39 AM UTC 24 2210215452 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.3465516173 Oct 03 10:20:23 AM UTC 24 Oct 03 10:20:40 AM UTC 24 267242623 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3396792293 Oct 03 10:20:39 AM UTC 24 Oct 03 10:20:41 AM UTC 24 20931022 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1178707061 Oct 03 10:20:39 AM UTC 24 Oct 03 10:20:41 AM UTC 24 60636380 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3346989723 Oct 03 10:20:29 AM UTC 24 Oct 03 10:20:42 AM UTC 24 855595547 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3632055337 Oct 03 10:20:29 AM UTC 24 Oct 03 10:20:44 AM UTC 24 336040567 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.51961408 Oct 03 10:20:13 AM UTC 24 Oct 03 10:20:44 AM UTC 24 3224305078 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.673362905 Oct 03 10:20:35 AM UTC 24 Oct 03 10:20:46 AM UTC 24 253144154 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.537009599 Oct 03 10:20:40 AM UTC 24 Oct 03 10:20:46 AM UTC 24 464345916 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.842337382 Oct 03 10:20:01 AM UTC 24 Oct 03 10:20:46 AM UTC 24 2834652720 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1562383712 Oct 03 10:20:40 AM UTC 24 Oct 03 10:20:47 AM UTC 24 326942058 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.891581996 Oct 03 10:20:45 AM UTC 24 Oct 03 10:20:47 AM UTC 24 26907001 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.3991607427 Oct 03 10:20:30 AM UTC 24 Oct 03 10:20:47 AM UTC 24 776852807 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1069158659 Oct 03 10:20:39 AM UTC 24 Oct 03 10:20:48 AM UTC 24 509463985 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3504875942 Oct 03 10:20:35 AM UTC 24 Oct 03 10:20:48 AM UTC 24 1333516853 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3487790237 Oct 03 10:20:34 AM UTC 24 Oct 03 10:20:53 AM UTC 24 5746527594 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.982575790 Oct 03 10:20:47 AM UTC 24 Oct 03 10:20:54 AM UTC 24 1095258252 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1870749054 Oct 03 10:20:36 AM UTC 24 Oct 03 10:20:54 AM UTC 24 2676643401 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1628051543 Oct 03 10:20:21 AM UTC 24 Oct 03 10:20:56 AM UTC 24 1926237094 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2169970539 Oct 03 10:20:34 AM UTC 24 Oct 03 10:20:57 AM UTC 24 2731367772 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.2871888746 Oct 03 10:20:03 AM UTC 24 Oct 03 10:20:57 AM UTC 24 8512429731 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1056767502 Oct 03 10:20:47 AM UTC 24 Oct 03 10:20:57 AM UTC 24 1554040921 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.4236952384 Oct 03 10:20:48 AM UTC 24 Oct 03 10:20:58 AM UTC 24 1517639117 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.821394096 Oct 03 10:20:42 AM UTC 24 Oct 03 10:20:58 AM UTC 24 2535283512 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.741779087 Oct 03 10:20:58 AM UTC 24 Oct 03 10:21:00 AM UTC 24 49140023 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1153089160 Oct 03 10:20:58 AM UTC 24 Oct 03 10:21:00 AM UTC 24 93548513 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.4101206812 Oct 03 10:20:45 AM UTC 24 Oct 03 10:21:00 AM UTC 24 778847964 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1517522356 Oct 03 10:21:01 AM UTC 24 Oct 03 10:21:05 AM UTC 24 42064662 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.807701729 Oct 03 10:20:42 AM UTC 24 Oct 03 10:21:05 AM UTC 24 2717127219 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.554537588 Oct 03 10:20:43 AM UTC 24 Oct 03 10:21:05 AM UTC 24 1071209628 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.3350399139 Oct 03 10:20:50 AM UTC 24 Oct 03 10:21:06 AM UTC 24 377281957 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.696857680 Oct 03 10:20:59 AM UTC 24 Oct 03 10:21:06 AM UTC 24 82104520 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.3436819009 Oct 03 10:20:58 AM UTC 24 Oct 03 10:21:07 AM UTC 24 335469123 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1536392690 Oct 03 10:20:54 AM UTC 24 Oct 03 10:21:07 AM UTC 24 465114545 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2254128 Oct 03 10:20:16 AM UTC 24 Oct 03 10:21:10 AM UTC 24 3679219162 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1954160343 Oct 03 10:20:49 AM UTC 24 Oct 03 10:21:10 AM UTC 24 1546549116 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3253429711 Oct 03 10:20:55 AM UTC 24 Oct 03 10:21:10 AM UTC 24 1021394628 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1004794890 Oct 03 10:20:17 AM UTC 24 Oct 03 10:21:11 AM UTC 24 8638806500 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1770189952 Oct 03 10:21:06 AM UTC 24 Oct 03 10:21:11 AM UTC 24 117746806 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1873275899 Oct 03 10:21:07 AM UTC 24 Oct 03 10:21:12 AM UTC 24 133532692 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3614068885 Oct 03 10:20:49 AM UTC 24 Oct 03 10:21:12 AM UTC 24 1167932260 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.1024944414 Oct 03 10:20:40 AM UTC 24 Oct 03 10:21:12 AM UTC 24 242960863 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3795969505 Oct 03 10:20:59 AM UTC 24 Oct 03 10:21:12 AM UTC 24 645460560 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2904280149 Oct 03 10:20:59 AM UTC 24 Oct 03 10:21:13 AM UTC 24 460934582 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.709706046 Oct 03 10:21:08 AM UTC 24 Oct 03 10:21:13 AM UTC 24 744761270 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.2105244630 Oct 03 10:20:47 AM UTC 24 Oct 03 10:21:14 AM UTC 24 1276145409 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.2724060432 Oct 03 10:21:11 AM UTC 24 Oct 03 10:21:14 AM UTC 24 92138205 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.402526415 Oct 03 10:21:13 AM UTC 24 Oct 03 10:21:15 AM UTC 24 16109178 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.765837562 Oct 03 10:21:07 AM UTC 24 Oct 03 10:21:16 AM UTC 24 429968780 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.26733089 Oct 03 10:21:12 AM UTC 24 Oct 03 10:21:18 AM UTC 24 234563437 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.4018500304 Oct 03 10:21:14 AM UTC 24 Oct 03 10:21:18 AM UTC 24 373388868 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.2677855176 Oct 03 10:21:16 AM UTC 24 Oct 03 10:21:19 AM UTC 24 11921385 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3208106552 Oct 03 10:21:01 AM UTC 24 Oct 03 10:21:22 AM UTC 24 992607836 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2333111251 Oct 03 10:20:29 AM UTC 24 Oct 03 10:21:22 AM UTC 24 7132914233 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3478024472 Oct 03 10:21:11 AM UTC 24 Oct 03 10:21:22 AM UTC 24 1429127451 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.231502443 Oct 03 10:21:01 AM UTC 24 Oct 03 10:21:24 AM UTC 24 374410770 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2169359205 Oct 03 10:21:14 AM UTC 24 Oct 03 10:21:25 AM UTC 24 267235776 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3715591464 Oct 03 10:21:17 AM UTC 24 Oct 03 10:21:25 AM UTC 24 220961301 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2218651590 Oct 03 10:21:14 AM UTC 24 Oct 03 10:21:27 AM UTC 24 81052413 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.475939334 Oct 03 10:20:59 AM UTC 24 Oct 03 10:21:27 AM UTC 24 925910330 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.477524242 Oct 03 10:21:15 AM UTC 24 Oct 03 10:21:30 AM UTC 24 1246858788 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3848524902 Oct 03 10:21:06 AM UTC 24 Oct 03 10:21:58 AM UTC 24 7109092006 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3245190134 Oct 03 10:21:10 AM UTC 24 Oct 03 10:21:30 AM UTC 24 298204318 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2017889162 Oct 03 10:21:20 AM UTC 24 Oct 03 10:21:30 AM UTC 24 4335780614 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.573654101 Oct 03 10:21:09 AM UTC 24 Oct 03 10:21:30 AM UTC 24 1436578165 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1263258491 Oct 03 10:21:23 AM UTC 24 Oct 03 10:21:30 AM UTC 24 290879422 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1695630493 Oct 03 10:21:11 AM UTC 24 Oct 03 10:21:31 AM UTC 24 782271067 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.1639008098 Oct 03 10:19:44 AM UTC 24 Oct 03 10:21:32 AM UTC 24 16935648501 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.356157412 Oct 03 10:21:23 AM UTC 24 Oct 03 10:21:32 AM UTC 24 936663398 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.905055640 Oct 03 10:21:31 AM UTC 24 Oct 03 10:21:34 AM UTC 24 39722769 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3083231165 Oct 03 10:21:31 AM UTC 24 Oct 03 10:21:34 AM UTC 24 75753043 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1509116359 Oct 03 10:21:15 AM UTC 24 Oct 03 10:21:36 AM UTC 24 985303205 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.273589299 Oct 03 10:21:33 AM UTC 24 Oct 03 10:21:39 AM UTC 24 276235346 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2412342675 Oct 03 10:21:31 AM UTC 24 Oct 03 10:21:39 AM UTC 24 318118010 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.14299506 Oct 03 10:21:14 AM UTC 24 Oct 03 10:21:40 AM UTC 24 273683883 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1134239933 Oct 03 10:21:26 AM UTC 24 Oct 03 10:21:40 AM UTC 24 475887787 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1811944716 Oct 03 10:21:26 AM UTC 24 Oct 03 10:21:42 AM UTC 24 4353482572 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3824410358 Oct 03 10:21:06 AM UTC 24 Oct 03 10:21:42 AM UTC 24 816306771 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.3497863923 Oct 03 10:21:33 AM UTC 24 Oct 03 10:21:42 AM UTC 24 996529217 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.487846039 Oct 03 10:21:34 AM UTC 24 Oct 03 10:21:45 AM UTC 24 2015112117 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1981057084 Oct 03 10:21:32 AM UTC 24 Oct 03 10:21:46 AM UTC 24 48689589 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2325705421 Oct 03 10:20:31 AM UTC 24 Oct 03 10:21:46 AM UTC 24 2877590793 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.3603907139 Oct 03 10:21:40 AM UTC 24 Oct 03 10:21:46 AM UTC 24 174570671 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.3146946225 Oct 03 10:21:33 AM UTC 24 Oct 03 10:21:46 AM UTC 24 414086539 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3159165595 Oct 03 10:21:28 AM UTC 24 Oct 03 10:21:46 AM UTC 24 1170959924 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3458931585 Oct 03 10:21:24 AM UTC 24 Oct 03 10:21:47 AM UTC 24 5432297079 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1770170766 Oct 03 10:21:20 AM UTC 24 Oct 03 10:21:47 AM UTC 24 3767881844 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.1141866805 Oct 03 10:21:47 AM UTC 24 Oct 03 10:21:49 AM UTC 24 70570570 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2792277352 Oct 03 10:21:47 AM UTC 24 Oct 03 10:21:49 AM UTC 24 12822379 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3280672445 Oct 03 10:20:47 AM UTC 24 Oct 03 10:21:56 AM UTC 24 11638436828 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.3613853449 Oct 03 10:21:50 AM UTC 24 Oct 03 10:22:03 AM UTC 24 4439978149 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2963679161 Oct 03 10:21:47 AM UTC 24 Oct 03 10:21:50 AM UTC 24 136911499 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.3091068555 Oct 03 10:21:36 AM UTC 24 Oct 03 10:21:53 AM UTC 24 1150045044 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1425060392 Oct 03 10:21:41 AM UTC 24 Oct 03 10:21:53 AM UTC 24 458500709 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.803710279 Oct 03 10:21:48 AM UTC 24 Oct 03 10:21:54 AM UTC 24 148272406 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3363333358 Oct 03 10:21:42 AM UTC 24 Oct 03 10:21:56 AM UTC 24 1038324255 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1783662797 Oct 03 10:21:41 AM UTC 24 Oct 03 10:21:58 AM UTC 24 2358383732 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2685841222 Oct 03 10:22:00 AM UTC 24 Oct 03 10:22:02 AM UTC 24 65969362 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.2861993693 Oct 03 10:21:54 AM UTC 24 Oct 03 10:21:59 AM UTC 24 164540518 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.1658887678 Oct 03 10:21:47 AM UTC 24 Oct 03 10:22:00 AM UTC 24 216796613 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.2249494471 Oct 03 10:21:43 AM UTC 24 Oct 03 10:22:01 AM UTC 24 3037483818 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1364456598 Oct 03 10:21:48 AM UTC 24 Oct 03 10:22:03 AM UTC 24 350739328 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4079623117 Oct 03 10:21:11 AM UTC 24 Oct 03 10:22:04 AM UTC 24 5641808946 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1915547866 Oct 03 10:22:02 AM UTC 24 Oct 03 10:22:04 AM UTC 24 24528124 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.3145490823 Oct 03 10:21:32 AM UTC 24 Oct 03 10:22:05 AM UTC 24 278458727 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1216115038 Oct 03 10:21:55 AM UTC 24 Oct 03 10:22:05 AM UTC 24 660399515 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.741227062 Oct 03 10:21:48 AM UTC 24 Oct 03 10:22:05 AM UTC 24 1241927437 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.3180138998 Oct 03 10:22:01 AM UTC 24 Oct 03 10:22:06 AM UTC 24 870596889 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2869660142 Oct 03 10:21:57 AM UTC 24 Oct 03 10:22:08 AM UTC 24 255214761 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.3887531677 Oct 03 10:22:03 AM UTC 24 Oct 03 10:22:09 AM UTC 24 238364563 ps
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