Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53033617

1

T1

2640

T2

1350

T3

1192

auto[1]

1106823

1

T4

297

T5

98

T12

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53059825

1

T1

2640

T2

1350

T3

1192

auto[1]

1080615

1

T4

891

T12

396

T13

99

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5073366	1			T1	656		T2	120		T3	96
auto[IdleSt]	14458499	1			T1	714		T2	16		T3	1096
auto[ClkMuxSt]	27028	1			T1	7		T2	1		T4	12
auto[CntIncrSt]	26843	1			T1	7		T2	1		T4	12
auto[CntProgSt]	1274444	1			T1	117		T2	49		T4	542
auto[TransCheckSt]	21573	1			T1	7		T2	1		T12	2
auto[TokenHashSt]	14781970	1			T1	76		T2	94		T12	25
auto[FlashRmaSt]	26095	1			T1	38		T12	2		T6	23
auto[TokenCheck0St]	9493	1			T1	7		T12	2		T6	7
auto[TokenCheck1St]	6866	1			T1	7		T12	2		T6	7
auto[TransProgSt]	272376	1			T1	60		T12	384		T6	107
auto[PostTransSt]	7454387	1			T1	944		T2	1068		T4	746
auto[ScrapSt]	336058	1			T24	8		T21	16		T40	409
auto[EscalateSt]	4153455	1			T4	1560		T5	501		T12	1590
auto[InvalidSt]	6216605	1			T12	1059		T7	12933		T19	1556

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1382	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6216605	1			T12	1059		T7	12933		T19	1556
EscalateSt	4153455	1			T4	1560		T5	501		T12	1590
ScrapSt	336058	1			T24	8		T21	16		T40	409
PostTransSt	7454387	1			T1	944		T2	1068		T4	746
TransProgSt	272376	1			T1	60		T12	384		T6	107
TokenCheck1St	6866	1			T1	7		T12	2		T6	7
TokenCheck0St	9493	1			T1	7		T12	2		T6	7
FlashRmaSt	26095	1			T1	38		T12	2		T6	23
TokenHashSt	14781970	1			T1	76		T2	94		T12	25
TransCheckSt	21573	1			T1	7		T2	1		T12	2
CntProgSt	1274444	1			T1	117		T2	49		T4	542
CntIncrSt	26843	1			T1	7		T2	1		T4	12
ClkMuxSt	27028	1			T1	7		T2	1		T4	12
IdleSt	14458499	1			T1	714		T2	16		T3	1096
ResetSt	5073366	1			T1	656		T2	120		T3	96
arcs[ResetSt=>IdleSt]	40029	1			T1	7		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	243	1			T24	2		T21	2		T40	5
arcs[IdleSt=>ClkMuxSt]	26883	1			T1	7		T2	1		T4	12
arcs[ClkMuxSt=>CntIncrSt]	26843	1			T1	7		T2	1		T4	12
arcs[CntIncrSt=>PostTransSt]	1063	1			T13	6		T17	10		T25	3
arcs[CntIncrSt=>CntProgSt]	25715	1			T1	7		T2	1		T4	12
arcs[CntProgSt=>PostTransSt]	3149	1			T4	12		T5	1		T13	1
arcs[CntProgSt=>TransCheckSt]	21573	1			T1	7		T2	1		T12	2
arcs[TransCheckSt=>PostTransSt]	3107	1			T13	8		T20	48		T17	11
arcs[TransCheckSt=>TokenHashSt]	18339	1			T1	7		T2	1		T12	2
arcs[TokenHashSt=>PostTransSt]	7957	1			T2	1		T13	27		T14	1
arcs[TokenHashSt=>FlashRmaSt]	9535	1			T1	7		T12	2		T6	7
arcs[FlashRmaSt=>TokenCheck0St]	9493	1			T1	7		T12	2		T6	7
arcs[TokenCheck0St=>PostTransSt]	2566	1			T13	7		T19	6		T20	15
arcs[TokenCheck0St=>TokenCheck1St]	6866	1			T1	7		T12	2		T6	7
arcs[TokenCheck1St=>PostTransSt]	606	1			T13	1		T20	8		T41	11
arcs[TransProgSt=>PostTransSt]	5412	1			T1	7		T12	2		T6	7
arcs[IdleSt=>EscalateSt]	172	1			T24	2		T54	7		T55	3
arcs[ClkMuxSt=>EscalateSt]	40	1			T24	2		T54	1		T55	1
arcs[CntIncrSt=>EscalateSt]	65	1			T55	3		T56	2		T57	1
arcs[CntProgSt=>EscalateSt]	993	1			T24	34		T54	25		T55	18
arcs[TransCheckSt=>EscalateSt]	127	1			T54	4		T56	6		T60	7
arcs[TokenHashSt=>EscalateSt]	847	1			T24	11		T54	9		T55	7
arcs[FlashRmaSt=>EscalateSt]	42	1			T24	2		T54	1		T56	1
arcs[TokenCheck0St=>EscalateSt]	61	1			T24	2		T54	2		T55	2
arcs[TokenCheck1St=>EscalateSt]	34	1			T24	1		T55	1		T57	1
arcs[TransProgSt=>EscalateSt]	814	1			T24	28		T54	10		T55	13
arcs[PostTransSt=>EscalateSt]	3480	1			T4	12		T5	1		T13	1
arcs[InvalidSt=>EscalateSt]	9400	1			T12	7		T7	8		T19	20

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5073187	1			T1	656		T2	120		T3	96
auto[0]	auto[IdleSt]	14458385	1			T1	714		T2	16		T3	1096
auto[0]	auto[ClkMuxSt]	27004	1			T1	7		T2	1		T4	12
auto[0]	auto[CntIncrSt]	26801	1			T1	7		T2	1		T4	12
auto[0]	auto[CntProgSt]	1273757	1			T1	117		T2	49		T4	542
auto[0]	auto[TransCheckSt]	21487	1			T1	7		T2	1		T12	2
auto[0]	auto[TokenHashSt]	14781401	1			T1	76		T2	94		T12	25
auto[0]	auto[FlashRmaSt]	26068	1			T1	38		T12	2		T6	23
auto[0]	auto[TokenCheck0St]	9448	1			T1	7		T12	2		T6	7
auto[0]	auto[TokenCheck1St]	6843	1			T1	7		T12	2		T6	7
auto[0]	auto[TransProgSt]	271817	1			T1	60		T12	384		T6	107
auto[0]	auto[PostTransSt]	7452590	1			T1	944		T2	1068		T4	743
auto[0]	auto[ScrapSt]	336013	1			T24	7		T21	16		T40	409
auto[0]	auto[EscalateSt]	3055582	1			T4	1266		T5	404		T12	1296
auto[0]	auto[InvalidSt]	6211852	1			T12	1056		T7	12930		T19	1545
auto[1]	auto[ResetSt]	179	1			T24	5		T54	3		T55	4
auto[1]	auto[IdleSt]	114	1			T54	3		T55	2		T56	4
auto[1]	auto[ClkMuxSt]	24	1			T24	2		T54	1		T55	1
auto[1]	auto[CntIncrSt]	42	1			T55	3		T56	1		T208	1
auto[1]	auto[CntProgSt]	687	1			T24	19		T54	18		T55	15
auto[1]	auto[TransCheckSt]	86	1			T54	1		T56	5		T60	6
auto[1]	auto[TokenHashSt]	569	1			T24	7		T54	8		T55	5
auto[1]	auto[FlashRmaSt]	27	1			T24	2		T54	1		T56	1
auto[1]	auto[TokenCheck0St]	45	1			T24	2		T54	2		T55	2
auto[1]	auto[TokenCheck1St]	23	1			T24	1		T55	1		T208	1
auto[1]	auto[TransProgSt]	559	1			T24	23		T54	4		T55	11
auto[1]	auto[PostTransSt]	1797	1			T4	3		T5	1		T19	11
auto[1]	auto[ScrapSt]	45	1			T24	1		T55	1		T57	3
auto[1]	auto[EscalateSt]	1097873	1			T4	294		T5	97		T12	294
auto[1]	auto[InvalidSt]	4753	1			T12	3		T7	3		T19	11

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5073197	1			T1	656		T2	120		T3	96
auto[0]	auto[IdleSt]	14458385	1			T1	714		T2	16		T3	1096
auto[0]	auto[ClkMuxSt]	26999	1			T1	7		T2	1		T4	12
auto[0]	auto[CntIncrSt]	26798	1			T1	7		T2	1		T4	12
auto[0]	auto[CntProgSt]	1273790	1			T1	117		T2	49		T4	542
auto[0]	auto[TransCheckSt]	21491	1			T1	7		T2	1		T12	2
auto[0]	auto[TokenHashSt]	14781421	1			T1	76		T2	94		T12	25
auto[0]	auto[FlashRmaSt]	26066	1			T1	38		T12	2		T6	23
auto[0]	auto[TokenCheck0St]	9458	1			T1	7		T12	2		T6	7
auto[0]	auto[TokenCheck1St]	6843	1			T1	7		T12	2		T6	7
auto[0]	auto[TransProgSt]	271818	1			T1	60		T12	384		T6	107
auto[0]	auto[PostTransSt]	7452612	1			T1	944		T2	1068		T4	737
auto[0]	auto[ScrapSt]	336015	1			T24	6		T21	16		T40	409
auto[0]	auto[EscalateSt]	3081592	1			T4	678		T5	501		T12	1198
auto[0]	auto[InvalidSt]	6211958	1			T12	1055		T7	12928		T19	1547
auto[1]	auto[ResetSt]	169	1			T24	6		T54	2		T55	2
auto[1]	auto[IdleSt]	114	1			T24	2		T54	4		T55	1
auto[1]	auto[ClkMuxSt]	29	1			T54	1		T56	1		T60	1
auto[1]	auto[CntIncrSt]	45	1			T55	2		T56	2		T57	1
auto[1]	auto[CntProgSt]	654	1			T24	25		T54	17		T55	9
auto[1]	auto[TransCheckSt]	82	1			T54	3		T56	3		T60	6
auto[1]	auto[TokenHashSt]	549	1			T24	9		T54	3		T55	4
auto[1]	auto[FlashRmaSt]	29	1			T56	1		T60	1		T57	1
auto[1]	auto[TokenCheck0St]	35	1			T54	1		T55	1		T56	1
auto[1]	auto[TokenCheck1St]	23	1			T24	1		T57	1		T208	1
auto[1]	auto[TransProgSt]	558	1			T24	19		T54	7		T55	7
auto[1]	auto[PostTransSt]	1775	1			T4	9		T13	1		T19	16
auto[1]	auto[ScrapSt]	43	1			T24	2		T55	1		T56	1
auto[1]	auto[EscalateSt]	1071863	1			T4	882		T12	392		T13	98
auto[1]	auto[InvalidSt]	4647	1			T12	4		T7	5		T19	9