Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.90 97.90 96.03 93.40 97.62 98.49 98.76 96.11


Total tests in report: 995
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.65 64.65 81.95 81.95 46.67 46.67 62.29 62.29 54.76 54.76 83.23 83.23 92.04 92.04 31.63 31.63 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1170863005
78.31 13.66 90.24 8.28 80.68 34.01 78.16 15.87 59.52 4.76 91.61 8.39 94.28 2.24 53.71 22.08 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3649150121
85.06 6.74 90.34 0.10 82.62 1.94 81.17 3.02 85.71 26.19 93.12 1.51 94.78 0.50 67.67 13.96 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.923263262
87.58 2.52 96.78 6.44 83.36 0.74 82.42 1.24 88.10 2.38 94.84 1.72 94.78 0.00 72.79 5.12 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3910984080
89.28 1.70 96.83 0.05 85.95 2.59 87.15 4.73 88.10 0.00 95.48 0.65 94.78 0.00 76.68 3.89 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.16204865
90.47 1.19 96.93 0.10 87.71 1.76 87.19 0.04 88.10 0.00 96.13 0.65 95.77 1.00 81.45 4.77 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2275098286
91.40 0.93 96.93 0.00 87.71 0.00 87.19 0.00 92.86 4.76 96.13 0.00 95.77 0.00 83.22 1.77 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.2443464965
92.21 0.81 97.03 0.10 88.45 0.74 87.69 0.51 95.24 2.38 96.56 0.43 96.02 0.25 84.45 1.24 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.476872221
92.78 0.58 97.03 0.00 88.45 0.00 88.73 1.04 95.24 0.00 96.56 0.00 96.02 0.00 87.46 3.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1319974188
93.31 0.53 97.03 0.00 88.54 0.09 90.93 2.20 95.24 0.00 96.56 0.00 96.02 0.00 88.87 1.41 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.154066144
93.83 0.52 97.09 0.05 89.37 0.83 91.10 0.17 95.24 0.00 96.77 0.22 96.77 0.75 90.46 1.59 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3698876517
94.23 0.41 97.24 0.15 90.57 1.20 91.10 0.00 95.24 0.00 97.20 0.43 96.77 0.00 91.52 1.06 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.500361563
94.61 0.37 97.24 0.00 90.57 0.00 91.33 0.22 97.62 2.38 97.20 0.00 96.77 0.00 91.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.255796856
94.92 0.31 97.24 0.00 90.57 0.00 92.24 0.91 97.62 0.00 97.42 0.22 96.77 0.00 92.58 1.06 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2222455388
95.22 0.30 97.29 0.05 90.57 0.00 92.48 0.24 97.62 0.00 97.63 0.22 96.77 0.00 94.17 1.59 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.4027204294
95.47 0.25 97.29 0.00 90.57 0.00 92.48 0.00 97.62 0.00 97.63 0.00 98.51 1.74 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.98617177
95.67 0.20 97.65 0.36 91.50 0.92 92.58 0.10 97.62 0.00 97.63 0.00 98.51 0.00 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.352360802
95.82 0.15 97.75 0.10 92.24 0.74 92.58 0.00 97.62 0.00 97.85 0.22 98.51 0.00 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.3159101653
95.95 0.13 97.75 0.00 93.16 0.92 92.58 0.00 97.62 0.00 97.85 0.00 98.51 0.00 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2899974664
96.08 0.13 97.75 0.00 93.72 0.55 92.58 0.00 97.62 0.00 97.85 0.00 98.51 0.00 94.52 0.35 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1859246787
96.18 0.10 97.75 0.00 93.81 0.09 92.99 0.40 97.62 0.00 98.06 0.22 98.51 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.976370701
96.26 0.08 97.75 0.00 94.36 0.55 92.99 0.00 97.62 0.00 98.06 0.00 98.51 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1814166226
96.34 0.08 97.80 0.05 94.45 0.09 92.99 0.00 97.62 0.00 98.28 0.22 98.51 0.00 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.14060642
96.40 0.07 97.80 0.00 94.45 0.00 93.29 0.30 97.62 0.00 98.28 0.00 98.51 0.00 94.88 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3456020942
96.47 0.06 97.80 0.00 94.73 0.28 93.29 0.00 97.62 0.00 98.28 0.00 98.51 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3508228223
96.53 0.06 97.80 0.00 94.73 0.00 93.36 0.07 97.62 0.00 98.28 0.00 98.51 0.00 95.41 0.35 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1937819888
96.59 0.06 97.90 0.10 94.82 0.09 93.36 0.00 97.62 0.00 98.49 0.22 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.351743051
96.63 0.04 97.90 0.00 95.10 0.28 93.36 0.00 97.62 0.00 98.49 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.303156559
96.67 0.04 97.90 0.00 95.38 0.28 93.36 0.00 97.62 0.00 98.49 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2829969015
96.70 0.04 97.90 0.00 95.38 0.00 93.36 0.00 97.62 0.00 98.49 0.00 98.76 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1915695135
96.73 0.03 97.90 0.00 95.38 0.00 93.38 0.02 97.62 0.00 98.49 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3326908745
96.76 0.03 97.90 0.00 95.38 0.00 93.39 0.01 97.62 0.00 98.49 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2175575200
96.78 0.03 97.90 0.00 95.56 0.18 93.39 0.00 97.62 0.00 98.49 0.00 98.76 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3956784836
96.81 0.03 97.90 0.00 95.56 0.00 93.39 0.00 97.62 0.00 98.49 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1197136092
96.83 0.03 97.90 0.00 95.56 0.00 93.39 0.00 97.62 0.00 98.49 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2324830607
96.85 0.01 97.90 0.00 95.66 0.09 93.39 0.00 97.62 0.00 98.49 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3239044552
96.86 0.01 97.90 0.00 95.75 0.09 93.39 0.00 97.62 0.00 98.49 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.584184663
96.87 0.01 97.90 0.00 95.84 0.09 93.39 0.00 97.62 0.00 98.49 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1566427572
96.89 0.01 97.90 0.00 95.93 0.09 93.39 0.00 97.62 0.00 98.49 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3134315609
96.90 0.01 97.90 0.00 96.03 0.09 93.39 0.00 97.62 0.00 98.49 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3939754980
96.90 0.01 97.90 0.00 96.03 0.00 93.40 0.01 97.62 0.00 98.49 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2616038989

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1546694084
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3004317520
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1908075063
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3201341149
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1152855014
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2292699683
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.198930271
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3382275715
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2269623750
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3752225619
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2864316177
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2546788813
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1112599683
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1853284989
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2588810945
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3820251319
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2489064352
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2846120014
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3270740898
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3157923904
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2351050762
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3186944215
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2461782353
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2030790991
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1480747917
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3731267014
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.962931353
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1787115930
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1467863589
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3821178773
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3145240301
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1398576647
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3539477231
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3614555082
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.974416096
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2988514616
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2222338297
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3259029693
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.146436752
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1604253820
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2655591707
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3324953043
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.64037159
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.822075886
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1286916212
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4231685399
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2573419030
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1233399810
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2728061026
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.445901296
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.894134290
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1950595525
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1114242433
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1460461570
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.802194221
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3766812237
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.3030482284
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3492483373
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3695167946
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.3319529995
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1181274691
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2027504582
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1776810274
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.1414268212
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.3049403169
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3528421510
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1257643119
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3094094184
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.642783905
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3145488434
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.2475385543
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.3167955150
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1420532299
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1270547271
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.4074574072
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1459104763
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.909592180
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3117848812
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.1862877379
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1656198117
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1611802112
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.142836392
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.432383257
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3043103729
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.454458494
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3224127445
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.4056518088
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1377862494
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2805880656
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1517662501
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1628352043
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.690568867
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1711009462
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2658052127
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3281918381
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.843954593
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.716008535
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1505640545
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2297870150
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3812367220
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.3149232849
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2761736208
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3525755615
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.809079427
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1543852565
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2815677005
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.1948479888
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1987958146
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.284564391
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.123658314
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3504854495
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3327595762
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3998436319
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2749001105
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3528594742
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.1391673932
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.671622362
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2976288677
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1008091556



Total test records in report: 995
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.365489414 Oct 09 10:48:17 AM UTC 24 Oct 09 10:48:20 AM UTC 24 55013162 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2175575200 Oct 09 10:48:18 AM UTC 24 Oct 09 10:48:20 AM UTC 24 13651486 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3326908745 Oct 09 10:48:18 AM UTC 24 Oct 09 10:48:21 AM UTC 24 12451505 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1937819888 Oct 09 10:48:18 AM UTC 24 Oct 09 10:48:22 AM UTC 24 860906519 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.3144722737 Oct 09 10:48:19 AM UTC 24 Oct 09 10:48:24 AM UTC 24 356137319 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.1437989690 Oct 09 10:48:18 AM UTC 24 Oct 09 10:48:28 AM UTC 24 144724178 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.4199682933 Oct 09 10:48:19 AM UTC 24 Oct 09 10:48:28 AM UTC 24 916191078 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1170863005 Oct 09 10:48:18 AM UTC 24 Oct 09 10:48:29 AM UTC 24 228090900 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2193020843 Oct 09 10:48:29 AM UTC 24 Oct 09 10:48:32 AM UTC 24 14563551 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.352360802 Oct 09 10:48:29 AM UTC 24 Oct 09 10:48:32 AM UTC 24 18927606 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1319974188 Oct 09 10:48:19 AM UTC 24 Oct 09 10:48:34 AM UTC 24 2107391501 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.2390897546 Oct 09 10:48:29 AM UTC 24 Oct 09 10:48:35 AM UTC 24 107924335 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3698876517 Oct 09 10:48:19 AM UTC 24 Oct 09 10:48:37 AM UTC 24 411123603 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3910984080 Oct 09 10:48:21 AM UTC 24 Oct 09 10:48:38 AM UTC 24 365164029 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.4027204294 Oct 09 10:48:21 AM UTC 24 Oct 09 10:48:39 AM UTC 24 367352440 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.923263262 Oct 09 10:48:18 AM UTC 24 Oct 09 10:48:39 AM UTC 24 1988836516 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3040736006 Oct 09 10:48:18 AM UTC 24 Oct 09 10:48:40 AM UTC 24 1239265648 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.984176849 Oct 09 10:48:38 AM UTC 24 Oct 09 10:48:41 AM UTC 24 33840510 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3871718314 Oct 09 10:48:22 AM UTC 24 Oct 09 10:48:41 AM UTC 24 1495559297 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2616038989 Oct 09 10:48:20 AM UTC 24 Oct 09 10:48:41 AM UTC 24 828270687 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.523452270 Oct 09 10:48:35 AM UTC 24 Oct 09 10:48:41 AM UTC 24 107659846 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.748044489 Oct 09 10:48:18 AM UTC 24 Oct 09 10:48:43 AM UTC 24 233593745 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3683081215 Oct 09 10:48:33 AM UTC 24 Oct 09 10:48:44 AM UTC 24 247836760 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.872432307 Oct 09 10:48:42 AM UTC 24 Oct 09 10:48:50 AM UTC 24 1259044044 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2056218973 Oct 09 10:48:36 AM UTC 24 Oct 09 10:48:50 AM UTC 24 288362648 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.534950519 Oct 09 10:48:42 AM UTC 24 Oct 09 10:48:51 AM UTC 24 395095901 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3972642463 Oct 09 10:48:20 AM UTC 24 Oct 09 10:48:53 AM UTC 24 1765726415 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2166789384 Oct 09 10:48:42 AM UTC 24 Oct 09 10:48:56 AM UTC 24 647598065 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.16204865 Oct 09 10:48:33 AM UTC 24 Oct 09 10:48:57 AM UTC 24 1549504908 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3649150121 Oct 09 10:48:24 AM UTC 24 Oct 09 10:48:57 AM UTC 24 10273884950 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2209954489 Oct 09 10:48:44 AM UTC 24 Oct 09 10:48:57 AM UTC 24 552354281 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.2281234148 Oct 09 10:48:57 AM UTC 24 Oct 09 10:48:59 AM UTC 24 90255008 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.296197529 Oct 09 10:48:24 AM UTC 24 Oct 09 10:49:00 AM UTC 24 873893344 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.280005123 Oct 09 10:48:39 AM UTC 24 Oct 09 10:49:00 AM UTC 24 2022753436 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4142163951 Oct 09 10:48:59 AM UTC 24 Oct 09 10:49:01 AM UTC 24 14050541 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.466560917 Oct 09 10:48:36 AM UTC 24 Oct 09 10:49:01 AM UTC 24 557539152 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1085653614 Oct 09 10:48:44 AM UTC 24 Oct 09 10:49:02 AM UTC 24 264415730 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.405444351 Oct 09 10:48:38 AM UTC 24 Oct 09 10:49:02 AM UTC 24 1883912973 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1398444801 Oct 09 10:48:58 AM UTC 24 Oct 09 10:49:04 AM UTC 24 95202793 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2157754752 Oct 09 10:49:02 AM UTC 24 Oct 09 10:49:05 AM UTC 24 11718898 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.484306858 Oct 09 10:48:41 AM UTC 24 Oct 09 10:49:05 AM UTC 24 1685463174 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.808490036 Oct 09 10:49:00 AM UTC 24 Oct 09 10:49:05 AM UTC 24 67442717 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2955778346 Oct 09 10:49:02 AM UTC 24 Oct 09 10:49:07 AM UTC 24 289940408 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3112106171 Oct 09 10:48:51 AM UTC 24 Oct 09 10:49:08 AM UTC 24 1670719758 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2923050702 Oct 09 10:49:00 AM UTC 24 Oct 09 10:49:08 AM UTC 24 129264474 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1281541711 Oct 09 10:49:01 AM UTC 24 Oct 09 10:49:09 AM UTC 24 239367198 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1515154446 Oct 09 10:48:42 AM UTC 24 Oct 09 10:49:10 AM UTC 24 1612265957 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1861905113 Oct 09 10:48:19 AM UTC 24 Oct 09 10:49:10 AM UTC 24 1482613102 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.253317611 Oct 09 10:49:06 AM UTC 24 Oct 09 10:49:11 AM UTC 24 1253307330 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3193963769 Oct 09 10:49:12 AM UTC 24 Oct 09 10:49:14 AM UTC 24 83780011 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2986361061 Oct 09 10:49:06 AM UTC 24 Oct 09 10:49:17 AM UTC 24 1143001053 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.541543104 Oct 09 10:49:15 AM UTC 24 Oct 09 10:49:18 AM UTC 24 68386822 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3335675206 Oct 09 10:49:16 AM UTC 24 Oct 09 10:49:19 AM UTC 24 39736238 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.1828604594 Oct 09 10:49:05 AM UTC 24 Oct 09 10:49:19 AM UTC 24 563677427 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.397545085 Oct 09 10:49:06 AM UTC 24 Oct 09 10:49:19 AM UTC 24 1386160938 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.1199807617 Oct 09 10:49:01 AM UTC 24 Oct 09 10:49:20 AM UTC 24 238906868 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2052153810 Oct 09 10:49:00 AM UTC 24 Oct 09 10:49:21 AM UTC 24 1579598016 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4036790405 Oct 09 10:48:19 AM UTC 24 Oct 09 10:49:21 AM UTC 24 10228701603 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1173554007 Oct 09 10:49:19 AM UTC 24 Oct 09 10:49:23 AM UTC 24 113543536 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1288468040 Oct 09 10:49:09 AM UTC 24 Oct 09 10:49:23 AM UTC 24 1093073687 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.659417998 Oct 09 10:49:18 AM UTC 24 Oct 09 10:49:24 AM UTC 24 53650721 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.786526774 Oct 09 10:49:22 AM UTC 24 Oct 09 10:49:25 AM UTC 24 12987177 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.971385388 Oct 09 10:49:08 AM UTC 24 Oct 09 10:49:26 AM UTC 24 672390278 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1629046029 Oct 09 10:49:03 AM UTC 24 Oct 09 10:49:26 AM UTC 24 540930419 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.551356535 Oct 09 10:49:09 AM UTC 24 Oct 09 10:49:28 AM UTC 24 702863654 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.4055924244 Oct 09 10:49:23 AM UTC 24 Oct 09 10:49:29 AM UTC 24 657364978 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.542913476 Oct 09 10:49:27 AM UTC 24 Oct 09 10:49:30 AM UTC 24 86039272 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.580567936 Oct 09 10:49:20 AM UTC 24 Oct 09 10:49:33 AM UTC 24 506643595 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2413173324 Oct 09 10:49:27 AM UTC 24 Oct 09 10:49:33 AM UTC 24 244650190 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2442883005 Oct 09 10:48:53 AM UTC 24 Oct 09 10:49:34 AM UTC 24 800507345 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2447965838 Oct 09 10:49:25 AM UTC 24 Oct 09 10:49:35 AM UTC 24 465572845 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.260292495 Oct 09 10:48:59 AM UTC 24 Oct 09 10:49:35 AM UTC 24 286690950 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.141126341 Oct 09 10:48:41 AM UTC 24 Oct 09 10:49:36 AM UTC 24 1625202782 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.3680075438 Oct 09 10:49:21 AM UTC 24 Oct 09 10:49:36 AM UTC 24 1442985613 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.548671895 Oct 09 10:49:36 AM UTC 24 Oct 09 10:49:38 AM UTC 24 17949368 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1896391351 Oct 09 10:49:36 AM UTC 24 Oct 09 10:49:39 AM UTC 24 117690256 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.2715542564 Oct 09 10:49:36 AM UTC 24 Oct 09 10:49:39 AM UTC 24 223475364 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2141982111 Oct 09 10:49:05 AM UTC 24 Oct 09 10:49:43 AM UTC 24 3175737033 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.827161694 Oct 09 10:49:18 AM UTC 24 Oct 09 10:49:44 AM UTC 24 229351510 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2474467883 Oct 09 10:49:12 AM UTC 24 Oct 09 10:49:44 AM UTC 24 544411514 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3692326982 Oct 09 10:48:42 AM UTC 24 Oct 09 10:49:44 AM UTC 24 2167714706 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.2443464965 Oct 09 10:49:20 AM UTC 24 Oct 09 10:49:46 AM UTC 24 1738229134 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.904054952 Oct 09 10:49:30 AM UTC 24 Oct 09 10:49:47 AM UTC 24 449863433 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.3535453738 Oct 09 10:49:39 AM UTC 24 Oct 09 10:49:47 AM UTC 24 96911456 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1197136092 Oct 09 10:49:45 AM UTC 24 Oct 09 10:49:48 AM UTC 24 39322446 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.977270461 Oct 09 10:49:40 AM UTC 24 Oct 09 10:49:49 AM UTC 24 454222889 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.138366654 Oct 09 10:49:29 AM UTC 24 Oct 09 10:49:50 AM UTC 24 938124763 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.2782312674 Oct 09 10:49:40 AM UTC 24 Oct 09 10:49:51 AM UTC 24 687207174 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1057394138 Oct 09 10:49:03 AM UTC 24 Oct 09 10:49:51 AM UTC 24 1667509140 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1464181659 Oct 09 10:49:37 AM UTC 24 Oct 09 10:49:51 AM UTC 24 118697908 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1813139018 Oct 09 10:49:31 AM UTC 24 Oct 09 10:49:52 AM UTC 24 362278539 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.311149090 Oct 09 10:49:48 AM UTC 24 Oct 09 10:49:53 AM UTC 24 85688063 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.1419076954 Oct 09 10:49:25 AM UTC 24 Oct 09 10:49:53 AM UTC 24 1408543739 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.922008123 Oct 09 10:49:45 AM UTC 24 Oct 09 10:49:55 AM UTC 24 1190544081 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.153591818 Oct 09 10:49:25 AM UTC 24 Oct 09 10:49:56 AM UTC 24 2781397685 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3639570917 Oct 09 10:49:53 AM UTC 24 Oct 09 10:49:56 AM UTC 24 29024786 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1114242433 Oct 09 10:49:54 AM UTC 24 Oct 09 10:49:57 AM UTC 24 14439137 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2729267072 Oct 09 10:49:47 AM UTC 24 Oct 09 10:49:58 AM UTC 24 392787500 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.3885028502 Oct 09 10:49:30 AM UTC 24 Oct 09 10:49:58 AM UTC 24 1901278812 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.1835775448 Oct 09 10:49:53 AM UTC 24 Oct 09 10:49:58 AM UTC 24 238313793 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3556290601 Oct 09 10:49:57 AM UTC 24 Oct 09 10:50:01 AM UTC 24 29350990 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1300687670 Oct 09 10:49:44 AM UTC 24 Oct 09 10:50:02 AM UTC 24 1975947055 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3720585534 Oct 09 10:49:59 AM UTC 24 Oct 09 10:50:02 AM UTC 24 14673691 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.1204068490 Oct 09 10:49:48 AM UTC 24 Oct 09 10:50:02 AM UTC 24 329415902 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3885529553 Oct 09 10:49:50 AM UTC 24 Oct 09 10:50:03 AM UTC 24 1004516564 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.14060642 Oct 09 10:49:49 AM UTC 24 Oct 09 10:50:04 AM UTC 24 1342014999 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.438141269 Oct 09 10:49:57 AM UTC 24 Oct 09 10:50:04 AM UTC 24 82720756 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.1688588687 Oct 09 10:50:04 AM UTC 24 Oct 09 10:50:07 AM UTC 24 170881123 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.544714576 Oct 09 10:50:03 AM UTC 24 Oct 09 10:50:08 AM UTC 24 462177091 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.578705683 Oct 09 10:49:49 AM UTC 24 Oct 09 10:50:12 AM UTC 24 973270643 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2682002541 Oct 09 10:49:37 AM UTC 24 Oct 09 10:50:12 AM UTC 24 577918155 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.4235005778 Oct 09 10:49:45 AM UTC 24 Oct 09 10:50:13 AM UTC 24 498801485 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.476872221 Oct 09 10:49:35 AM UTC 24 Oct 09 10:50:15 AM UTC 24 753391613 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.1083488388 Oct 09 10:50:14 AM UTC 24 Oct 09 10:50:16 AM UTC 24 20559496 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3461262963 Oct 09 10:49:58 AM UTC 24 Oct 09 10:50:16 AM UTC 24 1311282277 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.1967134867 Oct 09 10:50:00 AM UTC 24 Oct 09 10:50:17 AM UTC 24 963551482 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2027504582 Oct 09 10:50:14 AM UTC 24 Oct 09 10:50:18 AM UTC 24 40822503 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.4096100666 Oct 09 10:49:59 AM UTC 24 Oct 09 10:50:18 AM UTC 24 1679807616 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1354411537 Oct 09 10:49:52 AM UTC 24 Oct 09 10:50:18 AM UTC 24 3411948349 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1849610133 Oct 09 10:50:16 AM UTC 24 Oct 09 10:50:18 AM UTC 24 21869190 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3490878526 Oct 09 10:50:05 AM UTC 24 Oct 09 10:50:20 AM UTC 24 569758398 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3251492337 Oct 09 10:49:59 AM UTC 24 Oct 09 10:50:21 AM UTC 24 1962356072 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2430464469 Oct 09 10:49:11 AM UTC 24 Oct 09 10:50:21 AM UTC 24 1466863267 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.802194221 Oct 09 10:50:20 AM UTC 24 Oct 09 10:50:22 AM UTC 24 10907737 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.363849437 Oct 09 10:49:48 AM UTC 24 Oct 09 10:50:22 AM UTC 24 4305518926 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3766812237 Oct 09 10:50:19 AM UTC 24 Oct 09 10:50:22 AM UTC 24 39405189 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.1414268212 Oct 09 10:50:17 AM UTC 24 Oct 09 10:50:23 AM UTC 24 122456820 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1969689704 Oct 09 10:50:02 AM UTC 24 Oct 09 10:50:24 AM UTC 24 508843469 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2733347408 Oct 09 10:50:08 AM UTC 24 Oct 09 10:50:25 AM UTC 24 702830763 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.218715972 Oct 09 10:50:05 AM UTC 24 Oct 09 10:50:25 AM UTC 24 596268548 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.547803365 Oct 09 10:50:08 AM UTC 24 Oct 09 10:50:26 AM UTC 24 305890576 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.4289099138 Oct 09 10:50:08 AM UTC 24 Oct 09 10:50:26 AM UTC 24 373514252 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.476520274 Oct 09 10:50:21 AM UTC 24 Oct 09 10:50:26 AM UTC 24 95963383 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1810283620 Oct 09 10:49:56 AM UTC 24 Oct 09 10:50:27 AM UTC 24 182253929 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1460461570 Oct 09 10:50:28 AM UTC 24 Oct 09 10:50:31 AM UTC 24 20416492 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1181274691 Oct 09 10:50:19 AM UTC 24 Oct 09 10:50:31 AM UTC 24 264150940 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.3030482284 Oct 09 10:50:19 AM UTC 24 Oct 09 10:50:33 AM UTC 24 1334457603 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.1508509285 Oct 09 10:49:52 AM UTC 24 Oct 09 10:50:33 AM UTC 24 819347256 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1611802112 Oct 09 10:50:32 AM UTC 24 Oct 09 10:50:35 AM UTC 24 30076643 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3228389133 Oct 09 10:50:24 AM UTC 24 Oct 09 10:50:36 AM UTC 24 1446601252 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1459104763 Oct 09 10:50:32 AM UTC 24 Oct 09 10:50:37 AM UTC 24 195829717 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3695167946 Oct 09 10:50:26 AM UTC 24 Oct 09 10:50:40 AM UTC 24 1337659951 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3949313593 Oct 09 10:50:19 AM UTC 24 Oct 09 10:50:40 AM UTC 24 410344237 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3145488434 Oct 09 10:50:35 AM UTC 24 Oct 09 10:50:40 AM UTC 24 338245252 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3456020942 Oct 09 10:49:24 AM UTC 24 Oct 09 10:50:41 AM UTC 24 14393320182 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2324830607 Oct 09 10:50:41 AM UTC 24 Oct 09 10:50:43 AM UTC 24 34738163 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.86310921 Oct 09 10:50:25 AM UTC 24 Oct 09 10:50:43 AM UTC 24 8829506510 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2694543147 Oct 09 10:50:01 AM UTC 24 Oct 09 10:50:44 AM UTC 24 1106424127 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2039609719 Oct 09 10:49:45 AM UTC 24 Oct 09 10:50:44 AM UTC 24 2369774220 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1776810274 Oct 09 10:50:17 AM UTC 24 Oct 09 10:50:44 AM UTC 24 364512583 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.3319529995 Oct 09 10:50:26 AM UTC 24 Oct 09 10:50:44 AM UTC 24 6323954069 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1592239527 Oct 09 10:50:24 AM UTC 24 Oct 09 10:50:44 AM UTC 24 1561347660 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3882250157 Oct 09 10:50:22 AM UTC 24 Oct 09 10:50:45 AM UTC 24 349129946 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.2739044119 Oct 09 10:50:04 AM UTC 24 Oct 09 10:50:45 AM UTC 24 4171214843 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3086676261 Oct 09 10:50:24 AM UTC 24 Oct 09 10:50:46 AM UTC 24 7672315431 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3117848812 Oct 09 10:50:33 AM UTC 24 Oct 09 10:50:46 AM UTC 24 102940303 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1069404152 Oct 09 10:50:37 AM UTC 24 Oct 09 10:50:48 AM UTC 24 1034303279 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.4074574072 Oct 09 10:50:38 AM UTC 24 Oct 09 10:50:49 AM UTC 24 180726240 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2297870150 Oct 09 10:50:50 AM UTC 24 Oct 09 10:50:54 AM UTC 24 24692825 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1257643119 Oct 09 10:50:41 AM UTC 24 Oct 09 10:50:51 AM UTC 24 6930759325 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3492483373 Oct 09 10:50:26 AM UTC 24 Oct 09 10:50:51 AM UTC 24 3010695272 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.1676884348 Oct 09 10:50:49 AM UTC 24 Oct 09 10:50:51 AM UTC 24 13936092 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3548811776 Oct 09 10:50:45 AM UTC 24 Oct 09 10:50:52 AM UTC 24 568969668 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1013788449 Oct 09 10:48:23 AM UTC 24 Oct 09 10:50:52 AM UTC 24 7207618483 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3856988564 Oct 09 10:50:51 AM UTC 24 Oct 09 10:50:54 AM UTC 24 17538343 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1711009462 Oct 09 10:50:53 AM UTC 24 Oct 09 10:50:57 AM UTC 24 257113565 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.2475385543 Oct 09 10:50:41 AM UTC 24 Oct 09 10:50:57 AM UTC 24 5447064541 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.432383257 Oct 09 10:50:56 AM UTC 24 Oct 09 10:50:59 AM UTC 24 41563517 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2951240318 Oct 09 10:50:24 AM UTC 24 Oct 09 10:50:59 AM UTC 24 6129469224 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1416690330 Oct 09 10:50:45 AM UTC 24 Oct 09 10:50:59 AM UTC 24 1670373006 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.4132591629 Oct 09 10:50:45 AM UTC 24 Oct 09 10:50:59 AM UTC 24 2936237738 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1270547271 Oct 09 10:50:47 AM UTC 24 Oct 09 10:51:01 AM UTC 24 1028968161 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2222455388 Oct 09 10:50:13 AM UTC 24 Oct 09 10:51:01 AM UTC 24 1638772314 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.642783905 Oct 09 10:50:45 AM UTC 24 Oct 09 10:51:01 AM UTC 24 1732025871 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1420532299 Oct 09 10:50:47 AM UTC 24 Oct 09 10:51:02 AM UTC 24 914972617 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3812367220 Oct 09 10:50:53 AM UTC 24 Oct 09 10:51:03 AM UTC 24 303332911 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1517662501 Oct 09 10:50:58 AM UTC 24 Oct 09 10:51:03 AM UTC 24 235538363 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.3167955150 Oct 09 10:50:45 AM UTC 24 Oct 09 10:51:03 AM UTC 24 1851223208 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3043103729 Oct 09 10:50:54 AM UTC 24 Oct 09 10:51:04 AM UTC 24 1396211113 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.909592180 Oct 09 10:50:33 AM UTC 24 Oct 09 10:51:04 AM UTC 24 1122516981 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.454458494 Oct 09 10:51:01 AM UTC 24 Oct 09 10:51:06 AM UTC 24 428593669 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.1862877379 Oct 09 10:50:47 AM UTC 24 Oct 09 10:51:06 AM UTC 24 437429485 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2658052127 Oct 09 10:50:55 AM UTC 24 Oct 09 10:51:07 AM UTC 24 205138834 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.142836392 Oct 09 10:51:05 AM UTC 24 Oct 09 10:51:08 AM UTC 24 50718373 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.4056518088 Oct 09 10:51:02 AM UTC 24 Oct 09 10:51:08 AM UTC 24 253421549 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1008091556 Oct 09 10:51:07 AM UTC 24 Oct 09 10:51:09 AM UTC 24 22291405 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1377862494 Oct 09 10:51:00 AM UTC 24 Oct 09 10:51:10 AM UTC 24 349077523 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3528594742 Oct 09 10:51:05 AM UTC 24 Oct 09 10:51:12 AM UTC 24 576711176 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.4064042211 Oct 09 10:51:12 AM UTC 24 Oct 09 10:51:14 AM UTC 24 20813538 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1505640545 Oct 09 10:50:55 AM UTC 24 Oct 09 10:51:15 AM UTC 24 1395967083 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.976370701 Oct 09 10:50:52 AM UTC 24 Oct 09 10:51:16 AM UTC 24 726968621 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.284564391 Oct 09 10:51:09 AM UTC 24 Oct 09 10:51:17 AM UTC 24 282255858 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.716008535 Oct 09 10:51:04 AM UTC 24 Oct 09 10:51:17 AM UTC 24 281710687 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.843954593 Oct 09 10:51:04 AM UTC 24 Oct 09 10:51:18 AM UTC 24 483114018 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2317370759 Oct 09 10:51:15 AM UTC 24 Oct 09 10:51:19 AM UTC 24 432391520 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.690568867 Oct 09 10:51:00 AM UTC 24 Oct 09 10:51:20 AM UTC 24 2183203072 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3852527268 Oct 09 10:50:45 AM UTC 24 Oct 09 10:51:22 AM UTC 24 6447655177 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.671622362 Oct 09 10:51:08 AM UTC 24 Oct 09 10:51:23 AM UTC 24 322863999 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2749001105 Oct 09 10:51:10 AM UTC 24 Oct 09 10:51:24 AM UTC 24 5189281518 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.154066144 Oct 09 10:49:52 AM UTC 24 Oct 09 10:51:25 AM UTC 24 11051621703 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.467159300 Oct 09 10:51:18 AM UTC 24 Oct 09 10:51:26 AM UTC 24 6362886184 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3528421510 Oct 09 10:50:28 AM UTC 24 Oct 09 10:51:28 AM UTC 24 1547248596 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2761736208 Oct 09 10:51:09 AM UTC 24 Oct 09 10:51:29 AM UTC 24 1159107636 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.1172087314 Oct 09 10:51:26 AM UTC 24 Oct 09 10:51:29 AM UTC 24 33340306 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3525755615 Oct 09 10:51:18 AM UTC 24 Oct 09 10:51:29 AM UTC 24 264841063 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2815677005 Oct 09 10:51:13 AM UTC 24 Oct 09 10:51:30 AM UTC 24 425887830 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3342574610 Oct 09 10:50:45 AM UTC 24 Oct 09 10:51:30 AM UTC 24 2466138291 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2412054892 Oct 09 10:51:29 AM UTC 24 Oct 09 10:51:31 AM UTC 24 99327265 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3998436319 Oct 09 10:51:21 AM UTC 24 Oct 09 10:51:32 AM UTC 24 366052827 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2805880656 Oct 09 10:51:02 AM UTC 24 Oct 09 10:51:32 AM UTC 24 2198292767 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2310447961 Oct 09 10:51:27 AM UTC 24 Oct 09 10:51:34 AM UTC 24 59331743 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3281918381 Oct 09 10:51:02 AM UTC 24 Oct 09 10:51:36 AM UTC 24 401575536 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.1391673932 Oct 09 10:51:08 AM UTC 24 Oct 09 10:51:36 AM UTC 24 166226986 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1656198117 Oct 09 10:50:48 AM UTC 24 Oct 09 10:51:37 AM UTC 24 2739967017 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1756294793 Oct 09 10:51:30 AM UTC 24 Oct 09 10:51:38 AM UTC 24 180888382 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.123658314 Oct 09 10:51:12 AM UTC 24 Oct 09 10:51:38 AM UTC 24 648440302 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3504854495 Oct 09 10:51:20 AM UTC 24 Oct 09 10:51:40 AM UTC 24 1735874960 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2813609632 Oct 09 10:51:30 AM UTC 24 Oct 09 10:51:41 AM UTC 24 211290400 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3327595762 Oct 09 10:51:23 AM UTC 24 Oct 09 10:51:42 AM UTC 24 450857839 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3094094184 Oct 09 10:50:42 AM UTC 24 Oct 09 10:51:43 AM UTC 24 1780641231 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1453419643 Oct 09 10:51:33 AM UTC 24 Oct 09 10:51:43 AM UTC 24 187520216 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.3051651491 Oct 09 10:51:31 AM UTC 24 Oct 09 10:51:45 AM UTC 24 897411604 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.144035027 Oct 09 10:51:37 AM UTC 24 Oct 09 10:51:45 AM UTC 24 556391206 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.1723131638 Oct 09 10:51:30 AM UTC 24 Oct 09 10:51:54 AM UTC 24 335049960 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.1220931827 Oct 09 10:51:42 AM UTC 24 Oct 09 10:51:46 AM UTC 24 14300596 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3224127445 Oct 09 10:51:00 AM UTC 24 Oct 09 10:51:46 AM UTC 24 1634999072 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1628352043 Oct 09 10:50:58 AM UTC 24 Oct 09 10:51:46 AM UTC 24 2655908378 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3718648036 Oct 09 10:51:44 AM UTC 24 Oct 09 10:51:46 AM UTC 24 46565976 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1987958146 Oct 09 10:51:15 AM UTC 24 Oct 09 10:51:47 AM UTC 24 4701400284 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.809079427 Oct 09 10:51:18 AM UTC 24 Oct 09 10:51:47 AM UTC 24 5634817962 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.1812189925 Oct 09 10:49:33 AM UTC 24 Oct 09 10:51:48 AM UTC 24 30701686393 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.266072918 Oct 09 10:51:44 AM UTC 24 Oct 09 10:51:49 AM UTC 24 1258071405 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1573921965 Oct 09 10:50:22 AM UTC 24 Oct 09 10:51:50 AM UTC 24 19513633568 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.3049403169 Oct 09 10:50:28 AM UTC 24 Oct 09 10:51:50 AM UTC 24 8662838358 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.4121117546 Oct 09 10:51:31 AM UTC 24 Oct 09 10:51:50 AM UTC 24 538030413 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1827051979 Oct 09 10:51:46 AM UTC 24 Oct 09 10:51:51 AM UTC 24 22407318 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.601231667 Oct 09 10:51:35 AM UTC 24 Oct 09 10:51:53 AM UTC 24 1311775509 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.812063058 Oct 09 10:51:48 AM UTC 24 Oct 09 10:51:54 AM UTC 24 269868662 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2100791143 Oct 09 10:51:50 AM UTC 24 Oct 09 10:51:56 AM UTC 24 952397279 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.4201935938 Oct 09 10:51:39 AM UTC 24 Oct 09 10:51:56 AM UTC 24 1027106658 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1020349376 Oct 09 10:51:34 AM UTC 24 Oct 09 10:51:57 AM UTC 24 1131672064 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2289918688 Oct 09 10:51:55 AM UTC 24 Oct 09 10:51:58 AM UTC 24 92406073 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.918212540 Oct 09 10:51:55 AM UTC 24 Oct 09 10:51:58 AM UTC 24 13842261 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.4071353984 Oct 09 10:51:55 AM UTC 24 Oct 09 10:51:58 AM UTC 24 27279269 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.230413179 Oct 09 10:52:41 AM UTC 24 Oct 09 10:52:56 AM UTC 24 2770399913 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1543852565 Oct 09 10:51:19 AM UTC 24 Oct 09 10:52:00 AM UTC 24 4236837153 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.605006515 Oct 09 10:51:39 AM UTC 24 Oct 09 10:52:00 AM UTC 24 307288619 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.1273565358 Oct 09 10:51:48 AM UTC 24 Oct 09 10:52:01 AM UTC 24 317374108 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.3823340433 Oct 09 10:51:48 AM UTC 24 Oct 09 10:52:01 AM UTC 24 1128746642 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.4164941839 Oct 09 10:51:39 AM UTC 24 Oct 09 10:52:03 AM UTC 24 643489302 ps
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