Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63462424

1

T1

1559

T2

1402

T3

5293

auto[1]

1104193

1

T2

99

T4

297

T16

6143

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63461687

1

T1

1559

T2

1501

T3

5293

auto[1]

1104930

1

T4

792

T16

7097

T20

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5518186	1			T1	80		T2	208		T3	1341
auto[IdleSt]	17630043	1			T1	58		T2	1001		T3	1337
auto[ClkMuxSt]	29949	1			T1	1		T2	1		T3	13
auto[CntIncrSt]	29717	1			T1	1		T2	1		T3	13
auto[CntProgSt]	1285108	1			T1	2		T2	68		T3	26
auto[TransCheckSt]	23626	1			T1	1		T3	13		T14	1
auto[TokenHashSt]	16888845	1			T1	679		T3	1495		T14	19
auto[FlashRmaSt]	29680	1			T3	13		T15	16		T16	71
auto[TokenCheck0St]	10404	1			T3	13		T15	16		T16	15
auto[TokenCheck1St]	7332	1			T3	13		T15	16		T16	14
auto[TransProgSt]	277596	1			T3	26		T15	32		T16	53
auto[PostTransSt]	9976829	1			T1	737		T2	75		T3	970
auto[ScrapSt]	234929	1			T3	20		T15	85		T16	12
auto[EscalateSt]	4827856	1			T2	147		T4	1467		T16	9003
auto[InvalidSt]	7795228	1			T20	243		T23	1079		T29	507

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1289	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7795228	1			T20	243		T23	1079		T29	507
EscalateSt	4827856	1			T2	147		T4	1467		T16	9003
ScrapSt	234929	1			T3	20		T15	85		T16	12
PostTransSt	9976829	1			T1	737		T2	75		T3	970
TransProgSt	277596	1			T3	26		T15	32		T16	53
TokenCheck1St	7332	1			T3	13		T15	16		T16	14
TokenCheck0St	10404	1			T3	13		T15	16		T16	15
FlashRmaSt	29680	1			T3	13		T15	16		T16	71
TokenHashSt	16888845	1			T1	679		T3	1495		T14	19
TransCheckSt	23626	1			T1	1		T3	13		T14	1
CntProgSt	1285108	1			T1	2		T2	68		T3	26
CntIncrSt	29717	1			T1	1		T2	1		T3	13
ClkMuxSt	29949	1			T1	1		T2	1		T3	13
IdleSt	17630043	1			T1	58		T2	1001		T3	1337
ResetSt	5518186	1			T1	80		T2	208		T3	1341
arcs[ResetSt=>IdleSt]	42546	1			T1	1		T2	2		T3	14
arcs[IdleSt=>ScrapSt]	236	1			T3	1		T15	3		T16	3
arcs[IdleSt=>ClkMuxSt]	29763	1			T1	1		T2	1		T3	13
arcs[ClkMuxSt=>CntIncrSt]	29717	1			T1	1		T2	1		T3	13
arcs[CntIncrSt=>PostTransSt]	1405	1			T21	8		T31	10		T32	9
arcs[CntIncrSt=>CntProgSt]	28245	1			T1	1		T2	1		T3	13
arcs[CntProgSt=>PostTransSt]	3550	1			T2	1		T4	11		T21	8
arcs[CntProgSt=>TransCheckSt]	23626	1			T1	1		T3	13		T14	1
arcs[TransCheckSt=>PostTransSt]	3312	1			T21	7		T22	38		T48	25
arcs[TransCheckSt=>TokenHashSt]	20211	1			T1	1		T3	13		T14	1
arcs[TokenHashSt=>PostTransSt]	8983	1			T1	1		T14	1		T21	19
arcs[TokenHashSt=>FlashRmaSt]	10437	1			T3	13		T15	16		T16	15
arcs[FlashRmaSt=>TokenCheck0St]	10404	1			T3	13		T15	16		T16	15
arcs[TokenCheck0St=>PostTransSt]	3007	1			T21	7		T22	20		T48	13
arcs[TokenCheck0St=>TokenCheck1St]	7332	1			T3	13		T15	16		T16	14
arcs[TokenCheck1St=>PostTransSt]	600	1			T22	17		T48	7		T47	1
arcs[TransProgSt=>PostTransSt]	5914	1			T3	13		T15	16		T20	6
arcs[IdleSt=>EscalateSt]	139	1			T63	5		T64	4		T65	1
arcs[ClkMuxSt=>EscalateSt]	46	1			T63	1		T64	1		T65	1
arcs[CntIncrSt=>EscalateSt]	67	1			T16	1		T63	1		T64	2
arcs[CntProgSt=>EscalateSt]	1069	1			T16	27		T63	10		T64	21
arcs[TransCheckSt=>EscalateSt]	103	1			T63	7		T65	3		T70	1
arcs[TokenHashSt=>EscalateSt]	791	1			T16	9		T63	33		T64	3
arcs[FlashRmaSt=>EscalateSt]	33	1			T63	1		T64	1		T66	1
arcs[TokenCheck0St=>EscalateSt]	65	1			T16	1		T63	1		T64	1
arcs[TokenCheck1St=>EscalateSt]	35	1			T63	1		T64	1		T65	1
arcs[TransProgSt=>EscalateSt]	783	1			T16	14		T63	5		T64	16
arcs[PostTransSt=>EscalateSt]	3879	1			T2	1		T4	11		T21	8
arcs[InvalidSt=>EscalateSt]	9297	1			T20	3		T23	6		T29	7

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5518018	1			T1	80		T2	208		T3	1341
auto[0]	auto[IdleSt]	17629957	1			T1	58		T2	1001		T3	1337
auto[0]	auto[ClkMuxSt]	29913	1			T1	1		T2	1		T3	13
auto[0]	auto[CntIncrSt]	29677	1			T1	1		T2	1		T3	13
auto[0]	auto[CntProgSt]	1284378	1			T1	2		T2	68		T3	26
auto[0]	auto[TransCheckSt]	23561	1			T1	1		T3	13		T14	1
auto[0]	auto[TokenHashSt]	16888309	1			T1	679		T3	1495		T14	19
auto[0]	auto[FlashRmaSt]	29652	1			T3	13		T15	16		T16	71
auto[0]	auto[TokenCheck0St]	10356	1			T3	13		T15	16		T16	15
auto[0]	auto[TokenCheck1St]	7307	1			T3	13		T15	16		T16	14
auto[0]	auto[TransProgSt]	277068	1			T3	26		T15	32		T16	44
auto[0]	auto[PostTransSt]	9974823	1			T1	737		T2	74		T3	970
auto[0]	auto[ScrapSt]	234884	1			T3	20		T15	85		T16	10
auto[0]	auto[EscalateSt]	3732593	1			T2	49		T4	1173		T16	2899
auto[0]	auto[InvalidSt]	7790639	1			T20	242		T23	1076		T29	503
auto[1]	auto[ResetSt]	168	1			T16	3		T63	7		T64	2
auto[1]	auto[IdleSt]	86	1			T63	5		T64	4		T70	1
auto[1]	auto[ClkMuxSt]	36	1			T63	1		T65	1		T70	1
auto[1]	auto[CntIncrSt]	40	1			T16	1		T63	1		T64	2
auto[1]	auto[CntProgSt]	730	1			T16	18		T63	4		T64	14
auto[1]	auto[TransCheckSt]	65	1			T63	6		T65	2		T66	3
auto[1]	auto[TokenHashSt]	536	1			T16	6		T63	24		T64	2
auto[1]	auto[FlashRmaSt]	28	1			T64	1		T66	1		T238	1
auto[1]	auto[TokenCheck0St]	48	1			T63	1		T65	3		T70	1
auto[1]	auto[TokenCheck1St]	25	1			T63	1		T64	1		T67	1
auto[1]	auto[TransProgSt]	528	1			T16	9		T63	4		T64	12
auto[1]	auto[PostTransSt]	2006	1			T2	1		T4	3		T21	5
auto[1]	auto[ScrapSt]	45	1			T16	2		T63	1		T67	1
auto[1]	auto[EscalateSt]	1095263	1			T2	98		T4	294		T16	6104
auto[1]	auto[InvalidSt]	4589	1			T20	1		T23	3		T29	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5518010	1			T1	80		T2	208		T3	1341
auto[0]	auto[IdleSt]	17629947	1			T1	58		T2	1001		T3	1337
auto[0]	auto[ClkMuxSt]	29923	1			T1	1		T2	1		T3	13
auto[0]	auto[CntIncrSt]	29668	1			T1	1		T2	1		T3	13
auto[0]	auto[CntProgSt]	1284396	1			T1	2		T2	68		T3	26
auto[0]	auto[TransCheckSt]	23556	1			T1	1		T3	13		T14	1
auto[0]	auto[TokenHashSt]	16888323	1			T1	679		T3	1495		T14	19
auto[0]	auto[FlashRmaSt]	29661	1			T3	13		T15	16		T16	71
auto[0]	auto[TokenCheck0St]	10362	1			T3	13		T15	16		T16	14
auto[0]	auto[TokenCheck1St]	7310	1			T3	13		T15	16		T16	14
auto[0]	auto[TransProgSt]	277083	1			T3	26		T15	32		T16	43
auto[0]	auto[PostTransSt]	9974847	1			T1	737		T2	75		T3	970
auto[0]	auto[ScrapSt]	234892	1			T3	20		T15	85		T16	10
auto[0]	auto[EscalateSt]	3731900	1			T2	147		T4	683		T16	1951
auto[0]	auto[InvalidSt]	7790520	1			T20	241		T23	1076		T29	504
auto[1]	auto[ResetSt]	176	1			T16	1		T63	5		T64	2
auto[1]	auto[IdleSt]	96	1			T63	3		T64	1		T65	1
auto[1]	auto[ClkMuxSt]	26	1			T64	1		T238	2		T239	1
auto[1]	auto[CntIncrSt]	49	1			T16	1		T63	1		T64	1
auto[1]	auto[CntProgSt]	712	1			T16	22		T63	9		T64	16
auto[1]	auto[TransCheckSt]	70	1			T63	3		T65	2		T70	1
auto[1]	auto[TokenHashSt]	522	1			T16	8		T63	23		T64	3
auto[1]	auto[FlashRmaSt]	19	1			T63	1		T64	1		T238	1
auto[1]	auto[TokenCheck0St]	42	1			T16	1		T63	1		T64	1
auto[1]	auto[TokenCheck1St]	22	1			T64	1		T65	1		T238	1
auto[1]	auto[TransProgSt]	513	1			T16	10		T63	3		T64	9
auto[1]	auto[PostTransSt]	1982	1			T4	8		T21	3		T7	1
auto[1]	auto[ScrapSt]	37	1			T16	2		T63	1		T240	1
auto[1]	auto[EscalateSt]	1095956	1			T4	784		T16	7052		T20	196
auto[1]	auto[InvalidSt]	4708	1			T20	2		T23	3		T29	3