Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 97.90 95.38 93.40 100.00 98.49 98.76 96.29


Total tests in report: 1005
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.72 65.72 80.98 80.98 45.29 45.29 55.67 55.67 52.38 52.38 80.00 80.00 92.04 92.04 53.71 53.71 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.677866282
75.53 9.80 87.78 6.80 73.20 27.91 69.90 14.23 57.14 4.76 85.59 5.59 93.78 1.74 61.31 7.60 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.2026397463
81.64 6.11 88.80 1.02 82.16 8.96 75.37 5.48 73.81 16.67 89.89 4.30 94.28 0.50 67.14 5.83 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.4166550097
84.60 2.96 95.60 6.80 82.53 0.37 75.63 0.25 78.57 4.76 93.12 3.23 94.28 0.00 72.44 5.30 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.845831837
87.14 2.55 95.65 0.05 82.72 0.18 81.84 6.21 88.10 9.52 93.55 0.43 94.28 0.00 73.85 1.41 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1768810505
88.51 1.37 96.68 1.02 85.86 3.14 82.21 0.36 88.10 0.00 94.84 1.29 95.02 0.75 76.86 3.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2985576390
89.69 1.18 96.93 0.26 87.71 1.85 82.27 0.06 88.10 0.00 95.48 0.65 96.27 1.24 81.10 4.24 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3305372105
90.63 0.94 97.03 0.10 87.71 0.00 82.47 0.20 92.86 4.76 95.91 0.43 96.27 0.00 82.16 1.06 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2606858164
91.54 0.91 97.03 0.00 87.71 0.00 85.87 3.40 92.86 0.00 95.91 0.00 96.27 0.00 85.16 3.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.52187278
92.36 0.81 97.09 0.05 88.35 0.65 86.57 0.70 95.24 2.38 96.34 0.43 96.52 0.25 86.40 1.24 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1430369229
93.07 0.71 97.09 0.00 89.46 1.11 86.73 0.16 97.62 2.38 96.34 0.00 96.77 0.25 87.46 1.06 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1759594957
93.66 0.60 97.14 0.05 91.31 1.85 86.77 0.04 97.62 0.00 96.99 0.65 96.77 0.00 89.05 1.59 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.640097880
94.13 0.47 97.14 0.00 91.31 0.00 89.63 2.85 97.62 0.00 96.99 0.00 97.01 0.25 89.22 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1526537183
94.52 0.39 97.19 0.05 91.31 0.00 90.30 0.68 97.62 0.00 97.42 0.43 97.01 0.00 90.81 1.59 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.845169106
94.89 0.37 97.19 0.00 91.31 0.00 90.30 0.00 100.00 2.38 97.42 0.00 97.01 0.00 90.99 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.2592371536
95.20 0.32 97.19 0.00 91.31 0.00 90.57 0.26 100.00 0.00 97.42 0.00 97.01 0.00 92.93 1.94 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.92686929
95.45 0.24 97.55 0.36 92.24 0.92 90.97 0.40 100.00 0.00 97.42 0.00 97.01 0.00 92.93 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.97629116
95.66 0.21 97.55 0.00 92.24 0.00 90.97 0.00 100.00 0.00 97.42 0.00 98.51 1.49 92.93 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2365519054
95.82 0.16 97.65 0.10 92.24 0.00 91.28 0.30 100.00 0.00 97.63 0.22 98.51 0.00 93.46 0.53 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2383512415
95.98 0.15 97.80 0.15 92.24 0.00 91.41 0.13 100.00 0.00 98.06 0.43 98.51 0.00 93.82 0.35 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.717970447
96.11 0.13 97.80 0.00 92.24 0.00 91.61 0.20 100.00 0.00 98.06 0.00 98.51 0.00 94.52 0.71 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2666003705
96.22 0.11 97.80 0.00 92.24 0.00 92.38 0.77 100.00 0.00 98.06 0.00 98.51 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1508052097
96.32 0.10 97.80 0.00 92.33 0.09 92.80 0.43 100.00 0.00 98.28 0.22 98.51 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.645886352
96.43 0.10 97.80 0.00 92.88 0.55 92.80 0.00 100.00 0.00 98.28 0.00 98.51 0.00 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1775487120
96.52 0.10 97.90 0.10 93.25 0.37 92.80 0.00 100.00 0.00 98.49 0.22 98.51 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.3598058550
96.59 0.07 97.90 0.00 93.72 0.46 92.80 0.00 100.00 0.00 98.49 0.00 98.51 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2929111783
96.65 0.06 97.90 0.00 93.99 0.28 92.80 0.00 100.00 0.00 98.49 0.00 98.51 0.00 94.88 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2836494534
96.71 0.06 97.90 0.00 93.99 0.00 93.21 0.40 100.00 0.00 98.49 0.00 98.51 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.1467651394
96.76 0.05 97.90 0.00 93.99 0.00 93.35 0.14 100.00 0.00 98.49 0.00 98.51 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.976220346
96.79 0.04 97.90 0.00 93.99 0.00 93.35 0.00 100.00 0.00 98.49 0.00 98.76 0.25 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3092256599
96.82 0.03 97.90 0.00 93.99 0.00 93.39 0.04 100.00 0.00 98.49 0.00 98.76 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2503095459
96.85 0.03 97.90 0.00 94.18 0.18 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1784965892
96.88 0.03 97.90 0.00 94.36 0.18 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.831660275
96.90 0.03 97.90 0.00 94.55 0.18 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2525473809
96.93 0.03 97.90 0.00 94.55 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3032649863
96.95 0.03 97.90 0.00 94.55 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.985927240
96.98 0.03 97.90 0.00 94.55 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.436826612
97.00 0.03 97.90 0.00 94.55 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3213050564
97.03 0.03 97.90 0.00 94.55 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.3456870808
97.05 0.03 97.90 0.00 94.55 0.00 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2836744194
97.07 0.01 97.90 0.00 94.64 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2170772731
97.08 0.01 97.90 0.00 94.73 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.429038578
97.09 0.01 97.90 0.00 94.82 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1528828718
97.11 0.01 97.90 0.00 94.92 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3901860626
97.12 0.01 97.90 0.00 95.01 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3201361723
97.13 0.01 97.90 0.00 95.10 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3086051141
97.15 0.01 97.90 0.00 95.19 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.45765449
97.16 0.01 97.90 0.00 95.29 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1574648019
97.17 0.01 97.90 0.00 95.38 0.09 93.39 0.00 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2627847447
97.17 0.01 97.90 0.00 95.38 0.00 93.40 0.01 100.00 0.00 98.49 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1516963185

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3683873056
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3289808486
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2250598527
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2078805221
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2202616975
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3139484306
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1097491069
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.896328514
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.30525429
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4256179672
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2938984797
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3797570610
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3730337296
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.522412083
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2532930146
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4179693258
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.836716402
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3631889468
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.35325191
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2433435254
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1364616722
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.778395332
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.992405055
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1893417972
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1863687346
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1173683906
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1881098764
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1732869117
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.620504736
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.202943398
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1712532444
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3697848820
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3469910251
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1384156479
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1861372407
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1388141402
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1400805314
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Total test records in report: 1005
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3895711824 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:54 PM UTC 24 194881316 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.976220346 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:55 PM UTC 24 65313067 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2613854712 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:55 PM UTC 24 220631186 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.438557846 Oct 12 02:08:53 PM UTC 24 Oct 12 02:08:55 PM UTC 24 41342700 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.97629116 Oct 12 02:08:55 PM UTC 24 Oct 12 02:08:57 PM UTC 24 80027661 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.985927240 Oct 12 02:08:55 PM UTC 24 Oct 12 02:08:57 PM UTC 24 34105994 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3294211054 Oct 12 02:08:55 PM UTC 24 Oct 12 02:08:57 PM UTC 24 16214381 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.802627915 Oct 12 02:08:55 PM UTC 24 Oct 12 02:08:59 PM UTC 24 220740532 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1184549007 Oct 12 02:08:55 PM UTC 24 Oct 12 02:08:59 PM UTC 24 225074444 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.677866282 Oct 12 02:08:52 PM UTC 24 Oct 12 02:09:00 PM UTC 24 273237597 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.386591723 Oct 12 02:08:54 PM UTC 24 Oct 12 02:09:01 PM UTC 24 1807780295 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.2035746959 Oct 12 02:08:52 PM UTC 24 Oct 12 02:09:02 PM UTC 24 612056707 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1194919834 Oct 12 02:08:53 PM UTC 24 Oct 12 02:09:02 PM UTC 24 987087465 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.4166550097 Oct 12 02:08:55 PM UTC 24 Oct 12 02:09:03 PM UTC 24 220129485 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2383512415 Oct 12 02:08:54 PM UTC 24 Oct 12 02:09:04 PM UTC 24 733059709 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2503095459 Oct 12 02:09:02 PM UTC 24 Oct 12 02:09:04 PM UTC 24 64340487 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.344771757 Oct 12 02:09:02 PM UTC 24 Oct 12 02:09:04 PM UTC 24 14053485 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2541636541 Oct 12 02:09:02 PM UTC 24 Oct 12 02:09:05 PM UTC 24 80270084 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2985576390 Oct 12 02:08:58 PM UTC 24 Oct 12 02:09:06 PM UTC 24 1537818088 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.1154332052 Oct 12 02:08:57 PM UTC 24 Oct 12 02:09:06 PM UTC 24 236752197 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.845169106 Oct 12 02:08:54 PM UTC 24 Oct 12 02:09:06 PM UTC 24 1323995446 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.1122687534 Oct 12 02:08:58 PM UTC 24 Oct 12 02:09:07 PM UTC 24 7458439830 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.1477545639 Oct 12 02:08:54 PM UTC 24 Oct 12 02:09:07 PM UTC 24 720232111 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1810183034 Oct 12 02:09:05 PM UTC 24 Oct 12 02:09:07 PM UTC 24 42783361 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3548416043 Oct 12 02:08:55 PM UTC 24 Oct 12 02:09:07 PM UTC 24 387789360 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2829062719 Oct 12 02:09:03 PM UTC 24 Oct 12 02:09:08 PM UTC 24 256520587 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.914643904 Oct 12 02:09:00 PM UTC 24 Oct 12 02:09:08 PM UTC 24 2432293270 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3231532375 Oct 12 02:08:54 PM UTC 24 Oct 12 02:09:08 PM UTC 24 5596379474 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.717970447 Oct 12 02:08:52 PM UTC 24 Oct 12 02:09:09 PM UTC 24 990708401 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2772376903 Oct 12 02:09:05 PM UTC 24 Oct 12 02:09:09 PM UTC 24 222497143 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1430369229 Oct 12 02:09:09 PM UTC 24 Oct 12 02:09:31 PM UTC 24 1430026808 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.153974159 Oct 12 02:09:00 PM UTC 24 Oct 12 02:09:09 PM UTC 24 259167098 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1516963185 Oct 12 02:08:54 PM UTC 24 Oct 12 02:09:10 PM UTC 24 3859083022 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2606858164 Oct 12 02:08:55 PM UTC 24 Oct 12 02:09:10 PM UTC 24 1536005142 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.2026397463 Oct 12 02:08:57 PM UTC 24 Oct 12 02:09:10 PM UTC 24 2035887421 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.317253788 Oct 12 02:09:06 PM UTC 24 Oct 12 02:09:12 PM UTC 24 560445815 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.2959038456 Oct 12 02:08:57 PM UTC 24 Oct 12 02:09:12 PM UTC 24 570962006 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.780376951 Oct 12 02:09:08 PM UTC 24 Oct 12 02:09:13 PM UTC 24 772855840 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.2841589127 Oct 12 02:09:11 PM UTC 24 Oct 12 02:09:14 PM UTC 24 350093077 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3688071093 Oct 12 02:09:11 PM UTC 24 Oct 12 02:09:14 PM UTC 24 34935421 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3836342035 Oct 12 02:08:52 PM UTC 24 Oct 12 02:09:15 PM UTC 24 633361152 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.14850581 Oct 12 02:09:11 PM UTC 24 Oct 12 02:09:15 PM UTC 24 72463983 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.228483344 Oct 12 02:08:53 PM UTC 24 Oct 12 02:09:15 PM UTC 24 2684279538 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3745714220 Oct 12 02:09:05 PM UTC 24 Oct 12 02:09:15 PM UTC 24 275890059 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.845831837 Oct 12 02:08:58 PM UTC 24 Oct 12 02:09:15 PM UTC 24 1045056191 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3213050564 Oct 12 02:09:14 PM UTC 24 Oct 12 02:09:16 PM UTC 24 12433115 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.4267648566 Oct 12 02:08:55 PM UTC 24 Oct 12 02:09:17 PM UTC 24 500208756 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.3928494101 Oct 12 02:09:06 PM UTC 24 Oct 12 02:09:17 PM UTC 24 1678778490 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1353746062 Oct 12 02:09:11 PM UTC 24 Oct 12 02:09:26 PM UTC 24 1362203486 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1835328416 Oct 12 02:09:08 PM UTC 24 Oct 12 02:09:18 PM UTC 24 1797845508 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1962831276 Oct 12 02:09:11 PM UTC 24 Oct 12 02:09:20 PM UTC 24 106728199 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.782602945 Oct 12 02:08:54 PM UTC 24 Oct 12 02:09:20 PM UTC 24 733457780 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.3541199860 Oct 12 02:09:08 PM UTC 24 Oct 12 02:09:21 PM UTC 24 442546916 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1574648019 Oct 12 02:08:55 PM UTC 24 Oct 12 02:09:21 PM UTC 24 3954712886 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1297705619 Oct 12 02:09:09 PM UTC 24 Oct 12 02:09:22 PM UTC 24 287301288 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1898520542 Oct 12 02:09:11 PM UTC 24 Oct 12 02:09:22 PM UTC 24 364345084 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2184391868 Oct 12 02:09:05 PM UTC 24 Oct 12 02:09:22 PM UTC 24 1019231917 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.609253292 Oct 12 02:09:12 PM UTC 24 Oct 12 02:09:23 PM UTC 24 3842202137 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2310914015 Oct 12 02:09:16 PM UTC 24 Oct 12 02:09:23 PM UTC 24 3929029599 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.1900255929 Oct 12 02:09:05 PM UTC 24 Oct 12 02:09:24 PM UTC 24 6468293574 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2222999886 Oct 12 02:09:15 PM UTC 24 Oct 12 02:09:24 PM UTC 24 1107288442 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2576394953 Oct 12 02:08:58 PM UTC 24 Oct 12 02:09:24 PM UTC 24 810684956 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.269516030 Oct 12 02:09:08 PM UTC 24 Oct 12 02:09:24 PM UTC 24 1654767909 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.2823785332 Oct 12 02:09:06 PM UTC 24 Oct 12 02:09:24 PM UTC 24 3083145673 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.4076068716 Oct 12 02:09:22 PM UTC 24 Oct 12 02:09:25 PM UTC 24 19829776 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.1802148609 Oct 12 02:09:22 PM UTC 24 Oct 12 02:09:25 PM UTC 24 50960083 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.45765449 Oct 12 02:08:54 PM UTC 24 Oct 12 02:09:26 PM UTC 24 3374599169 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3062631903 Oct 12 02:09:24 PM UTC 24 Oct 12 02:09:26 PM UTC 24 14742636 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2374345670 Oct 12 02:09:25 PM UTC 24 Oct 12 02:09:30 PM UTC 24 120796472 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1601138990 Oct 12 02:09:24 PM UTC 24 Oct 12 02:09:27 PM UTC 24 64123369 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.3456870808 Oct 12 02:09:25 PM UTC 24 Oct 12 02:09:27 PM UTC 24 18801738 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1999868789 Oct 12 02:09:08 PM UTC 24 Oct 12 02:09:27 PM UTC 24 1433467952 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.1360011642 Oct 12 02:09:16 PM UTC 24 Oct 12 02:09:28 PM UTC 24 1495492695 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3008323652 Oct 12 02:08:55 PM UTC 24 Oct 12 02:09:28 PM UTC 24 1237865590 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3223651203 Oct 12 02:09:18 PM UTC 24 Oct 12 02:09:29 PM UTC 24 557055387 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.1345005135 Oct 12 02:09:16 PM UTC 24 Oct 12 02:09:29 PM UTC 24 256265462 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1478036843 Oct 12 02:09:24 PM UTC 24 Oct 12 02:09:29 PM UTC 24 230561112 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2408203605 Oct 12 02:09:14 PM UTC 24 Oct 12 02:09:29 PM UTC 24 2771553027 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.645886352 Oct 12 02:09:03 PM UTC 24 Oct 12 02:09:30 PM UTC 24 207233259 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2061525721 Oct 12 02:09:16 PM UTC 24 Oct 12 02:09:31 PM UTC 24 2175757480 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.4272588743 Oct 12 02:09:17 PM UTC 24 Oct 12 02:09:32 PM UTC 24 602037592 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2996564891 Oct 12 02:09:25 PM UTC 24 Oct 12 02:09:32 PM UTC 24 237322159 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.1419048512 Oct 12 02:09:27 PM UTC 24 Oct 12 02:09:32 PM UTC 24 114370224 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1741623601 Oct 12 02:09:31 PM UTC 24 Oct 12 02:09:33 PM UTC 24 42771026 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.458767765 Oct 12 02:09:30 PM UTC 24 Oct 12 02:09:33 PM UTC 24 42257769 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1188195688 Oct 12 02:09:30 PM UTC 24 Oct 12 02:09:33 PM UTC 24 61734311 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2271690773 Oct 12 02:09:27 PM UTC 24 Oct 12 02:09:34 PM UTC 24 1361925344 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1389733855 Oct 12 02:09:19 PM UTC 24 Oct 12 02:09:35 PM UTC 24 1623516094 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3884947545 Oct 12 02:09:33 PM UTC 24 Oct 12 02:09:35 PM UTC 24 10798108 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.2528709541 Oct 12 02:09:25 PM UTC 24 Oct 12 02:09:36 PM UTC 24 701894636 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.52187278 Oct 12 02:08:52 PM UTC 24 Oct 12 02:09:37 PM UTC 24 1220764343 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3934386517 Oct 12 02:09:32 PM UTC 24 Oct 12 02:09:37 PM UTC 24 62047764 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3210335945 Oct 12 02:09:29 PM UTC 24 Oct 12 02:09:38 PM UTC 24 6078544624 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.54678396 Oct 12 02:09:31 PM UTC 24 Oct 12 02:09:38 PM UTC 24 193243810 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.1132671958 Oct 12 02:09:35 PM UTC 24 Oct 12 02:09:38 PM UTC 24 254585237 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3249165765 Oct 12 02:08:57 PM UTC 24 Oct 12 02:09:38 PM UTC 24 1162522946 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.751144723 Oct 12 02:09:27 PM UTC 24 Oct 12 02:09:39 PM UTC 24 1229280855 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1757297487 Oct 12 02:09:16 PM UTC 24 Oct 12 02:09:40 PM UTC 24 5716173388 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.1028250571 Oct 12 02:09:38 PM UTC 24 Oct 12 02:09:40 PM UTC 24 13703792 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3545156437 Oct 12 02:09:33 PM UTC 24 Oct 12 02:09:41 PM UTC 24 203071289 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2332185753 Oct 12 02:09:27 PM UTC 24 Oct 12 02:09:41 PM UTC 24 2051406874 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3657918904 Oct 12 02:09:32 PM UTC 24 Oct 12 02:09:41 PM UTC 24 348568150 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1365948796 Oct 12 02:09:29 PM UTC 24 Oct 12 02:09:41 PM UTC 24 1133012184 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1148020207 Oct 12 02:09:35 PM UTC 24 Oct 12 02:09:41 PM UTC 24 191819563 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1704177205 Oct 12 02:09:40 PM UTC 24 Oct 12 02:09:42 PM UTC 24 46347368 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3866182293 Oct 12 02:09:25 PM UTC 24 Oct 12 02:09:42 PM UTC 24 670016318 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.88064777 Oct 12 02:09:32 PM UTC 24 Oct 12 02:09:42 PM UTC 24 278810501 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3944683505 Oct 12 02:09:27 PM UTC 24 Oct 12 02:09:43 PM UTC 24 2814047892 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.292866198 Oct 12 02:09:36 PM UTC 24 Oct 12 02:09:43 PM UTC 24 184667714 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1508052097 Oct 12 02:09:11 PM UTC 24 Oct 12 02:09:43 PM UTC 24 840683271 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1889679507 Oct 12 02:09:02 PM UTC 24 Oct 12 02:09:43 PM UTC 24 1121821614 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1886262653 Oct 12 02:09:40 PM UTC 24 Oct 12 02:09:44 PM UTC 24 38333059 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.198001507 Oct 12 02:09:39 PM UTC 24 Oct 12 02:09:44 PM UTC 24 154821784 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.1756886911 Oct 12 02:09:42 PM UTC 24 Oct 12 02:09:44 PM UTC 24 16701067 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.917010679 Oct 12 02:08:57 PM UTC 24 Oct 12 02:09:44 PM UTC 24 1242116594 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.4221135314 Oct 12 02:09:42 PM UTC 24 Oct 12 02:09:46 PM UTC 24 153487735 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3270089601 Oct 12 02:09:33 PM UTC 24 Oct 12 02:09:47 PM UTC 24 671016180 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.3907631937 Oct 12 02:09:44 PM UTC 24 Oct 12 02:09:48 PM UTC 24 319690842 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1966829142 Oct 12 02:09:27 PM UTC 24 Oct 12 02:09:48 PM UTC 24 2209498053 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.2182068477 Oct 12 02:09:46 PM UTC 24 Oct 12 02:09:48 PM UTC 24 41400441 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.1934747363 Oct 12 02:09:38 PM UTC 24 Oct 12 02:09:49 PM UTC 24 1242515138 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2474498060 Oct 12 02:09:47 PM UTC 24 Oct 12 02:09:49 PM UTC 24 12816387 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.2695288688 Oct 12 02:09:46 PM UTC 24 Oct 12 02:09:51 PM UTC 24 105706550 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.4207264760 Oct 12 02:09:48 PM UTC 24 Oct 12 02:09:52 PM UTC 24 32632382 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.707862996 Oct 12 02:09:24 PM UTC 24 Oct 12 02:09:52 PM UTC 24 888266074 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.1804655680 Oct 12 02:09:41 PM UTC 24 Oct 12 02:09:52 PM UTC 24 1384328180 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.867038021 Oct 12 02:09:45 PM UTC 24 Oct 12 02:09:53 PM UTC 24 546482429 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1426390719 Oct 12 02:09:38 PM UTC 24 Oct 12 02:09:53 PM UTC 24 346604919 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3339504949 Oct 12 02:09:09 PM UTC 24 Oct 12 02:09:53 PM UTC 24 3339463291 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3077027947 Oct 12 02:09:40 PM UTC 24 Oct 12 02:09:53 PM UTC 24 165252232 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2434245529 Oct 12 02:09:51 PM UTC 24 Oct 12 02:09:53 PM UTC 24 34902253 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.917732547 Oct 12 02:09:16 PM UTC 24 Oct 12 02:09:54 PM UTC 24 2188664467 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.118330194 Oct 12 02:09:02 PM UTC 24 Oct 12 02:09:55 PM UTC 24 2950053858 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.4206712282 Oct 12 02:09:44 PM UTC 24 Oct 12 02:09:56 PM UTC 24 2253858248 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.332546937 Oct 12 02:09:22 PM UTC 24 Oct 12 02:09:56 PM UTC 24 220556970 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.3017491465 Oct 12 02:09:41 PM UTC 24 Oct 12 02:09:57 PM UTC 24 312511074 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.387498508 Oct 12 02:09:38 PM UTC 24 Oct 12 02:09:58 PM UTC 24 592116790 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1181081962 Oct 12 02:09:25 PM UTC 24 Oct 12 02:09:58 PM UTC 24 11384488352 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1855520514 Oct 12 02:09:53 PM UTC 24 Oct 12 02:09:58 PM UTC 24 264365932 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2666003705 Oct 12 02:09:48 PM UTC 24 Oct 12 02:10:03 PM UTC 24 102724265 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.2726709292 Oct 12 02:09:50 PM UTC 24 Oct 12 02:10:08 PM UTC 24 1537641313 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2410186661 Oct 12 02:09:52 PM UTC 24 Oct 12 02:09:58 PM UTC 24 188324778 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.1344634260 Oct 12 02:09:30 PM UTC 24 Oct 12 02:09:58 PM UTC 24 917174531 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.240278560 Oct 12 02:09:36 PM UTC 24 Oct 12 02:09:59 PM UTC 24 6176030554 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3249649445 Oct 12 02:09:44 PM UTC 24 Oct 12 02:09:59 PM UTC 24 790394762 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3171110799 Oct 12 02:09:55 PM UTC 24 Oct 12 02:10:00 PM UTC 24 171784444 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3239253706 Oct 12 02:09:42 PM UTC 24 Oct 12 02:10:00 PM UTC 24 492884922 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.4209554547 Oct 12 02:09:44 PM UTC 24 Oct 12 02:10:00 PM UTC 24 393028309 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.2230198818 Oct 12 02:10:02 PM UTC 24 Oct 12 02:10:05 PM UTC 24 453140392 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2143974515 Oct 12 02:09:46 PM UTC 24 Oct 12 02:10:01 PM UTC 24 2663884418 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2945286767 Oct 12 02:09:59 PM UTC 24 Oct 12 02:10:02 PM UTC 24 13106417 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1768810505 Oct 12 02:09:50 PM UTC 24 Oct 12 02:10:02 PM UTC 24 725132003 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.1451577172 Oct 12 02:09:59 PM UTC 24 Oct 12 02:10:02 PM UTC 24 70592221 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1471750134 Oct 12 02:09:31 PM UTC 24 Oct 12 02:10:02 PM UTC 24 1136485991 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4256010182 Oct 12 02:09:51 PM UTC 24 Oct 12 02:10:03 PM UTC 24 1442582427 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2836744194 Oct 12 02:10:02 PM UTC 24 Oct 12 02:10:04 PM UTC 24 21065152 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2731110100 Oct 12 02:09:59 PM UTC 24 Oct 12 02:10:04 PM UTC 24 46751203 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3997663184 Oct 12 02:10:00 PM UTC 24 Oct 12 02:10:05 PM UTC 24 49911148 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.587999308 Oct 12 02:09:56 PM UTC 24 Oct 12 02:10:07 PM UTC 24 4905960735 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.534325661 Oct 12 02:08:53 PM UTC 24 Oct 12 02:10:06 PM UTC 24 14563486463 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3634069206 Oct 12 02:09:44 PM UTC 24 Oct 12 02:10:07 PM UTC 24 5309654582 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.4042900995 Oct 12 02:09:42 PM UTC 24 Oct 12 02:10:07 PM UTC 24 1372917350 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.345900795 Oct 12 02:10:03 PM UTC 24 Oct 12 02:10:07 PM UTC 24 1133387086 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.92686929 Oct 12 02:09:29 PM UTC 24 Oct 12 02:10:07 PM UTC 24 13704165795 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3951962359 Oct 12 02:09:42 PM UTC 24 Oct 12 02:10:08 PM UTC 24 963545315 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.3344903010 Oct 12 02:09:55 PM UTC 24 Oct 12 02:10:08 PM UTC 24 3814532089 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1081701680 Oct 12 02:10:14 PM UTC 24 Oct 12 02:10:40 PM UTC 24 2658611247 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3967787212 Oct 12 02:10:03 PM UTC 24 Oct 12 02:10:09 PM UTC 24 189471355 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1114083706 Oct 12 02:10:07 PM UTC 24 Oct 12 02:10:10 PM UTC 24 15471050 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.2782013224 Oct 12 02:09:59 PM UTC 24 Oct 12 02:10:10 PM UTC 24 88676675 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3440159019 Oct 12 02:10:07 PM UTC 24 Oct 12 02:10:10 PM UTC 24 44932424 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.731879987 Oct 12 02:09:38 PM UTC 24 Oct 12 02:10:11 PM UTC 24 1148641234 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.2728612485 Oct 12 02:10:04 PM UTC 24 Oct 12 02:10:11 PM UTC 24 2382207824 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3892638770 Oct 12 02:10:00 PM UTC 24 Oct 12 02:10:11 PM UTC 24 331481665 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2530252739 Oct 12 02:09:55 PM UTC 24 Oct 12 02:10:12 PM UTC 24 1269099655 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.853693548 Oct 12 02:10:10 PM UTC 24 Oct 12 02:10:13 PM UTC 24 58611835 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.4251096190 Oct 12 02:10:07 PM UTC 24 Oct 12 02:10:13 PM UTC 24 118267180 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1951535541 Oct 12 02:09:55 PM UTC 24 Oct 12 02:10:13 PM UTC 24 336898966 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3947532906 Oct 12 02:10:09 PM UTC 24 Oct 12 02:10:14 PM UTC 24 64740359 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.268282882 Oct 12 02:10:34 PM UTC 24 Oct 12 02:10:43 PM UTC 24 355231017 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.336231893 Oct 12 02:10:09 PM UTC 24 Oct 12 02:10:14 PM UTC 24 225298930 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.1801579535 Oct 12 02:10:10 PM UTC 24 Oct 12 02:10:14 PM UTC 24 232733108 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.965283189 Oct 12 02:09:53 PM UTC 24 Oct 12 02:10:14 PM UTC 24 4853865063 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2165333530 Oct 12 02:09:06 PM UTC 24 Oct 12 02:10:15 PM UTC 24 15099000270 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3540585942 Oct 12 02:10:00 PM UTC 24 Oct 12 02:10:15 PM UTC 24 420109291 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1976154540 Oct 12 02:09:40 PM UTC 24 Oct 12 02:10:16 PM UTC 24 317912579 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.4129246567 Oct 12 02:10:00 PM UTC 24 Oct 12 02:10:16 PM UTC 24 1925824933 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3352490803 Oct 12 02:10:15 PM UTC 24 Oct 12 02:10:17 PM UTC 24 22381627 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.673640995 Oct 12 02:10:06 PM UTC 24 Oct 12 02:10:17 PM UTC 24 553990373 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.418760569 Oct 12 02:10:27 PM UTC 24 Oct 12 02:10:48 PM UTC 24 803556589 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1316455859 Oct 12 02:10:13 PM UTC 24 Oct 12 02:10:18 PM UTC 24 1128515129 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4139614762 Oct 12 02:10:16 PM UTC 24 Oct 12 02:10:18 PM UTC 24 95039681 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1526537183 Oct 12 02:09:09 PM UTC 24 Oct 12 02:10:21 PM UTC 24 1739411926 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2217764341 Oct 12 02:10:16 PM UTC 24 Oct 12 02:10:21 PM UTC 24 71900419 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1398241544 Oct 12 02:09:35 PM UTC 24 Oct 12 02:10:21 PM UTC 24 6569353987 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3799098487 Oct 12 02:10:06 PM UTC 24 Oct 12 02:10:21 PM UTC 24 1216100479 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.140895859 Oct 12 02:10:10 PM UTC 24 Oct 12 02:10:21 PM UTC 24 253343641 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1419129293 Oct 12 02:10:17 PM UTC 24 Oct 12 02:10:21 PM UTC 24 31989536 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.513876325 Oct 12 02:10:12 PM UTC 24 Oct 12 02:10:22 PM UTC 24 552922349 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2398298222 Oct 12 02:10:10 PM UTC 24 Oct 12 02:10:23 PM UTC 24 278460681 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.2012347659 Oct 12 02:10:04 PM UTC 24 Oct 12 02:10:23 PM UTC 24 384052293 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.2663370969 Oct 12 02:10:12 PM UTC 24 Oct 12 02:10:24 PM UTC 24 997698487 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.658299384 Oct 12 02:09:57 PM UTC 24 Oct 12 02:10:24 PM UTC 24 2775462840 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.1467651394 Oct 12 02:09:48 PM UTC 24 Oct 12 02:10:25 PM UTC 24 1220144812 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.57522749 Oct 12 02:10:04 PM UTC 24 Oct 12 02:10:25 PM UTC 24 687834275 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.941842637 Oct 12 02:10:19 PM UTC 24 Oct 12 02:10:25 PM UTC 24 1511245077 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.4266453543 Oct 12 02:10:17 PM UTC 24 Oct 12 02:10:26 PM UTC 24 54348126 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.863684637 Oct 12 02:09:27 PM UTC 24 Oct 12 02:10:26 PM UTC 24 2194860515 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2422631551 Oct 12 02:10:24 PM UTC 24 Oct 12 02:10:26 PM UTC 24 60618124 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.501207172 Oct 12 02:10:22 PM UTC 24 Oct 12 02:10:27 PM UTC 24 71148609 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2710252549 Oct 12 02:10:25 PM UTC 24 Oct 12 02:10:27 PM UTC 24 37287520 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1322970859 Oct 12 02:10:25 PM UTC 24 Oct 12 02:10:29 PM UTC 24 81767507 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.870602642 Oct 12 02:10:32 PM UTC 24 Oct 12 02:10:44 PM UTC 24 869467794 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.2138221971 Oct 12 02:10:03 PM UTC 24 Oct 12 02:10:30 PM UTC 24 1452270727 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3359675385 Oct 12 02:10:14 PM UTC 24 Oct 12 02:10:30 PM UTC 24 6222869982 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.4097420034 Oct 12 02:10:22 PM UTC 24 Oct 12 02:10:30 PM UTC 24 1961618873 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.3541332196 Oct 12 02:10:39 PM UTC 24 Oct 12 02:10:42 PM UTC 24 167082938 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3973422777 Oct 12 02:10:23 PM UTC 24 Oct 12 02:10:31 PM UTC 24 781898384 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3284644613 Oct 12 02:09:59 PM UTC 24 Oct 12 02:10:31 PM UTC 24 307923947 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1257788137 Oct 12 02:10:27 PM UTC 24 Oct 12 02:10:31 PM UTC 24 68851311 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1744011462 Oct 12 02:09:35 PM UTC 24 Oct 12 02:10:31 PM UTC 24 20974101240 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.906194463 Oct 12 02:10:14 PM UTC 24 Oct 12 02:10:31 PM UTC 24 273161685 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.567338787 Oct 12 02:10:19 PM UTC 24 Oct 12 02:10:32 PM UTC 24 452900229 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3904763889 Oct 12 02:09:35 PM UTC 24 Oct 12 02:10:44 PM UTC 24 11167796187 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.791124283 Oct 12 02:10:10 PM UTC 24 Oct 12 02:10:32 PM UTC 24 397918847 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3470036986 Oct 12 02:09:55 PM UTC 24 Oct 12 02:10:32 PM UTC 24 1476522768 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1878547023 Oct 12 02:10:23 PM UTC 24 Oct 12 02:10:32 PM UTC 24 1330776019 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1347548669 Oct 12 02:10:28 PM UTC 24 Oct 12 02:10:35 PM UTC 24 1358379537 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.3739494311 Oct 12 02:10:34 PM UTC 24 Oct 12 02:10:36 PM UTC 24 109090736 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3234581252 Oct 12 02:10:34 PM UTC 24 Oct 12 02:10:36 PM UTC 24 82463292 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2152792878 Oct 12 02:10:27 PM UTC 24 Oct 12 02:10:36 PM UTC 24 235973542 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.307175754 Oct 12 02:10:34 PM UTC 24 Oct 12 02:10:37 PM UTC 24 55077413 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.124176860 Oct 12 02:10:17 PM UTC 24 Oct 12 02:10:37 PM UTC 24 1408062332 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3724732962 Oct 12 02:10:24 PM UTC 24 Oct 12 02:10:37 PM UTC 24 365116871 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2034289819 Oct 12 02:10:27 PM UTC 24 Oct 12 02:10:38 PM UTC 24 91332379 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3068488525 Oct 12 02:10:09 PM UTC 24 Oct 12 02:10:38 PM UTC 24 429268094 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.4274813349 Oct 12 02:10:36 PM UTC 24 Oct 12 02:10:40 PM UTC 24 33396488 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1440884649 Oct 12 02:10:32 PM UTC 24 Oct 12 02:10:44 PM UTC 24 427046260 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3926737309 Oct 12 02:09:07 PM UTC 24 Oct 12 02:10:44 PM UTC 24 14943192731 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.2071462101 Oct 12 02:10:12 PM UTC 24 Oct 12 02:10:44 PM UTC 24 5310261583 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3618820310 Oct 12 02:09:53 PM UTC 24 Oct 12 02:10:45 PM UTC 24 3605830879 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4083691081 Oct 12 02:10:46 PM UTC 24 Oct 12 02:10:48 PM UTC 24 14537995 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2991889438 Oct 12 02:10:45 PM UTC 24 Oct 12 02:10:48 PM UTC 24 35529613 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.2582985433 Oct 12 02:09:53 PM UTC 24 Oct 12 02:10:49 PM UTC 24 7944742459 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3332416375 Oct 12 02:10:13 PM UTC 24 Oct 12 02:10:49 PM UTC 24 5278855088 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.4259958555 Oct 12 02:10:38 PM UTC 24 Oct 12 02:10:49 PM UTC 24 2259638581 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.1767295927 Oct 12 02:10:37 PM UTC 24 Oct 12 02:10:50 PM UTC 24 1322947180 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3875190942 Oct 12 02:10:32 PM UTC 24 Oct 12 02:10:50 PM UTC 24 1637888762 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2029310215 Oct 12 02:10:11 PM UTC 24 Oct 12 02:10:50 PM UTC 24 7843038317 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.2215455098 Oct 12 02:10:32 PM UTC 24 Oct 12 02:10:50 PM UTC 24 1282727162 ps
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