Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.50 97.90 95.56 93.40 95.24 98.28 99.00 96.11


Total tests in report: 998
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.15 67.15 81.13 81.13 52.22 52.22 58.34 58.34 52.38 52.38 81.29 81.29 92.04 92.04 52.65 52.65 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1651263993
79.78 12.63 88.65 7.52 81.05 28.84 73.92 15.58 71.43 19.05 89.25 7.96 93.53 1.49 60.60 7.95 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2705495665
83.38 3.60 95.45 6.80 81.79 0.74 76.13 2.22 76.19 4.76 92.04 2.80 94.03 0.50 68.02 7.42 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.1251855602
85.50 2.12 95.50 0.05 81.79 0.00 76.13 0.00 88.10 11.90 92.26 0.22 94.03 0.00 70.67 2.65 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.278793119
87.55 2.05 95.71 0.20 82.81 1.02 82.63 6.50 88.10 0.00 92.69 0.43 94.03 0.00 76.86 6.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1870665048
89.02 1.47 95.96 0.26 84.57 1.76 86.39 3.76 88.10 0.00 93.98 1.29 94.28 0.25 79.86 3.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4095773324
90.21 1.19 96.17 0.20 86.23 1.66 86.43 0.04 88.10 0.00 94.62 0.65 95.27 1.00 84.63 4.77 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1169213781
91.18 0.98 96.27 0.10 86.97 0.74 87.93 1.50 90.48 2.38 95.27 0.65 95.52 0.25 85.87 1.24 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.3904471187
92.06 0.87 96.27 0.00 88.08 1.11 91.45 3.52 90.48 0.00 95.27 0.00 95.77 0.25 87.10 1.24 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2926186516
92.89 0.83 97.19 0.92 89.56 1.48 91.65 0.20 90.48 0.00 96.13 0.86 96.52 0.75 88.69 1.59 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2559492986
93.34 0.45 97.19 0.00 89.56 0.00 92.07 0.43 90.48 0.00 96.13 0.00 96.77 0.25 91.17 2.47 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3706216495
93.72 0.38 97.19 0.00 89.83 0.28 92.07 0.00 92.86 2.38 96.13 0.00 96.77 0.00 91.17 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.86573029
94.07 0.35 97.29 0.10 89.83 0.00 92.40 0.32 92.86 0.00 96.56 0.43 96.77 0.00 92.76 1.59 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3631758956
94.41 0.34 97.29 0.00 89.83 0.00 92.40 0.00 95.24 2.38 96.56 0.00 96.77 0.00 92.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.2744430337
94.74 0.34 97.29 0.00 90.94 1.11 92.40 0.00 95.24 0.00 96.56 0.00 96.77 0.00 93.99 1.24 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.380317948
94.97 0.23 97.34 0.05 92.05 1.11 92.40 0.00 95.24 0.00 96.99 0.43 96.77 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2127526950
95.18 0.21 97.34 0.00 92.05 0.00 92.40 0.00 95.24 0.00 96.99 0.00 98.26 1.49 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2817251784
95.39 0.21 97.70 0.36 92.98 0.92 92.57 0.17 95.24 0.00 96.99 0.00 98.26 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.803302871
95.54 0.15 97.70 0.00 92.98 0.00 93.01 0.44 95.24 0.00 97.63 0.65 98.26 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.347884002
95.66 0.11 97.80 0.10 92.98 0.00 93.14 0.13 95.24 0.00 97.85 0.22 98.26 0.00 94.35 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1831707344
95.75 0.09 97.80 0.00 93.44 0.46 93.14 0.00 95.24 0.00 97.85 0.00 98.26 0.00 94.52 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2193744090
95.83 0.08 97.80 0.00 93.99 0.55 93.14 0.00 95.24 0.00 97.85 0.00 98.26 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2426239342
95.90 0.07 97.80 0.00 93.99 0.00 93.14 0.00 95.24 0.00 97.85 0.00 98.76 0.50 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1559222241
95.96 0.06 97.80 0.00 93.99 0.00 93.32 0.18 95.24 0.00 97.85 0.00 99.00 0.25 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3467016023
96.02 0.06 97.90 0.10 94.09 0.09 93.32 0.00 95.24 0.00 98.06 0.22 99.00 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3033873938
96.07 0.05 97.90 0.00 94.27 0.18 93.32 0.00 95.24 0.00 98.06 0.00 99.00 0.00 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.487779848
96.12 0.05 97.90 0.00 94.27 0.00 93.32 0.00 95.24 0.00 98.06 0.00 99.00 0.00 95.05 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1203917648
96.16 0.04 97.90 0.00 94.27 0.00 93.40 0.08 95.24 0.00 98.06 0.00 99.00 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.2062519318
96.19 0.03 97.90 0.00 94.27 0.00 93.40 0.00 95.24 0.00 98.28 0.22 99.00 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1092702222
96.22 0.03 97.90 0.00 94.45 0.18 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.419100649
96.24 0.03 97.90 0.00 94.64 0.18 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1238238032
96.27 0.03 97.90 0.00 94.64 0.00 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2992840379
96.29 0.03 97.90 0.00 94.64 0.00 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.121371309
96.32 0.03 97.90 0.00 94.64 0.00 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.406697273
96.34 0.03 97.90 0.00 94.64 0.00 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1621379292
96.37 0.03 97.90 0.00 94.64 0.00 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.681887266
96.38 0.01 97.90 0.00 94.73 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3742311430
96.39 0.01 97.90 0.00 94.82 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.19062967
96.41 0.01 97.90 0.00 94.92 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1743198867
96.42 0.01 97.90 0.00 95.01 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1375951119
96.43 0.01 97.90 0.00 95.10 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4106027177
96.45 0.01 97.90 0.00 95.19 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1663381100
96.46 0.01 97.90 0.00 95.29 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.280799051
96.47 0.01 97.90 0.00 95.38 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2550114914
96.49 0.01 97.90 0.00 95.47 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3901582031
96.50 0.01 97.90 0.00 95.56 0.09 93.40 0.00 95.24 0.00 98.28 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.3149496623

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3368623095
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1330931880
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.856743829
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1104576488
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.453982440
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1743114413
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1968811122
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3043497074
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.698694376
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4062248171
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.513330147
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2200540256
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1952500349
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1685994793
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.622987403
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2169880471
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3187691566
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2660742320
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.216609693
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3048454102
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.669534707
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1566757562
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2389964742
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3619998827
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1759460981
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1917256748
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2658497867
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.577739283
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1016770692
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4202351868
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.441581826
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.372128036
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1631300209
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3234185504
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3813780690
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.155380679
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2010310183
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.387230358
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.58524360
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3946911367
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1662946085
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2257267293
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2661563636
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.991749053
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2690853599
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2454106032
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.64901193
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.2360142619
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1074735115
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.4282317315
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2575097878
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3012688458
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.4072825155
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.966521552
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2312283915
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3746880497
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2492213274
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3421776925
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2557499024
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.2716864846
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.685302618
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1766832518
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1835630313
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1971618522
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3626198179



Total test records in report: 998
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.712981949 Oct 15 04:30:51 AM UTC 24 Oct 15 04:30:57 AM UTC 24 94981240 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.121371309 Oct 15 04:30:58 AM UTC 24 Oct 15 04:31:01 AM UTC 24 13954572 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.4288160492 Oct 15 04:31:07 AM UTC 24 Oct 15 04:31:13 AM UTC 24 69033152 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1533206005 Oct 15 04:31:14 AM UTC 24 Oct 15 04:31:21 AM UTC 24 185633739 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1052092684 Oct 15 04:31:01 AM UTC 24 Oct 15 04:31:25 AM UTC 24 878274880 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2967245795 Oct 15 04:31:23 AM UTC 24 Oct 15 04:31:44 AM UTC 24 1904821017 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1651263993 Oct 15 04:31:26 AM UTC 24 Oct 15 04:31:47 AM UTC 24 739396652 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3412997569 Oct 15 04:31:46 AM UTC 24 Oct 15 04:31:48 AM UTC 24 18006383 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1720910794 Oct 15 04:31:29 AM UTC 24 Oct 15 04:31:49 AM UTC 24 340130395 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3405241729 Oct 15 04:31:48 AM UTC 24 Oct 15 04:31:55 AM UTC 24 772554778 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2992840379 Oct 15 04:31:50 AM UTC 24 Oct 15 04:32:02 AM UTC 24 352119103 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1831707344 Oct 15 04:31:56 AM UTC 24 Oct 15 04:32:07 AM UTC 24 529532326 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2559492986 Oct 15 04:32:03 AM UTC 24 Oct 15 04:32:09 AM UTC 24 995203416 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4095773324 Oct 15 04:32:10 AM UTC 24 Oct 15 04:32:32 AM UTC 24 989407720 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2100926137 Oct 15 04:32:07 AM UTC 24 Oct 15 04:32:34 AM UTC 24 3366345975 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3631758956 Oct 15 04:32:28 AM UTC 24 Oct 15 04:32:42 AM UTC 24 1761469786 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.1251855602 Oct 15 04:32:19 AM UTC 24 Oct 15 04:32:42 AM UTC 24 1610010313 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.803302871 Oct 15 04:32:45 AM UTC 24 Oct 15 04:32:47 AM UTC 24 27972625 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3168681592 Oct 15 04:32:50 AM UTC 24 Oct 15 04:32:52 AM UTC 24 46737682 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.4269891837 Oct 15 04:32:48 AM UTC 24 Oct 15 04:32:55 AM UTC 24 80286413 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2705495665 Oct 15 04:32:00 AM UTC 24 Oct 15 04:33:00 AM UTC 24 9616253200 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2313565160 Oct 15 04:32:33 AM UTC 24 Oct 15 04:33:02 AM UTC 24 2139452827 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.2062519318 Oct 15 04:32:56 AM UTC 24 Oct 15 04:33:03 AM UTC 24 592042015 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3996637041 Oct 15 04:33:04 AM UTC 24 Oct 15 04:33:07 AM UTC 24 13459832 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1545111495 Oct 15 04:32:56 AM UTC 24 Oct 15 04:33:08 AM UTC 24 77482738 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1207673667 Oct 15 04:32:43 AM UTC 24 Oct 15 04:33:11 AM UTC 24 281310488 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.347884002 Oct 15 04:31:49 AM UTC 24 Oct 15 04:33:17 AM UTC 24 5868223231 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.1054986639 Oct 15 04:33:03 AM UTC 24 Oct 15 04:33:17 AM UTC 24 644164116 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3509179931 Oct 15 04:33:07 AM UTC 24 Oct 15 04:33:17 AM UTC 24 1267577043 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.2634339663 Oct 15 04:33:12 AM UTC 24 Oct 15 04:33:20 AM UTC 24 1002039516 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1092702222 Oct 15 04:33:04 AM UTC 24 Oct 15 04:33:22 AM UTC 24 1321395434 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1020122984 Oct 15 04:33:02 AM UTC 24 Oct 15 04:33:22 AM UTC 24 568881646 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1826710416 Oct 15 04:32:53 AM UTC 24 Oct 15 04:33:23 AM UTC 24 1086790097 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1097987921 Oct 15 04:33:17 AM UTC 24 Oct 15 04:33:24 AM UTC 24 1563864207 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.741515068 Oct 15 04:33:17 AM UTC 24 Oct 15 04:33:29 AM UTC 24 606815658 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3526304247 Oct 15 04:33:28 AM UTC 24 Oct 15 04:33:31 AM UTC 24 145191699 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1647008410 Oct 15 04:33:29 AM UTC 24 Oct 15 04:33:33 AM UTC 24 59317218 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2034928050 Oct 15 04:33:20 AM UTC 24 Oct 15 04:33:33 AM UTC 24 312555807 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1038841708 Oct 15 04:33:31 AM UTC 24 Oct 15 04:33:34 AM UTC 24 19817155 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3504920704 Oct 15 04:33:23 AM UTC 24 Oct 15 04:33:35 AM UTC 24 164105439 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.3500164559 Oct 15 04:33:23 AM UTC 24 Oct 15 04:33:37 AM UTC 24 986979048 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.423528243 Oct 15 04:33:35 AM UTC 24 Oct 15 04:33:41 AM UTC 24 328007976 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3260584234 Oct 15 04:33:35 AM UTC 24 Oct 15 04:33:42 AM UTC 24 210990319 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.506227339 Oct 15 04:33:43 AM UTC 24 Oct 15 04:33:45 AM UTC 24 19446939 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1758750451 Oct 15 04:33:18 AM UTC 24 Oct 15 04:33:51 AM UTC 24 5420133783 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3033873938 Oct 15 04:33:15 AM UTC 24 Oct 15 04:33:52 AM UTC 24 3350321919 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.498898593 Oct 15 04:33:36 AM UTC 24 Oct 15 04:33:53 AM UTC 24 1501881373 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.314901695 Oct 15 04:33:12 AM UTC 24 Oct 15 04:33:55 AM UTC 24 4203543405 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1492440985 Oct 15 04:33:38 AM UTC 24 Oct 15 04:33:55 AM UTC 24 1419902141 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3058457323 Oct 15 04:33:46 AM UTC 24 Oct 15 04:33:56 AM UTC 24 323301882 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.208391389 Oct 15 04:33:41 AM UTC 24 Oct 15 04:33:57 AM UTC 24 1171147225 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.155475482 Oct 15 04:34:23 AM UTC 24 Oct 15 04:34:25 AM UTC 24 11585474 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.1254478630 Oct 15 04:33:33 AM UTC 24 Oct 15 04:34:01 AM UTC 24 495502810 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1812722686 Oct 15 04:33:57 AM UTC 24 Oct 15 04:34:02 AM UTC 24 352820646 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.3562606357 Oct 15 04:33:56 AM UTC 24 Oct 15 04:34:05 AM UTC 24 1127246209 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3230560808 Oct 15 04:33:52 AM UTC 24 Oct 15 04:34:07 AM UTC 24 344115876 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.3904471187 Oct 15 04:33:26 AM UTC 24 Oct 15 04:34:12 AM UTC 24 217371936 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.354304821 Oct 15 04:33:54 AM UTC 24 Oct 15 04:34:13 AM UTC 24 425311474 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1870665048 Oct 15 04:32:35 AM UTC 24 Oct 15 04:34:13 AM UTC 24 4306518060 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.646494360 Oct 15 04:34:14 AM UTC 24 Oct 15 04:34:17 AM UTC 24 56555112 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1002262335 Oct 15 04:34:14 AM UTC 24 Oct 15 04:34:17 AM UTC 24 21862968 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.44636003 Oct 15 04:34:02 AM UTC 24 Oct 15 04:34:18 AM UTC 24 283068103 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2865353532 Oct 15 04:33:58 AM UTC 24 Oct 15 04:34:18 AM UTC 24 1029577653 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2613599616 Oct 15 04:34:17 AM UTC 24 Oct 15 04:34:20 AM UTC 24 12824522 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.899385421 Oct 15 04:34:19 AM UTC 24 Oct 15 04:34:23 AM UTC 24 38732146 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.2771702030 Oct 15 04:34:03 AM UTC 24 Oct 15 04:34:23 AM UTC 24 469439675 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2389138094 Oct 15 04:34:02 AM UTC 24 Oct 15 04:34:23 AM UTC 24 532164102 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.244045290 Oct 15 04:34:18 AM UTC 24 Oct 15 04:34:27 AM UTC 24 175162469 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.3551573551 Oct 15 04:34:24 AM UTC 24 Oct 15 04:34:30 AM UTC 24 2624377989 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3713494741 Oct 15 04:34:21 AM UTC 24 Oct 15 04:34:30 AM UTC 24 378430886 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.3007735135 Oct 15 04:34:31 AM UTC 24 Oct 15 04:34:33 AM UTC 24 110203278 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.3328545815 Oct 15 04:33:52 AM UTC 24 Oct 15 04:34:36 AM UTC 24 2966569882 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1983959157 Oct 15 04:34:19 AM UTC 24 Oct 15 04:34:37 AM UTC 24 1962133207 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.3422207300 Oct 15 04:34:35 AM UTC 24 Oct 15 04:34:41 AM UTC 24 494198749 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2319811296 Oct 15 04:34:28 AM UTC 24 Oct 15 04:34:42 AM UTC 24 462412645 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.1144134172 Oct 15 04:33:09 AM UTC 24 Oct 15 04:34:44 AM UTC 24 17954819313 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.478035291 Oct 15 04:34:17 AM UTC 24 Oct 15 04:34:46 AM UTC 24 262597989 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.3475895166 Oct 15 04:34:23 AM UTC 24 Oct 15 04:34:47 AM UTC 24 332087814 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3837226616 Oct 15 04:34:26 AM UTC 24 Oct 15 04:34:48 AM UTC 24 2004446770 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1263051753 Oct 15 04:34:48 AM UTC 24 Oct 15 04:34:50 AM UTC 24 126866538 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.421050247 Oct 15 04:34:49 AM UTC 24 Oct 15 04:34:53 AM UTC 24 193129362 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4073486078 Oct 15 04:34:51 AM UTC 24 Oct 15 04:34:53 AM UTC 24 150837333 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.1316533274 Oct 15 04:33:56 AM UTC 24 Oct 15 04:34:54 AM UTC 24 7215707910 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1984807057 Oct 15 04:34:40 AM UTC 24 Oct 15 04:34:54 AM UTC 24 1244919789 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3261099435 Oct 15 04:34:13 AM UTC 24 Oct 15 04:34:58 AM UTC 24 226134083 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.3521150122 Oct 15 04:34:55 AM UTC 24 Oct 15 04:35:01 AM UTC 24 108757803 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.2833471739 Oct 15 04:34:54 AM UTC 24 Oct 15 04:35:06 AM UTC 24 179583104 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.406697273 Oct 15 04:35:07 AM UTC 24 Oct 15 04:35:09 AM UTC 24 15870587 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.869154891 Oct 15 04:36:32 AM UTC 24 Oct 15 04:36:44 AM UTC 24 1476694263 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1072167996 Oct 15 04:34:38 AM UTC 24 Oct 15 04:35:12 AM UTC 24 1477820589 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1868304181 Oct 15 04:34:41 AM UTC 24 Oct 15 04:35:14 AM UTC 24 3858722644 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.36858092 Oct 15 04:35:10 AM UTC 24 Oct 15 04:35:15 AM UTC 24 93547796 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2145124135 Oct 15 04:34:37 AM UTC 24 Oct 15 04:35:15 AM UTC 24 3959463339 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3706216495 Oct 15 04:33:24 AM UTC 24 Oct 15 04:35:16 AM UTC 24 3153924832 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.278793119 Oct 15 04:35:00 AM UTC 24 Oct 15 04:35:19 AM UTC 24 589539679 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.518842069 Oct 15 04:35:16 AM UTC 24 Oct 15 04:35:21 AM UTC 24 119810392 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.1864979128 Oct 15 04:34:55 AM UTC 24 Oct 15 04:35:21 AM UTC 24 826819534 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.4257810978 Oct 15 04:34:31 AM UTC 24 Oct 15 04:35:23 AM UTC 24 1419719803 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2076234799 Oct 15 04:35:02 AM UTC 24 Oct 15 04:35:23 AM UTC 24 263886979 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2718562313 Oct 15 04:35:16 AM UTC 24 Oct 15 04:35:25 AM UTC 24 853018449 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3585031247 Oct 15 04:35:12 AM UTC 24 Oct 15 04:35:25 AM UTC 24 7377973023 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.3647071813 Oct 15 04:34:54 AM UTC 24 Oct 15 04:35:29 AM UTC 24 746636147 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.3935110804 Oct 15 04:35:18 AM UTC 24 Oct 15 04:35:31 AM UTC 24 617985142 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2505953728 Oct 15 04:34:47 AM UTC 24 Oct 15 04:35:33 AM UTC 24 249228272 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2383806560 Oct 15 04:35:30 AM UTC 24 Oct 15 04:35:33 AM UTC 24 89655497 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.989811195 Oct 15 04:35:33 AM UTC 24 Oct 15 04:35:35 AM UTC 24 23683714 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3218020146 Oct 15 04:35:22 AM UTC 24 Oct 15 04:35:35 AM UTC 24 1212978591 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.128796513 Oct 15 04:35:32 AM UTC 24 Oct 15 04:35:36 AM UTC 24 125798136 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.4154962230 Oct 15 04:34:24 AM UTC 24 Oct 15 04:35:40 AM UTC 24 1688433742 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.594125827 Oct 15 04:35:34 AM UTC 24 Oct 15 04:35:41 AM UTC 24 298508535 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.4155232732 Oct 15 04:35:36 AM UTC 24 Oct 15 04:35:42 AM UTC 24 355951040 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2242347670 Oct 15 04:35:24 AM UTC 24 Oct 15 04:35:43 AM UTC 24 357880988 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1364751129 Oct 15 04:35:20 AM UTC 24 Oct 15 04:35:44 AM UTC 24 5741735698 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.120536826 Oct 15 04:35:21 AM UTC 24 Oct 15 04:35:44 AM UTC 24 455196739 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2469212365 Oct 15 04:35:43 AM UTC 24 Oct 15 04:35:45 AM UTC 24 41503050 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3011736193 Oct 15 04:35:37 AM UTC 24 Oct 15 04:35:51 AM UTC 24 1485254410 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.4183830082 Oct 15 04:35:46 AM UTC 24 Oct 15 04:35:52 AM UTC 24 168702343 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.4292595223 Oct 15 04:35:45 AM UTC 24 Oct 15 04:35:53 AM UTC 24 785415024 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1841018943 Oct 15 04:35:36 AM UTC 24 Oct 15 04:35:53 AM UTC 24 280708597 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3043208781 Oct 15 04:35:43 AM UTC 24 Oct 15 04:35:54 AM UTC 24 455416589 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.4148729188 Oct 15 04:35:16 AM UTC 24 Oct 15 04:35:57 AM UTC 24 19486285034 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2453969217 Oct 15 04:35:40 AM UTC 24 Oct 15 04:36:01 AM UTC 24 3755112996 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1011561059 Oct 15 04:35:44 AM UTC 24 Oct 15 04:36:02 AM UTC 24 1305508021 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2851075656 Oct 15 04:35:51 AM UTC 24 Oct 15 04:36:04 AM UTC 24 2016464816 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.106623846 Oct 15 04:36:02 AM UTC 24 Oct 15 04:36:05 AM UTC 24 75312861 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.976009653 Oct 15 04:36:32 AM UTC 24 Oct 15 04:36:45 AM UTC 24 466167068 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.2304848130 Oct 15 04:35:55 AM UTC 24 Oct 15 04:36:07 AM UTC 24 1065946273 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1979640012 Oct 15 04:35:53 AM UTC 24 Oct 15 04:36:08 AM UTC 24 482040787 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.998754436 Oct 15 04:34:06 AM UTC 24 Oct 15 04:36:08 AM UTC 24 4062766729 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3866442695 Oct 15 04:36:06 AM UTC 24 Oct 15 04:36:08 AM UTC 24 76695362 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.145976041 Oct 15 04:35:26 AM UTC 24 Oct 15 04:36:09 AM UTC 24 1600107624 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2978220936 Oct 15 04:35:52 AM UTC 24 Oct 15 04:36:09 AM UTC 24 1585384165 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3643672535 Oct 15 04:36:05 AM UTC 24 Oct 15 04:36:10 AM UTC 24 830025140 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.1270214667 Oct 15 04:35:55 AM UTC 24 Oct 15 04:36:11 AM UTC 24 1246717158 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.530910273 Oct 15 04:35:34 AM UTC 24 Oct 15 04:36:11 AM UTC 24 315045345 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.545890719 Oct 15 04:36:09 AM UTC 24 Oct 15 04:36:12 AM UTC 24 31758860 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2055171896 Oct 15 04:36:10 AM UTC 24 Oct 15 04:36:13 AM UTC 24 64066576 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.317875130 Oct 15 04:36:10 AM UTC 24 Oct 15 04:36:17 AM UTC 24 216963168 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.283425614 Oct 15 04:36:13 AM UTC 24 Oct 15 04:36:17 AM UTC 24 383967618 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.3266997448 Oct 15 04:35:12 AM UTC 24 Oct 15 04:36:18 AM UTC 24 3754674868 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.722413370 Oct 15 04:36:07 AM UTC 24 Oct 15 04:36:18 AM UTC 24 510887770 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3336232210 Oct 15 04:36:13 AM UTC 24 Oct 15 04:36:19 AM UTC 24 215745887 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.2360142619 Oct 15 04:36:10 AM UTC 24 Oct 15 04:36:23 AM UTC 24 3865609213 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2476334068 Oct 15 04:36:10 AM UTC 24 Oct 15 04:36:24 AM UTC 24 552687326 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.2697355969 Oct 15 04:36:25 AM UTC 24 Oct 15 04:36:27 AM UTC 24 17543393 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.64901193 Oct 15 04:36:18 AM UTC 24 Oct 15 04:36:28 AM UTC 24 1090177937 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3044701837 Oct 15 04:36:10 AM UTC 24 Oct 15 04:36:30 AM UTC 24 1346566528 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2492213274 Oct 15 04:36:28 AM UTC 24 Oct 15 04:36:30 AM UTC 24 46844573 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.4072825155 Oct 15 04:36:27 AM UTC 24 Oct 15 04:36:31 AM UTC 24 158456101 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2690853599 Oct 15 04:36:18 AM UTC 24 Oct 15 04:36:34 AM UTC 24 632988543 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.4017782654 Oct 15 04:36:12 AM UTC 24 Oct 15 04:36:34 AM UTC 24 2926810982 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2172277209 Oct 15 04:36:12 AM UTC 24 Oct 15 04:36:35 AM UTC 24 699878718 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2454106032 Oct 15 04:36:19 AM UTC 24 Oct 15 04:36:35 AM UTC 24 239385973 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1576170018 Oct 15 04:36:32 AM UTC 24 Oct 15 04:36:36 AM UTC 24 62385268 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.848376194 Oct 15 04:35:45 AM UTC 24 Oct 15 04:36:37 AM UTC 24 2114509453 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1621379292 Oct 15 04:36:35 AM UTC 24 Oct 15 04:36:37 AM UTC 24 15507965 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2312283915 Oct 15 04:36:29 AM UTC 24 Oct 15 04:36:42 AM UTC 24 166512185 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.3042228246 Oct 15 04:36:35 AM UTC 24 Oct 15 04:36:42 AM UTC 24 305406845 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2263702014 Oct 15 04:35:44 AM UTC 24 Oct 15 04:36:43 AM UTC 24 5844033867 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.2763927623 Oct 15 04:37:58 AM UTC 24 Oct 15 04:38:02 AM UTC 24 514729129 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1674375107 Oct 15 04:36:33 AM UTC 24 Oct 15 04:36:45 AM UTC 24 790402420 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1074735115 Oct 15 04:36:07 AM UTC 24 Oct 15 04:36:45 AM UTC 24 1233418873 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.482609547 Oct 15 04:36:47 AM UTC 24 Oct 15 04:36:49 AM UTC 24 123801572 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.725442643 Oct 15 04:36:39 AM UTC 24 Oct 15 04:36:49 AM UTC 24 4174628041 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1923361801 Oct 15 04:36:37 AM UTC 24 Oct 15 04:36:52 AM UTC 24 2529025713 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.809802844 Oct 15 04:36:50 AM UTC 24 Oct 15 04:36:53 AM UTC 24 40393787 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1971618522 Oct 15 04:36:50 AM UTC 24 Oct 15 04:36:55 AM UTC 24 28634083 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.966521552 Oct 15 04:36:28 AM UTC 24 Oct 15 04:36:58 AM UTC 24 479917805 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3012688458 Oct 15 04:36:45 AM UTC 24 Oct 15 04:36:58 AM UTC 24 5640563050 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2928425472 Oct 15 04:36:54 AM UTC 24 Oct 15 04:37:00 AM UTC 24 55336797 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3530660181 Oct 15 04:36:18 AM UTC 24 Oct 15 04:37:01 AM UTC 24 2463630541 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.681887266 Oct 15 04:36:59 AM UTC 24 Oct 15 04:37:01 AM UTC 24 11408531 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.4282317315 Oct 15 04:36:44 AM UTC 24 Oct 15 04:37:01 AM UTC 24 580138955 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.422363362 Oct 15 04:36:12 AM UTC 24 Oct 15 04:37:02 AM UTC 24 1669916351 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2926186516 Oct 15 04:35:26 AM UTC 24 Oct 15 04:37:03 AM UTC 24 1870761519 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3638772977 Oct 15 04:36:59 AM UTC 24 Oct 15 04:37:06 AM UTC 24 628036861 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2575097878 Oct 15 04:36:45 AM UTC 24 Oct 15 04:37:06 AM UTC 24 4368765898 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.897381024 Oct 15 04:36:54 AM UTC 24 Oct 15 04:37:06 AM UTC 24 761541765 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1897958593 Oct 15 04:36:43 AM UTC 24 Oct 15 04:37:07 AM UTC 24 6411309388 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1299743351 Oct 15 04:36:43 AM UTC 24 Oct 15 04:37:10 AM UTC 24 901754349 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3814697944 Oct 15 04:36:55 AM UTC 24 Oct 15 04:37:11 AM UTC 24 5862294918 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.2502607876 Oct 15 04:37:10 AM UTC 24 Oct 15 04:37:13 AM UTC 24 56214472 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.2292927914 Oct 15 04:37:05 AM UTC 24 Oct 15 04:37:16 AM UTC 24 1539491911 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3626198179 Oct 15 04:37:14 AM UTC 24 Oct 15 04:37:16 AM UTC 24 108539342 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.4261323035 Oct 15 04:37:13 AM UTC 24 Oct 15 04:37:18 AM UTC 24 105269185 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3077820666 Oct 15 04:36:54 AM UTC 24 Oct 15 04:37:18 AM UTC 24 280009574 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.455588795 Oct 15 04:37:02 AM UTC 24 Oct 15 04:37:18 AM UTC 24 410842954 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.4180036788 Oct 15 04:36:59 AM UTC 24 Oct 15 04:37:19 AM UTC 24 346235997 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.2588443604 Oct 15 04:36:36 AM UTC 24 Oct 15 04:37:19 AM UTC 24 1179784445 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1835630313 Oct 15 04:36:56 AM UTC 24 Oct 15 04:37:19 AM UTC 24 5254521674 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3140815129 Oct 15 04:37:02 AM UTC 24 Oct 15 04:37:20 AM UTC 24 3513303800 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3421776925 Oct 15 04:37:03 AM UTC 24 Oct 15 04:37:21 AM UTC 24 2868229008 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1766832518 Oct 15 04:37:07 AM UTC 24 Oct 15 04:37:22 AM UTC 24 2416774344 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3542189464 Oct 15 04:37:20 AM UTC 24 Oct 15 04:37:23 AM UTC 24 37733290 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2163839070 Oct 15 04:37:17 AM UTC 24 Oct 15 04:37:23 AM UTC 24 304778293 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1129214698 Oct 15 04:36:12 AM UTC 24 Oct 15 04:37:23 AM UTC 24 3280128196 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3128119643 Oct 15 04:37:19 AM UTC 24 Oct 15 04:37:25 AM UTC 24 91986214 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.2716864846 Oct 15 04:37:06 AM UTC 24 Oct 15 04:37:25 AM UTC 24 512519104 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.685302618 Oct 15 04:37:07 AM UTC 24 Oct 15 04:37:25 AM UTC 24 2363703028 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3272397144 Oct 15 04:37:20 AM UTC 24 Oct 15 04:37:25 AM UTC 24 202733055 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2831960839 Oct 15 04:37:05 AM UTC 24 Oct 15 04:37:27 AM UTC 24 902470203 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.3706695989 Oct 15 04:37:24 AM UTC 24 Oct 15 04:37:30 AM UTC 24 162342579 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2992019564 Oct 15 04:37:19 AM UTC 24 Oct 15 04:37:32 AM UTC 24 523118453 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3254920124 Oct 15 04:37:24 AM UTC 24 Oct 15 04:37:32 AM UTC 24 1984715083 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.2447137343 Oct 15 04:37:24 AM UTC 24 Oct 15 04:37:32 AM UTC 24 1585973735 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.4164652715 Oct 15 04:37:19 AM UTC 24 Oct 15 04:37:33 AM UTC 24 818909285 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1438512734 Oct 15 04:37:22 AM UTC 24 Oct 15 04:37:35 AM UTC 24 1487116124 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.4212642541 Oct 15 04:37:33 AM UTC 24 Oct 15 04:37:36 AM UTC 24 61757377 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.240342428 Oct 15 04:37:33 AM UTC 24 Oct 15 04:37:36 AM UTC 24 21941582 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.103662442 Oct 15 04:37:43 AM UTC 24 Oct 15 04:38:03 AM UTC 24 8913616697 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2275145433 Oct 15 04:37:19 AM UTC 24 Oct 15 04:37:36 AM UTC 24 4913436979 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3961725729 Oct 15 04:35:24 AM UTC 24 Oct 15 04:37:37 AM UTC 24 112566925909 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.368731612 Oct 15 04:37:27 AM UTC 24 Oct 15 04:37:37 AM UTC 24 304850580 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3746880497 Oct 15 04:36:46 AM UTC 24 Oct 15 04:37:41 AM UTC 24 4498008239 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3467016023 Oct 15 04:36:01 AM UTC 24 Oct 15 04:37:42 AM UTC 24 12605472694 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1581620177 Oct 15 04:37:27 AM UTC 24 Oct 15 04:37:42 AM UTC 24 1172662301 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2616584261 Oct 15 04:37:37 AM UTC 24 Oct 15 04:37:42 AM UTC 24 462979523 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.109373185 Oct 15 04:37:17 AM UTC 24 Oct 15 04:37:43 AM UTC 24 666813672 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1979173006 Oct 15 04:37:35 AM UTC 24 Oct 15 04:37:45 AM UTC 24 115320409 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3000435862 Oct 15 04:37:26 AM UTC 24 Oct 15 04:37:46 AM UTC 24 442598363 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.22411213 Oct 15 04:37:33 AM UTC 24 Oct 15 04:37:46 AM UTC 24 237548716 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1569512313 Oct 15 04:37:38 AM UTC 24 Oct 15 04:37:47 AM UTC 24 250148664 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.1463054368 Oct 15 04:37:43 AM UTC 24 Oct 15 04:37:48 AM UTC 24 239121924 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.138838626 Oct 15 04:37:47 AM UTC 24 Oct 15 04:37:50 AM UTC 24 64917243 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.561018697 Oct 15 04:37:25 AM UTC 24 Oct 15 04:37:51 AM UTC 24 639828172 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1768784752 Oct 15 04:37:37 AM UTC 24 Oct 15 04:37:51 AM UTC 24 630820288 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.1596604655 Oct 15 04:37:34 AM UTC 24 Oct 15 04:38:02 AM UTC 24 161420853 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.4206624460 Oct 15 04:37:49 AM UTC 24 Oct 15 04:37:52 AM UTC 24 109282793 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.218810162 Oct 15 04:37:37 AM UTC 24 Oct 15 04:37:53 AM UTC 24 1343228485 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.788081653 Oct 15 04:36:39 AM UTC 24 Oct 15 04:37:53 AM UTC 24 4950282290 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3243343449 Oct 15 04:37:51 AM UTC 24 Oct 15 04:37:53 AM UTC 24 14045503 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.1284911147 Oct 15 04:36:36 AM UTC 24 Oct 15 04:37:53 AM UTC 24 3824818391 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.40514917 Oct 15 04:37:43 AM UTC 24 Oct 15 04:37:56 AM UTC 24 288287887 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.3604342685 Oct 15 04:37:53 AM UTC 24 Oct 15 04:37:57 AM UTC 24 261970987 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2928653310 Oct 15 04:37:46 AM UTC 24 Oct 15 04:38:00 AM UTC 24 494629878 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.4090495904 Oct 15 04:37:44 AM UTC 24 Oct 15 04:38:00 AM UTC 24 1103655641 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.4164430520 Oct 15 04:37:01 AM UTC 24 Oct 15 04:38:01 AM UTC 24 4273319375 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2675911914 Oct 15 04:38:07 AM UTC 24 Oct 15 04:38:11 AM UTC 24 36001664 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.2046485191 Oct 15 04:37:46 AM UTC 24 Oct 15 04:38:03 AM UTC 24 1269142120 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.1799184214 Oct 15 04:37:53 AM UTC 24 Oct 15 04:38:04 AM UTC 24 98716687 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1203917648 Oct 15 04:37:54 AM UTC 24 Oct 15 04:38:06 AM UTC 24 5126793266 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.3468050793 Oct 15 04:37:54 AM UTC 24 Oct 15 04:38:06 AM UTC 24 2249640754 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3405146370 Oct 15 04:34:42 AM UTC 24 Oct 15 04:38:07 AM UTC 24 30434493023 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2638791079 Oct 15 04:38:05 AM UTC 24 Oct 15 04:38:07 AM UTC 24 58310435 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1761546755 Oct 15 04:37:08 AM UTC 24 Oct 15 04:38:09 AM UTC 24 15926569372 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2550188178 Oct 15 04:38:07 AM UTC 24 Oct 15 04:38:09 AM UTC 24 126827881 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.63046011 Oct 15 04:37:24 AM UTC 24 Oct 15 04:38:09 AM UTC 24 5892059959 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.144790449 Oct 15 04:38:02 AM UTC 24 Oct 15 04:38:11 AM UTC 24 2964210257 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2487738540 Oct 15 04:37:57 AM UTC 24 Oct 15 04:38:13 AM UTC 24 1537923948 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.965718402 Oct 15 04:36:21 AM UTC 24 Oct 15 04:38:14 AM UTC 24 22055580149 ps