Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115900009

1

T1

1245

T2

3619

T3

4344

auto[1]

1501918

1

T3

297

T4

396

T5

98

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115884797

1

T1

1245

T2

3619

T3

4245

auto[1]

1517130

1

T3

396

T4

297

T12

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7957473	1			T1	70		T2	696		T3	727
auto[IdleSt]	22860810	1			T1	48		T2	797		T3	828
auto[ClkMuxSt]	38808	1			T1	1		T2	8		T3	7
auto[CntIncrSt]	38584	1			T1	1		T2	8		T3	7
auto[CntProgSt]	2082814	1			T1	4		T2	138		T3	1793
auto[TransCheckSt]	29867	1			T1	1		T2	8		T4	6
auto[TokenHashSt]	49968141	1			T1	10		T2	854		T4	200
auto[FlashRmaSt]	38358	1			T2	8		T4	6		T12	49
auto[TokenCheck0St]	13929	1			T2	8		T4	6		T12	15
auto[TokenCheck1St]	10392	1			T2	8		T4	6		T12	8
auto[TransProgSt]	555442	1			T2	103		T4	60		T12	16
auto[PostTransSt]	13508142	1			T1	1110		T2	983		T3	435
auto[ScrapSt]	201631	1			T21	12		T37	1626		T27	4
auto[EscalateSt]	7396140	1			T3	844		T4	1875		T12	519
auto[InvalidSt]	12699168	1			T4	1303		T31	664		T35	6015

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2228	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12699168	1			T4	1303		T31	664		T35	6015
EscalateSt	7396140	1			T3	844		T4	1875		T12	519
ScrapSt	201631	1			T21	12		T37	1626		T27	4
PostTransSt	13508142	1			T1	1110		T2	983		T3	435
TransProgSt	555442	1			T2	103		T4	60		T12	16
TokenCheck1St	10392	1			T2	8		T4	6		T12	8
TokenCheck0St	13929	1			T2	8		T4	6		T12	15
FlashRmaSt	38358	1			T2	8		T4	6		T12	49
TokenHashSt	49968141	1			T1	10		T2	854		T4	200
TransCheckSt	29867	1			T1	1		T2	8		T4	6
CntProgSt	2082814	1			T1	4		T2	138		T3	1793
CntIncrSt	38584	1			T1	1		T2	8		T3	7
ClkMuxSt	38808	1			T1	1		T2	8		T3	7
IdleSt	22860810	1			T1	48		T2	797		T3	828
ResetSt	7957473	1			T1	70		T2	696		T3	727
arcs[ResetSt=>IdleSt]	59052	1			T1	1		T2	8		T3	8
arcs[IdleSt=>ScrapSt]	309	1			T21	3		T37	1		T27	1
arcs[IdleSt=>ClkMuxSt]	38612	1			T1	1		T2	8		T3	7
arcs[ClkMuxSt=>CntIncrSt]	38584	1			T1	1		T2	8		T3	7
arcs[CntIncrSt=>PostTransSt]	2078	1			T12	7		T23	8		T33	8
arcs[CntIncrSt=>CntProgSt]	36450	1			T1	1		T2	8		T3	7
arcs[CntProgSt=>PostTransSt]	5477	1			T3	7		T12	4		T5	1
arcs[CntProgSt=>TransCheckSt]	29867	1			T1	1		T2	8		T4	6
arcs[TransCheckSt=>PostTransSt]	3953	1			T12	4		T25	31		T23	10
arcs[TransCheckSt=>TokenHashSt]	25814	1			T1	1		T2	8		T4	6
arcs[TokenHashSt=>PostTransSt]	10998	1			T1	1		T12	24		T16	1
arcs[TokenHashSt=>FlashRmaSt]	13978	1			T2	8		T4	6		T12	15
arcs[FlashRmaSt=>TokenCheck0St]	13929	1			T2	8		T4	6		T12	15
arcs[TokenCheck0St=>PostTransSt]	3478	1			T12	7		T25	17		T23	2
arcs[TokenCheck0St=>TokenCheck1St]	10392	1			T2	8		T4	6		T12	8
arcs[TokenCheck1St=>PostTransSt]	678	1			T25	9		T30	14		T57	1
arcs[TransProgSt=>PostTransSt]	8876	1			T2	8		T4	6		T12	8
arcs[IdleSt=>EscalateSt]	161	1			T27	4		T67	5		T65	3
arcs[ClkMuxSt=>EscalateSt]	28	1			T27	1		T65	3		T66	1
arcs[CntIncrSt=>EscalateSt]	56	1			T21	1		T27	2		T65	1
arcs[CntProgSt=>EscalateSt]	1106	1			T21	34		T27	34		T67	6
arcs[TransCheckSt=>EscalateSt]	100	1			T21	1		T27	1		T67	4
arcs[TokenHashSt=>EscalateSt]	838	1			T21	14		T27	9		T67	18
arcs[FlashRmaSt=>EscalateSt]	49	1			T21	2		T68	2		T20	2
arcs[TokenCheck0St=>EscalateSt]	59	1			T21	1		T27	1		T65	1
arcs[TokenCheck1St=>EscalateSt]	21	1			T65	1		T68	1		T20	1
arcs[TransProgSt=>EscalateSt]	817	1			T21	18		T27	20		T67	3
arcs[PostTransSt=>EscalateSt]	5887	1			T3	7		T12	4		T5	1
arcs[InvalidSt=>EscalateSt]	15491	1			T4	7		T31	4		T35	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7957294	1			T1	70		T2	696		T3	727
auto[0]	auto[IdleSt]	22860700	1			T1	48		T2	797		T3	828
auto[0]	auto[ClkMuxSt]	38790	1			T1	1		T2	8		T3	7
auto[0]	auto[CntIncrSt]	38544	1			T1	1		T2	8		T3	7
auto[0]	auto[CntProgSt]	2082077	1			T1	4		T2	138		T3	1793
auto[0]	auto[TransCheckSt]	29806	1			T1	1		T2	8		T4	6
auto[0]	auto[TokenHashSt]	49967595	1			T1	10		T2	854		T4	200
auto[0]	auto[FlashRmaSt]	38322	1			T2	8		T4	6		T12	49
auto[0]	auto[TokenCheck0St]	13894	1			T2	8		T4	6		T12	15
auto[0]	auto[TokenCheck1St]	10375	1			T2	8		T4	6		T12	8
auto[0]	auto[TransProgSt]	554894	1			T2	103		T4	60		T12	16
auto[0]	auto[PostTransSt]	13505110	1			T1	1110		T2	983		T3	432
auto[0]	auto[ScrapSt]	201583	1			T21	11		T37	1626		T27	4
auto[0]	auto[EscalateSt]	5907263	1			T3	550		T4	1483		T12	519
auto[0]	auto[InvalidSt]	12691534	1			T4	1299		T31	662		T35	6014
auto[1]	auto[ResetSt]	179	1			T21	3		T27	3		T67	1
auto[1]	auto[IdleSt]	110	1			T27	4		T67	5		T65	1
auto[1]	auto[ClkMuxSt]	18	1			T27	1		T65	3		T215	2
auto[1]	auto[CntIncrSt]	40	1			T21	1		T27	2		T20	1
auto[1]	auto[CntProgSt]	737	1			T21	21		T27	22		T67	5
auto[1]	auto[TransCheckSt]	61	1			T67	3		T68	5		T20	2
auto[1]	auto[TokenHashSt]	546	1			T21	10		T27	6		T67	10
auto[1]	auto[FlashRmaSt]	36	1			T21	2		T68	2		T20	1
auto[1]	auto[TokenCheck0St]	35	1			T65	1		T68	1		T216	1
auto[1]	auto[TokenCheck1St]	17	1			T65	1		T68	1		T20	1
auto[1]	auto[TransProgSt]	548	1			T21	9		T27	12		T67	1
auto[1]	auto[PostTransSt]	3032	1			T3	3		T5	1		T22	8
auto[1]	auto[ScrapSt]	48	1			T21	1		T67	1		T20	1
auto[1]	auto[EscalateSt]	1488877	1			T3	294		T4	392		T5	97
auto[1]	auto[InvalidSt]	7634	1			T4	4		T31	2		T35	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7957287	1			T1	70		T2	696		T3	727
auto[0]	auto[IdleSt]	22860692	1			T1	48		T2	797		T3	828
auto[0]	auto[ClkMuxSt]	38787	1			T1	1		T2	8		T3	7
auto[0]	auto[CntIncrSt]	38550	1			T1	1		T2	8		T3	7
auto[0]	auto[CntProgSt]	2082100	1			T1	4		T2	138		T3	1793
auto[0]	auto[TransCheckSt]	29806	1			T1	1		T2	8		T4	6
auto[0]	auto[TokenHashSt]	49967597	1			T1	10		T2	854		T4	200
auto[0]	auto[FlashRmaSt]	38322	1			T2	8		T4	6		T12	49
auto[0]	auto[TokenCheck0St]	13885	1			T2	8		T4	6		T12	15
auto[0]	auto[TokenCheck1St]	10382	1			T2	8		T4	6		T12	8
auto[0]	auto[TransProgSt]	554900	1			T2	103		T4	60		T12	16
auto[0]	auto[PostTransSt]	13505161	1			T1	1110		T2	983		T3	431
auto[0]	auto[ScrapSt]	201589	1			T21	9		T37	1626		T27	3
auto[0]	auto[EscalateSt]	5892200	1			T3	452		T4	1581		T12	127
auto[0]	auto[InvalidSt]	12691311	1			T4	1300		T31	662		T35	6011
auto[1]	auto[ResetSt]	186	1			T21	3		T27	5		T67	3
auto[1]	auto[IdleSt]	118	1			T27	2		T67	4		T65	2
auto[1]	auto[ClkMuxSt]	21	1			T65	1		T66	1		T217	1
auto[1]	auto[CntIncrSt]	34	1			T27	1		T65	1		T20	1
auto[1]	auto[CntProgSt]	714	1			T21	25		T27	22		T67	3
auto[1]	auto[TransCheckSt]	61	1			T21	1		T27	1		T67	1
auto[1]	auto[TokenHashSt]	544	1			T21	9		T27	5		T67	11
auto[1]	auto[FlashRmaSt]	36	1			T21	1		T68	1		T20	2
auto[1]	auto[TokenCheck0St]	44	1			T21	1		T27	1		T20	1
auto[1]	auto[TokenCheck1St]	10	1			T65	1		T218	2		T215	1
auto[1]	auto[TransProgSt]	542	1			T21	12		T27	14		T67	2
auto[1]	auto[PostTransSt]	2981	1			T3	4		T12	4		T22	10
auto[1]	auto[ScrapSt]	42	1			T21	3		T27	1		T67	1
auto[1]	auto[EscalateSt]	1503940	1			T3	392		T4	294		T12	392
auto[1]	auto[InvalidSt]	7857	1			T4	3		T31	2		T35	4