Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63185377

1

T1

9115

T2

1393

T3

6426

auto[1]

1154743

1

T3

198

T4

693

T12

2574

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63185103

1

T1

9115

T2

1393

T3

6426

auto[1]

1155017

1

T3

198

T4

693

T12

2277

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5675011	1			T1	1118		T2	73		T3	1040
auto[IdleSt]	16547719	1			T1	1086		T2	77		T3	1552
auto[ClkMuxSt]	29391	1			T1	11		T2	1		T3	5
auto[CntIncrSt]	29240	1			T1	11		T2	1		T3	5
auto[CntProgSt]	1275568	1			T1	22		T2	10		T3	130
auto[TransCheckSt]	23108	1			T1	11		T2	1		T3	5
auto[TokenHashSt]	18859624	1			T1	5747		T2	45		T3	56
auto[FlashRmaSt]	27049	1			T1	41		T3	5		T13	22
auto[TokenCheck0St]	10055	1			T1	11		T3	5		T13	17
auto[TokenCheck1St]	7204	1			T1	11		T3	5		T13	9
auto[TransProgSt]	282346	1			T1	22		T3	141		T13	159
auto[PostTransSt]	9403585	1			T1	994		T2	1185		T3	1509
auto[ScrapSt]	105512	1			T1	30		T14	4		T5	415
auto[EscalateSt]	4763850	1			T3	1157		T4	1959		T12	6830
auto[InvalidSt]	7299457	1			T3	1008		T12	6576		T6	4121

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1401	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7299457	1			T3	1008		T12	6576		T6	4121
EscalateSt	4763850	1			T3	1157		T4	1959		T12	6830
ScrapSt	105512	1			T1	30		T14	4		T5	415
PostTransSt	9403585	1			T1	994		T2	1185		T3	1509
TransProgSt	282346	1			T1	22		T3	141		T13	159
TokenCheck1St	7204	1			T1	11		T3	5		T13	9
TokenCheck0St	10055	1			T1	11		T3	5		T13	17
FlashRmaSt	27049	1			T1	41		T3	5		T13	22
TokenHashSt	18859624	1			T1	5747		T2	45		T3	56
TransCheckSt	23108	1			T1	11		T2	1		T3	5
CntProgSt	1275568	1			T1	22		T2	10		T3	130
CntIncrSt	29240	1			T1	11		T2	1		T3	5
ClkMuxSt	29391	1			T1	11		T2	1		T3	5
IdleSt	16547719	1			T1	1086		T2	77		T3	1552
ResetSt	5675011	1			T1	1118		T2	73		T3	1040
arcs[ResetSt=>IdleSt]	43233	1			T1	12		T2	1		T3	11
arcs[IdleSt=>ScrapSt]	222	1			T1	1		T14	1		T5	1
arcs[IdleSt=>ClkMuxSt]	29274	1			T1	11		T2	1		T3	5
arcs[ClkMuxSt=>CntIncrSt]	29240	1			T1	11		T2	1		T3	5
arcs[CntIncrSt=>PostTransSt]	1453	1			T13	12		T22	15		T27	7
arcs[CntIncrSt=>CntProgSt]	27711	1			T1	11		T2	1		T3	5
arcs[CntProgSt=>PostTransSt]	3523	1			T4	14		T13	16		T7	14
arcs[CntProgSt=>TransCheckSt]	23108	1			T1	11		T2	1		T3	5
arcs[TransCheckSt=>PostTransSt]	3214	1			T13	10		T20	34		T22	10
arcs[TransCheckSt=>TokenHashSt]	19783	1			T1	11		T2	1		T3	5
arcs[TokenHashSt=>PostTransSt]	8873	1			T2	1		T13	31		T20	5
arcs[TokenHashSt=>FlashRmaSt]	10095	1			T1	11		T3	5		T13	17
arcs[FlashRmaSt=>TokenCheck0St]	10055	1			T1	11		T3	5		T13	17
arcs[TokenCheck0St=>PostTransSt]	2801	1			T13	8		T20	20		T21	6
arcs[TokenCheck0St=>TokenCheck1St]	7204	1			T1	11		T3	5		T13	9
arcs[TokenCheck1St=>PostTransSt]	579	1			T13	1		T20	13		T21	2
arcs[TransProgSt=>PostTransSt]	5780	1			T1	11		T3	5		T13	8
arcs[IdleSt=>EscalateSt]	166	1			T57	13		T58	4		T59	4
arcs[ClkMuxSt=>EscalateSt]	34	1			T57	2		T58	2		T59	3
arcs[CntIncrSt=>EscalateSt]	76	1			T25	4		T57	2		T60	1
arcs[CntProgSt=>EscalateSt]	1080	1			T14	37		T25	37		T57	8
arcs[TransCheckSt=>EscalateSt]	111	1			T57	5		T59	6		T64	5
arcs[TokenHashSt=>EscalateSt]	815	1			T14	7		T25	8		T57	30
arcs[FlashRmaSt=>EscalateSt]	40	1			T14	2		T57	1		T60	2
arcs[TokenCheck0St=>EscalateSt]	50	1			T14	1		T25	3		T58	1
arcs[TokenCheck1St=>EscalateSt]	33	1			T57	1		T58	2		T59	3
arcs[TransProgSt=>EscalateSt]	812	1			T14	22		T25	22		T57	10
arcs[PostTransSt=>EscalateSt]	3856	1			T4	14		T13	16		T7	14
arcs[InvalidSt=>EscalateSt]	10144	1			T3	4		T12	49		T6	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5674858	1			T1	1118		T2	73		T3	1040
auto[0]	auto[IdleSt]	16547616	1			T1	1086		T2	77		T3	1552
auto[0]	auto[ClkMuxSt]	29368	1			T1	11		T2	1		T3	5
auto[0]	auto[CntIncrSt]	29185	1			T1	11		T2	1		T3	5
auto[0]	auto[CntProgSt]	1274851	1			T1	22		T2	10		T3	130
auto[0]	auto[TransCheckSt]	23030	1			T1	11		T2	1		T3	5
auto[0]	auto[TokenHashSt]	18859081	1			T1	5747		T2	45		T3	56
auto[0]	auto[FlashRmaSt]	27019	1			T1	41		T3	5		T13	22
auto[0]	auto[TokenCheck0St]	10022	1			T1	11		T3	5		T13	17
auto[0]	auto[TokenCheck1St]	7182	1			T1	11		T3	5		T13	9
auto[0]	auto[TransProgSt]	281781	1			T1	22		T3	141		T13	159
auto[0]	auto[PostTransSt]	9401601	1			T1	994		T2	1185		T3	1509
auto[0]	auto[ScrapSt]	105479	1			T1	30		T14	4		T5	415
auto[0]	auto[EscalateSt]	3618490	1			T3	961		T4	1273		T12	4282
auto[0]	auto[InvalidSt]	7294413	1			T3	1006		T12	6550		T6	4120
auto[1]	auto[ResetSt]	153	1			T14	1		T25	5		T57	5
auto[1]	auto[IdleSt]	103	1			T57	9		T58	2		T59	3
auto[1]	auto[ClkMuxSt]	23	1			T57	2		T58	2		T59	2
auto[1]	auto[CntIncrSt]	55	1			T25	3		T57	1		T60	1
auto[1]	auto[CntProgSt]	717	1			T14	25		T25	24		T57	7
auto[1]	auto[TransCheckSt]	78	1			T57	2		T59	4		T64	4
auto[1]	auto[TokenHashSt]	543	1			T14	4		T25	7		T57	25
auto[1]	auto[FlashRmaSt]	30	1			T14	2		T57	1		T60	2
auto[1]	auto[TokenCheck0St]	33	1			T14	1		T25	2		T58	1
auto[1]	auto[TokenCheck1St]	22	1			T57	1		T58	1		T59	3
auto[1]	auto[TransProgSt]	565	1			T14	13		T25	17		T57	6
auto[1]	auto[PostTransSt]	1984	1			T4	7		T13	7		T7	5
auto[1]	auto[ScrapSt]	33	1			T58	2		T64	3		T235	1
auto[1]	auto[EscalateSt]	1145360	1			T3	196		T4	686		T12	2548
auto[1]	auto[InvalidSt]	5044	1			T3	2		T12	26		T6	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5674857	1			T1	1118		T2	73		T3	1040
auto[0]	auto[IdleSt]	16547606	1			T1	1086		T2	77		T3	1552
auto[0]	auto[ClkMuxSt]	29367	1			T1	11		T2	1		T3	5
auto[0]	auto[CntIncrSt]	29188	1			T1	11		T2	1		T3	5
auto[0]	auto[CntProgSt]	1274861	1			T1	22		T2	10		T3	130
auto[0]	auto[TransCheckSt]	23034	1			T1	11		T2	1		T3	5
auto[0]	auto[TokenHashSt]	18859083	1			T1	5747		T2	45		T3	56
auto[0]	auto[FlashRmaSt]	27022	1			T1	41		T3	5		T13	22
auto[0]	auto[TokenCheck0St]	10023	1			T1	11		T3	5		T13	17
auto[0]	auto[TokenCheck1St]	7179	1			T1	11		T3	5		T13	9
auto[0]	auto[TransProgSt]	281800	1			T1	22		T3	141		T13	159
auto[0]	auto[PostTransSt]	9401612	1			T1	994		T2	1185		T3	1509
auto[0]	auto[ScrapSt]	105483	1			T1	30		T14	3		T5	415
auto[0]	auto[EscalateSt]	3618230	1			T3	961		T4	1273		T12	4576
auto[0]	auto[InvalidSt]	7294357	1			T3	1006		T12	6553		T6	4118
auto[1]	auto[ResetSt]	154	1			T14	2		T25	4		T57	2
auto[1]	auto[IdleSt]	113	1			T57	9		T58	4		T59	1
auto[1]	auto[ClkMuxSt]	24	1			T57	2		T58	2		T59	2
auto[1]	auto[CntIncrSt]	52	1			T25	2		T57	1		T58	2
auto[1]	auto[CntProgSt]	707	1			T14	26		T25	24		T57	5
auto[1]	auto[TransCheckSt]	74	1			T57	4		T59	6		T64	5
auto[1]	auto[TokenHashSt]	541	1			T14	6		T25	4		T57	15
auto[1]	auto[FlashRmaSt]	27	1			T14	1		T60	2		T64	1
auto[1]	auto[TokenCheck0St]	32	1			T25	3		T58	1		T59	2
auto[1]	auto[TokenCheck1St]	25	1			T58	1		T59	2		T235	1
auto[1]	auto[TransProgSt]	546	1			T14	15		T25	16		T57	6
auto[1]	auto[PostTransSt]	1973	1			T4	7		T13	9		T7	9
auto[1]	auto[ScrapSt]	29	1			T14	1		T25	1		T60	1
auto[1]	auto[EscalateSt]	1145620	1			T3	196		T4	686		T12	2254
auto[1]	auto[InvalidSt]	5100	1			T3	2		T12	23		T6	3