Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.16 97.92 95.84 93.40 100.00 98.52 98.51 95.94


Total tests in report: 1004
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.25 67.25 82.09 82.09 52.87 52.87 58.00 58.00 50.00 50.00 82.63 82.63 91.79 91.79 53.36 53.36 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3545163135
77.82 10.58 88.84 6.75 80.50 27.63 74.36 16.37 54.76 4.76 89.62 6.99 93.78 1.99 62.90 9.54 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.321315621
83.09 5.27 89.09 0.25 81.42 0.92 76.47 2.11 80.95 26.19 91.10 1.48 94.03 0.25 68.55 5.65 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.4259898149
86.01 2.92 95.48 6.39 81.61 0.18 83.07 6.60 80.95 0.00 93.22 2.12 94.03 0.00 73.67 5.12 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.4177758713
87.39 1.39 95.54 0.05 81.98 0.37 83.07 0.00 88.10 7.14 93.43 0.21 94.03 0.00 75.62 1.94 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.472858622
88.78 1.38 96.55 1.01 85.12 3.14 83.37 0.30 88.10 0.00 94.92 1.48 94.78 0.75 78.62 3.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3685015935
90.12 1.34 96.80 0.25 87.34 2.22 83.47 0.10 88.10 0.00 95.55 0.64 96.02 1.24 83.57 4.95 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2304540018
91.13 1.01 96.91 0.10 87.34 0.00 83.47 0.00 92.86 4.76 95.97 0.42 96.02 0.00 85.34 1.77 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.2766390867
92.11 0.98 96.96 0.05 87.89 0.55 86.71 3.24 92.86 0.00 96.19 0.21 96.02 0.00 88.16 2.83 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4070348204
92.79 0.68 96.96 0.00 88.72 0.83 86.71 0.00 95.24 2.38 96.40 0.21 96.27 0.25 89.22 1.06 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3257387511
93.43 0.64 97.01 0.05 89.37 0.65 86.93 0.22 97.62 2.38 96.61 0.21 96.52 0.25 89.93 0.71 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.388647414
93.95 0.53 97.06 0.05 91.31 1.94 86.93 0.00 97.62 0.00 97.25 0.64 96.52 0.00 90.99 1.06 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3062896707
94.38 0.43 97.06 0.00 91.31 0.00 89.42 2.49 97.62 0.00 97.25 0.00 96.52 0.00 91.52 0.53 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1992822425
94.74 0.35 97.06 0.00 91.40 0.09 89.42 0.00 100.00 2.38 97.25 0.00 96.52 0.00 91.52 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1580649117
95.09 0.35 97.41 0.36 92.33 0.92 90.05 0.63 100.00 0.00 97.25 0.00 96.52 0.00 92.05 0.53 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1874877960
95.34 0.25 97.51 0.10 92.70 0.37 90.05 0.00 100.00 0.00 97.46 0.21 96.52 0.00 93.11 1.06 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.225471074
95.57 0.24 97.51 0.00 93.07 0.37 91.16 1.11 100.00 0.00 97.46 0.00 96.52 0.00 93.29 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1848351944
95.79 0.21 97.51 0.00 93.07 0.00 91.16 0.00 100.00 0.00 97.46 0.00 98.01 1.49 93.29 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3080419382
95.97 0.19 97.62 0.10 93.07 0.00 91.80 0.64 100.00 0.00 97.67 0.21 98.01 0.00 93.64 0.35 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.369408823
96.15 0.17 97.77 0.15 93.07 0.00 91.84 0.04 100.00 0.00 98.09 0.42 98.26 0.25 93.99 0.35 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.453575830
96.29 0.15 97.77 0.00 93.07 0.00 92.69 0.85 100.00 0.00 98.09 0.00 98.26 0.00 94.17 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.3354583039
96.43 0.14 97.82 0.05 93.07 0.00 92.87 0.18 100.00 0.00 98.31 0.21 98.26 0.00 94.70 0.53 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.55556074
96.53 0.10 97.92 0.10 93.44 0.37 92.87 0.00 100.00 0.00 98.52 0.21 98.26 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.181576878
96.61 0.08 97.92 0.00 93.81 0.37 92.87 0.00 100.00 0.00 98.52 0.00 98.26 0.00 94.88 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3151247100
96.67 0.06 97.92 0.00 94.09 0.28 92.87 0.00 100.00 0.00 98.52 0.00 98.26 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3746437779
96.73 0.05 97.92 0.00 94.45 0.37 92.87 0.00 100.00 0.00 98.52 0.00 98.26 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2113206327
96.76 0.04 97.92 0.00 94.73 0.28 92.87 0.00 100.00 0.00 98.52 0.00 98.26 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3750791772
96.80 0.04 97.92 0.00 94.73 0.00 93.14 0.26 100.00 0.00 98.52 0.00 98.26 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2834604664
96.84 0.04 97.92 0.00 94.73 0.00 93.14 0.00 100.00 0.00 98.52 0.00 98.51 0.25 95.05 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1050452282
96.87 0.04 97.92 0.00 94.73 0.00 93.21 0.07 100.00 0.00 98.52 0.00 98.51 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.2096775178
96.90 0.03 97.92 0.00 94.73 0.00 93.23 0.02 100.00 0.00 98.52 0.00 98.51 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3089430317
96.93 0.03 97.92 0.00 94.92 0.18 93.23 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3465095533
96.95 0.03 97.92 0.00 94.92 0.00 93.23 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1160168163
96.98 0.03 97.92 0.00 94.92 0.00 93.23 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.1577514771
97.00 0.03 97.92 0.00 94.92 0.00 93.23 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3835476774
97.03 0.02 97.92 0.00 94.92 0.00 93.39 0.16 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3991274223
97.04 0.01 97.92 0.00 95.01 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1616170497
97.05 0.01 97.92 0.00 95.10 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4185917988
97.07 0.01 97.92 0.00 95.19 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.713989662
97.08 0.01 97.92 0.00 95.29 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3034333328
97.09 0.01 97.92 0.00 95.38 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1892059558
97.11 0.01 97.92 0.00 95.47 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1859825476
97.12 0.01 97.92 0.00 95.56 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2936759832
97.13 0.01 97.92 0.00 95.66 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3093930449
97.15 0.01 97.92 0.00 95.75 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3115456205
97.16 0.01 97.92 0.00 95.84 0.09 93.39 0.00 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1412723551
97.16 0.01 97.92 0.00 95.84 0.00 93.40 0.01 100.00 0.00 98.52 0.00 98.51 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1327299083

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4234300935
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1242976804
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2066957287
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3030946474
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1573529238
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2852111061
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1706590881
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1690816597
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.128929772
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.667710212
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1008290266
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2426591112
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.925278308
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1206122466
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2990751021
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2037592133
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2720028446
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.738537096
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.507566816
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.573498574
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4053340577
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.799985471
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.576152204
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3698488507
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.856506451
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1319590466
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1259892456
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.658086434
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3828190274
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2094290813
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1384856694
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2830049007
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.35645841
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.417152577
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2215364334
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2283542546
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3203285817
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3144886543
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.563309725
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2091879305
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1361272889
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3651663906
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.168630325
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3424626663
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3737473734
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4141936455
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.76634284
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.166333225
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.365186379
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1767726169
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4269584338
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.55444451
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2006919445
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.2743945314
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.865080396
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.181196653
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.4216774414
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.662323440
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1820704294
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1110802446
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1148951181
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2354535627
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1136854276
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3620661665
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.32612719
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1299435041
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.2380343546
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.576871573
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2564095805
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3235638188
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.2269803407
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3936775452
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.413090644
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2243363814
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.4009879802
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Total test records in report: 1004
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3089430317 Feb 09 02:08:52 PM UTC 25 Feb 09 02:08:55 PM UTC 25 12467933 ps
T2 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2234815515 Feb 09 02:08:52 PM UTC 25 Feb 09 02:08:55 PM UTC 25 77034236 ps
T3 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.2836553497 Feb 09 02:08:52 PM UTC 25 Feb 09 02:08:57 PM UTC 25 201852984 ps
T4 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3991274223 Feb 09 02:08:52 PM UTC 25 Feb 09 02:09:00 PM UTC 25 86942360 ps
T12 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3545163135 Feb 09 02:08:52 PM UTC 25 Feb 09 02:09:03 PM UTC 25 451755911 ps
T13 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1160168163 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:07 PM UTC 25 48319136 ps
T14 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1874877960 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:07 PM UTC 25 52848311 ps
T15 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1903787155 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:08 PM UTC 25 60768574 ps
T16 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1740962836 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:08 PM UTC 25 14090574 ps
T17 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3697542176 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:08 PM UTC 25 122392992 ps
T5 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.752901269 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:10 PM UTC 25 385871584 ps
T6 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.106570632 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:10 PM UTC 25 174034248 ps
T22 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.369408823 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:10 PM UTC 25 311904692 ps
T24 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2563880332 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:12 PM UTC 25 1053527880 ps
T21 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.4259898149 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:13 PM UTC 25 1000649447 ps
T37 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3928113597 Feb 09 02:09:11 PM UTC 25 Feb 09 02:09:14 PM UTC 25 35851470 ps
T7 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3033546762 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:14 PM UTC 25 1950213170 ps
T11 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2709418799 Feb 09 02:09:09 PM UTC 25 Feb 09 02:09:15 PM UTC 25 172700751 ps
T31 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.55556074 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:16 PM UTC 25 112383573 ps
T25 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1998382916 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:16 PM UTC 25 489074127 ps
T34 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.851653637 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:17 PM UTC 25 1220133076 ps
T26 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1461640453 Feb 09 02:09:15 PM UTC 25 Feb 09 02:09:17 PM UTC 25 41332116 ps
T32 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.2096775178 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:18 PM UTC 25 3032506182 ps
T35 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.321315621 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:18 PM UTC 25 1344338530 ps
T8 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2997187632 Feb 09 02:09:08 PM UTC 25 Feb 09 02:09:18 PM UTC 25 613928150 ps
T9 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3685015935 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:19 PM UTC 25 5001577388 ps
T23 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.3543683599 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:19 PM UTC 25 217069404 ps
T27 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.59733705 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:21 PM UTC 25 342678187 ps
T45 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.4281411811 Feb 09 02:09:13 PM UTC 25 Feb 09 02:09:21 PM UTC 25 384867479 ps
T46 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.3617378061 Feb 09 02:09:17 PM UTC 25 Feb 09 02:09:21 PM UTC 25 31688875 ps
T47 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3835476774 Feb 09 02:09:19 PM UTC 25 Feb 09 02:09:22 PM UTC 25 40194370 ps
T29 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.1924228482 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:22 PM UTC 25 3176738234 ps
T36 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1327299083 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:23 PM UTC 25 1386957554 ps
T28 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.794016195 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:25 PM UTC 25 663138395 ps
T48 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2031477391 Feb 09 02:09:15 PM UTC 25 Feb 09 02:09:26 PM UTC 25 169360176 ps
T50 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2531004295 Feb 09 02:09:10 PM UTC 25 Feb 09 02:09:26 PM UTC 25 1080596721 ps
T30 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.400339448 Feb 09 02:09:10 PM UTC 25 Feb 09 02:09:26 PM UTC 25 1365353089 ps
T57 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.1082212582 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:27 PM UTC 25 386378655 ps
T49 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4070348204 Feb 09 02:08:52 PM UTC 25 Feb 09 02:09:27 PM UTC 25 255714045 ps
T75 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3691716647 Feb 09 02:09:20 PM UTC 25 Feb 09 02:09:28 PM UTC 25 358336434 ps
T225 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1643179014 Feb 09 02:09:10 PM UTC 25 Feb 09 02:09:28 PM UTC 25 2664388852 ps
T33 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.657524738 Feb 09 02:09:17 PM UTC 25 Feb 09 02:09:29 PM UTC 25 755616321 ps
T64 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.3484310529 Feb 09 02:09:22 PM UTC 25 Feb 09 02:09:29 PM UTC 25 665458341 ps
T221 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.2300583529 Feb 09 02:09:20 PM UTC 25 Feb 09 02:09:29 PM UTC 25 1290390100 ps
T131 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.1113297254 Feb 09 02:09:17 PM UTC 25 Feb 09 02:09:29 PM UTC 25 412308941 ps
T67 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.157980235 Feb 09 02:09:17 PM UTC 25 Feb 09 02:09:30 PM UTC 25 889407778 ps
T99 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.4274919435 Feb 09 02:09:28 PM UTC 25 Feb 09 02:09:31 PM UTC 25 106519836 ps
T73 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.453575830 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:31 PM UTC 25 773771377 ps
T226 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.122352871 Feb 09 02:09:28 PM UTC 25 Feb 09 02:09:31 PM UTC 25 49720774 ps
T227 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1056656289 Feb 09 02:09:29 PM UTC 25 Feb 09 02:09:31 PM UTC 25 16467744 ps
T228 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.3663070688 Feb 09 02:09:29 PM UTC 25 Feb 09 02:09:32 PM UTC 25 184159585 ps
T229 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3719585260 Feb 09 02:09:31 PM UTC 25 Feb 09 02:09:33 PM UTC 25 103216273 ps
T51 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.563052431 Feb 09 02:09:24 PM UTC 25 Feb 09 02:09:35 PM UTC 25 274956298 ps
T10 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2016988365 Feb 09 02:09:22 PM UTC 25 Feb 09 02:09:36 PM UTC 25 401274698 ps
T38 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.3493776122 Feb 09 02:09:33 PM UTC 25 Feb 09 02:09:37 PM UTC 25 567183447 ps
T91 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2932698630 Feb 09 02:09:31 PM UTC 25 Feb 09 02:09:40 PM UTC 25 498999628 ps
T92 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1420083533 Feb 09 02:09:09 PM UTC 25 Feb 09 02:09:40 PM UTC 25 4498303775 ps
T95 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.1341073936 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:40 PM UTC 25 2695437843 ps
T230 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2847383421 Feb 09 02:09:32 PM UTC 25 Feb 09 02:09:41 PM UTC 25 854659650 ps
T94 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2352131654 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:41 PM UTC 25 306587161 ps
T58 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3176988995 Feb 09 02:09:24 PM UTC 25 Feb 09 02:09:42 PM UTC 25 1366333238 ps
T76 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2513772245 Feb 09 02:09:31 PM UTC 25 Feb 09 02:09:42 PM UTC 25 1518212398 ps
T65 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.472858622 Feb 09 02:09:31 PM UTC 25 Feb 09 02:09:43 PM UTC 25 891060156 ps
T231 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3019061733 Feb 09 02:09:22 PM UTC 25 Feb 09 02:09:44 PM UTC 25 680944561 ps
T232 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.174245135 Feb 09 02:09:42 PM UTC 25 Feb 09 02:09:44 PM UTC 25 14196071 ps
T96 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.2664511841 Feb 09 02:09:31 PM UTC 25 Feb 09 02:09:44 PM UTC 25 322833453 ps
T233 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3787058487 Feb 09 02:09:43 PM UTC 25 Feb 09 02:09:45 PM UTC 25 17432385 ps
T77 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2297836115 Feb 09 02:09:34 PM UTC 25 Feb 09 02:09:47 PM UTC 25 649222989 ps
T219 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3939408576 Feb 09 02:09:29 PM UTC 25 Feb 09 02:09:47 PM UTC 25 257854355 ps
T93 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.805323957 Feb 09 02:09:43 PM UTC 25 Feb 09 02:09:48 PM UTC 25 301696257 ps
T97 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.3675912339 Feb 09 02:09:11 PM UTC 25 Feb 09 02:09:48 PM UTC 25 123376352 ps
T106 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.2985607296 Feb 09 02:09:15 PM UTC 25 Feb 09 02:09:48 PM UTC 25 149257461 ps
T54 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.225471074 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:49 PM UTC 25 4734539387 ps
T107 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1153684920 Feb 09 02:09:45 PM UTC 25 Feb 09 02:09:50 PM UTC 25 183734938 ps
T108 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1279120988 Feb 09 02:09:48 PM UTC 25 Feb 09 02:09:50 PM UTC 25 12255457 ps
T109 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3221545529 Feb 09 02:09:25 PM UTC 25 Feb 09 02:09:52 PM UTC 25 14316969761 ps
T110 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.4207585435 Feb 09 02:09:49 PM UTC 25 Feb 09 02:09:53 PM UTC 25 65745060 ps
T111 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.3354583039 Feb 09 02:09:05 PM UTC 25 Feb 09 02:09:53 PM UTC 25 21636292278 ps
T112 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.820868437 Feb 09 02:09:32 PM UTC 25 Feb 09 02:09:53 PM UTC 25 2747890124 ps
T113 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3185168311 Feb 09 02:09:45 PM UTC 25 Feb 09 02:09:53 PM UTC 25 302426178 ps
T18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.2766390867 Feb 09 02:09:37 PM UTC 25 Feb 09 02:09:54 PM UTC 25 2001716023 ps
T234 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1714604099 Feb 09 02:09:40 PM UTC 25 Feb 09 02:09:54 PM UTC 25 347020405 ps
T224 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1993568157 Feb 09 02:09:20 PM UTC 25 Feb 09 02:09:56 PM UTC 25 5191002649 ps
T68 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.1579509199 Feb 09 02:09:46 PM UTC 25 Feb 09 02:09:57 PM UTC 25 221877254 ps
T39 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2376872872 Feb 09 02:09:51 PM UTC 25 Feb 09 02:09:59 PM UTC 25 496927670 ps
T190 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1834758192 Feb 09 02:09:47 PM UTC 25 Feb 09 02:09:59 PM UTC 25 248000647 ps
T19 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.4177758713 Feb 09 02:09:37 PM UTC 25 Feb 09 02:10:00 PM UTC 25 1781757937 ps
T235 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1592496060 Feb 09 02:09:58 PM UTC 25 Feb 09 02:10:00 PM UTC 25 36648523 ps
T236 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3156848806 Feb 09 02:09:45 PM UTC 25 Feb 09 02:10:01 PM UTC 25 342438723 ps
T237 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3133982330 Feb 09 02:09:36 PM UTC 25 Feb 09 02:10:02 PM UTC 25 824591596 ps
T238 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.3421618786 Feb 09 02:09:59 PM UTC 25 Feb 09 02:10:02 PM UTC 25 33783636 ps
T239 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2230392394 Feb 09 02:10:00 PM UTC 25 Feb 09 02:10:02 PM UTC 25 45823543 ps
T240 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3787148589 Feb 09 02:09:50 PM UTC 25 Feb 09 02:10:04 PM UTC 25 2481407289 ps
T241 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.929664933 Feb 09 02:10:01 PM UTC 25 Feb 09 02:10:06 PM UTC 25 249098906 ps
T70 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.4049740239 Feb 09 02:09:05 PM UTC 25 Feb 09 02:10:07 PM UTC 25 2303864942 ps
T242 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2748228380 Feb 09 02:09:55 PM UTC 25 Feb 09 02:10:07 PM UTC 25 1190915022 ps
T243 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2834604664 Feb 09 02:09:29 PM UTC 25 Feb 09 02:10:07 PM UTC 25 888794852 ps
T212 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3887527192 Feb 09 02:10:05 PM UTC 25 Feb 09 02:10:07 PM UTC 25 22454724 ps
T191 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2737032477 Feb 09 02:09:53 PM UTC 25 Feb 09 02:10:08 PM UTC 25 3672429578 ps
T244 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3251210133 Feb 09 02:09:55 PM UTC 25 Feb 09 02:10:10 PM UTC 25 1438115629 ps
T220 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2816519926 Feb 09 02:09:50 PM UTC 25 Feb 09 02:10:10 PM UTC 25 439955193 ps
T245 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2926387542 Feb 09 02:10:01 PM UTC 25 Feb 09 02:10:11 PM UTC 25 115458135 ps
T246 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2979402743 Feb 09 02:10:09 PM UTC 25 Feb 09 02:10:12 PM UTC 25 32180205 ps
T247 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1988335116 Feb 09 02:10:08 PM UTC 25 Feb 09 02:10:13 PM UTC 25 215131490 ps
T248 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3730134854 Feb 09 02:09:55 PM UTC 25 Feb 09 02:10:14 PM UTC 25 304879875 ps
T98 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.552603019 Feb 09 02:09:28 PM UTC 25 Feb 09 02:10:14 PM UTC 25 116686190 ps
T249 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2573844186 Feb 09 02:10:07 PM UTC 25 Feb 09 02:10:17 PM UTC 25 1476787948 ps
T250 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2966166563 Feb 09 02:10:10 PM UTC 25 Feb 09 02:10:17 PM UTC 25 620497382 ps
T251 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3270268420 Feb 09 02:10:04 PM UTC 25 Feb 09 02:10:17 PM UTC 25 285206032 ps
T20 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.4032162000 Feb 09 02:10:04 PM UTC 25 Feb 09 02:10:17 PM UTC 25 285062160 ps
T252 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1573480903 Feb 09 02:10:04 PM UTC 25 Feb 09 02:10:19 PM UTC 25 526638909 ps
T253 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.680171100 Feb 09 02:10:17 PM UTC 25 Feb 09 02:10:19 PM UTC 25 16492759 ps
T254 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4216277298 Feb 09 02:10:18 PM UTC 25 Feb 09 02:10:21 PM UTC 25 25194991 ps
T255 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1324409376 Feb 09 02:09:44 PM UTC 25 Feb 09 02:10:21 PM UTC 25 212257229 ps
T256 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.4032862493 Feb 09 02:10:17 PM UTC 25 Feb 09 02:10:21 PM UTC 25 63080596 ps
T257 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1420540017 Feb 09 02:10:12 PM UTC 25 Feb 09 02:10:24 PM UTC 25 294004313 ps
T258 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.271685912 Feb 09 02:09:53 PM UTC 25 Feb 09 02:10:25 PM UTC 25 780525370 ps
T259 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.1334852022 Feb 09 02:10:25 PM UTC 25 Feb 09 02:10:27 PM UTC 25 36629569 ps
T260 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1535259269 Feb 09 02:10:21 PM UTC 25 Feb 09 02:10:27 PM UTC 25 602148241 ps
T261 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.633568490 Feb 09 02:10:13 PM UTC 25 Feb 09 02:10:29 PM UTC 25 909039486 ps
T222 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1159716496 Feb 09 02:10:08 PM UTC 25 Feb 09 02:10:29 PM UTC 25 2026320327 ps
T223 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3564264110 Feb 09 02:09:32 PM UTC 25 Feb 09 02:10:30 PM UTC 25 8334049038 ps
T262 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.501469259 Feb 09 02:10:22 PM UTC 25 Feb 09 02:10:31 PM UTC 25 246897803 ps
T263 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.512206104 Feb 09 02:09:20 PM UTC 25 Feb 09 02:10:31 PM UTC 25 6554743585 ps
T192 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2270242005 Feb 09 02:10:22 PM UTC 25 Feb 09 02:10:32 PM UTC 25 490337375 ps
T264 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.4224479571 Feb 09 02:10:14 PM UTC 25 Feb 09 02:10:35 PM UTC 25 1919421694 ps
T265 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2326716969 Feb 09 02:09:50 PM UTC 25 Feb 09 02:10:36 PM UTC 25 5296586441 ps
T266 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3603330226 Feb 09 02:10:26 PM UTC 25 Feb 09 02:10:37 PM UTC 25 5287404293 ps
T267 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.525987323 Feb 09 02:10:21 PM UTC 25 Feb 09 02:10:37 PM UTC 25 68088526 ps
T268 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.2509266165 Feb 09 02:09:05 PM UTC 25 Feb 09 02:10:38 PM UTC 25 4204978943 ps
T71 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.1182710222 Feb 09 02:10:22 PM UTC 25 Feb 09 02:10:38 PM UTC 25 3380641155 ps
T269 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2829929886 Feb 09 02:10:30 PM UTC 25 Feb 09 02:10:40 PM UTC 25 477386243 ps
T270 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3705292176 Feb 09 02:10:32 PM UTC 25 Feb 09 02:10:40 PM UTC 25 285314292 ps
T271 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.82048660 Feb 09 02:10:38 PM UTC 25 Feb 09 02:10:40 PM UTC 25 65370158 ps
T272 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1299435041 Feb 09 02:10:39 PM UTC 25 Feb 09 02:10:42 PM UTC 25 23173532 ps
T40 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2411721593 Feb 09 02:10:31 PM UTC 25 Feb 09 02:10:43 PM UTC 25 1998647887 ps
T273 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3925774870 Feb 09 02:10:12 PM UTC 25 Feb 09 02:10:44 PM UTC 25 4597954012 ps
T74 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1401987726 Feb 09 02:10:39 PM UTC 25 Feb 09 02:10:46 PM UTC 25 55507100 ps
T274 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1820704294 Feb 09 02:10:41 PM UTC 25 Feb 09 02:10:46 PM UTC 25 183218692 ps
T52 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.1546317824 Feb 09 02:09:50 PM UTC 25 Feb 09 02:10:47 PM UTC 25 11421179659 ps
T105 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.3399524080 Feb 09 02:09:42 PM UTC 25 Feb 09 02:10:48 PM UTC 25 415474639 ps
T78 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2710454714 Feb 09 02:10:32 PM UTC 25 Feb 09 02:10:48 PM UTC 25 4605445462 ps
T275 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.4055265209 Feb 09 02:10:34 PM UTC 25 Feb 09 02:10:48 PM UTC 25 348104144 ps
T276 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.2743945314 Feb 09 02:10:28 PM UTC 25 Feb 09 02:10:49 PM UTC 25 1589065035 ps
T277 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2702877837 Feb 09 02:10:47 PM UTC 25 Feb 09 02:10:49 PM UTC 25 12031821 ps
T278 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.181196653 Feb 09 02:10:47 PM UTC 25 Feb 09 02:10:49 PM UTC 25 69851117 ps
T279 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2899832795 Feb 09 02:09:22 PM UTC 25 Feb 09 02:10:50 PM UTC 25 3430486664 ps
T280 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2015105519 Feb 09 02:10:36 PM UTC 25 Feb 09 02:10:51 PM UTC 25 280665008 ps
T281 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.32612719 Feb 09 02:10:41 PM UTC 25 Feb 09 02:10:52 PM UTC 25 142071628 ps
T282 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.3991526242 Feb 09 02:10:42 PM UTC 25 Feb 09 02:10:52 PM UTC 25 2597088367 ps
T283 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.444919726 Feb 09 02:10:33 PM UTC 25 Feb 09 02:10:53 PM UTC 25 1546012846 ps
T284 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.1765026905 Feb 09 02:09:32 PM UTC 25 Feb 09 02:10:54 PM UTC 25 12057166146 ps
T285 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1110802446 Feb 09 02:10:45 PM UTC 25 Feb 09 02:10:56 PM UTC 25 818498733 ps
T193 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.2985624195 Feb 09 02:10:50 PM UTC 25 Feb 09 02:10:56 PM UTC 25 93639407 ps
T69 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.388647414 Feb 09 02:09:57 PM UTC 25 Feb 09 02:10:57 PM UTC 25 465722622 ps
T216 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1136854276 Feb 09 02:10:43 PM UTC 25 Feb 09 02:10:58 PM UTC 25 673618270 ps
T286 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3634793743 Feb 09 02:10:55 PM UTC 25 Feb 09 02:10:58 PM UTC 25 97679736 ps
T287 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.208557315 Feb 09 02:10:57 PM UTC 25 Feb 09 02:11:00 PM UTC 25 30413627 ps
T288 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1505982984 Feb 09 02:10:18 PM UTC 25 Feb 09 02:11:00 PM UTC 25 790940417 ps
T289 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1047757515 Feb 09 02:10:56 PM UTC 25 Feb 09 02:11:01 PM UTC 25 52223456 ps
T290 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.662323440 Feb 09 02:10:49 PM UTC 25 Feb 09 02:11:01 PM UTC 25 643505350 ps
T291 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2354535627 Feb 09 02:10:52 PM UTC 25 Feb 09 02:11:01 PM UTC 25 871275865 ps
T292 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.2605313217 Feb 09 02:10:01 PM UTC 25 Feb 09 02:11:01 PM UTC 25 319230309 ps
T293 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.2883837760 Feb 09 02:10:49 PM UTC 25 Feb 09 02:11:01 PM UTC 25 1346799539 ps
T294 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3407405278 Feb 09 02:10:59 PM UTC 25 Feb 09 02:11:02 PM UTC 25 23018204 ps
T41 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.3655291790 Feb 09 02:10:49 PM UTC 25 Feb 09 02:11:04 PM UTC 25 2805813405 ps
T55 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.2430961791 Feb 09 02:10:08 PM UTC 25 Feb 09 02:11:04 PM UTC 25 4188772425 ps
T295 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.117766723 Feb 09 02:10:59 PM UTC 25 Feb 09 02:11:04 PM UTC 25 65314690 ps
T213 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.822199940 Feb 09 02:11:02 PM UTC 25 Feb 09 02:11:05 PM UTC 25 14370720 ps
T296 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1148951181 Feb 09 02:10:52 PM UTC 25 Feb 09 02:11:05 PM UTC 25 1039232725 ps
T297 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.979141182 Feb 09 02:10:53 PM UTC 25 Feb 09 02:11:06 PM UTC 25 777720033 ps
T103 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.2508808295 Feb 09 02:09:05 PM UTC 25 Feb 09 02:11:11 PM UTC 25 18285870231 ps
T298 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2564095805 Feb 09 02:11:03 PM UTC 25 Feb 09 02:11:12 PM UTC 25 458710112 ps
T299 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.865080396 Feb 09 02:10:50 PM UTC 25 Feb 09 02:11:14 PM UTC 25 890768460 ps
T300 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.413090644 Feb 09 02:11:02 PM UTC 25 Feb 09 02:11:15 PM UTC 25 235094743 ps
T301 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.599997262 Feb 09 02:11:01 PM UTC 25 Feb 09 02:11:15 PM UTC 25 216506733 ps
T53 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3287359457 Feb 09 02:10:30 PM UTC 25 Feb 09 02:11:15 PM UTC 25 4934528162 ps
T302 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.1740974048 Feb 09 02:11:01 PM UTC 25 Feb 09 02:11:16 PM UTC 25 379655571 ps
T303 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.2269803407 Feb 09 02:11:02 PM UTC 25 Feb 09 02:11:16 PM UTC 25 2840495550 ps
T304 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.922185719 Feb 09 02:11:07 PM UTC 25 Feb 09 02:11:16 PM UTC 25 238176405 ps
T305 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2243363814 Feb 09 02:11:02 PM UTC 25 Feb 09 02:11:17 PM UTC 25 790519900 ps
T306 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.1008306453 Feb 09 02:11:06 PM UTC 25 Feb 09 02:11:18 PM UTC 25 2319855699 ps
T307 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3905304548 Feb 09 02:11:17 PM UTC 25 Feb 09 02:11:19 PM UTC 25 241070859 ps
T308 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3249578386 Feb 09 02:11:17 PM UTC 25 Feb 09 02:11:19 PM UTC 25 15940890 ps
T309 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1815555062 Feb 09 02:11:17 PM UTC 25 Feb 09 02:11:21 PM UTC 25 40695411 ps
T310 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.919727593 Feb 09 02:11:18 PM UTC 25 Feb 09 02:11:22 PM UTC 25 270186434 ps
T311 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.4009879802 Feb 09 02:11:07 PM UTC 25 Feb 09 02:11:22 PM UTC 25 234274554 ps
T312 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3558198876 Feb 09 02:11:20 PM UTC 25 Feb 09 02:11:23 PM UTC 25 27780116 ps
T104 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1992822425 Feb 09 02:09:10 PM UTC 25 Feb 09 02:11:26 PM UTC 25 6753330940 ps
T313 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.1651216159 Feb 09 02:11:21 PM UTC 25 Feb 09 02:11:27 PM UTC 25 318465018 ps
T314 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3369499405 Feb 09 02:11:12 PM UTC 25 Feb 09 02:11:27 PM UTC 25 765278317 ps
T315 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3507500104 Feb 09 02:11:17 PM UTC 25 Feb 09 02:11:27 PM UTC 25 42782550 ps
T66 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.452573813 Feb 09 02:11:19 PM UTC 25 Feb 09 02:11:31 PM UTC 25 1265181718 ps
T316 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.317412061 Feb 09 02:10:57 PM UTC 25 Feb 09 02:11:32 PM UTC 25 777829281 ps
T317 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1553787801 Feb 09 02:11:23 PM UTC 25 Feb 09 02:11:32 PM UTC 25 209984024 ps
T42 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.2380343546 Feb 09 02:11:05 PM UTC 25 Feb 09 02:11:34 PM UTC 25 887529418 ps
T318 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1300112117 Feb 09 02:11:20 PM UTC 25 Feb 09 02:11:34 PM UTC 25 952775708 ps
T319 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.741569498 Feb 09 02:11:18 PM UTC 25 Feb 09 02:11:34 PM UTC 25 434542851 ps
T320 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1944288968 Feb 09 02:11:28 PM UTC 25 Feb 09 02:11:35 PM UTC 25 1793826650 ps
T43 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.23975371 Feb 09 02:11:28 PM UTC 25 Feb 09 02:11:36 PM UTC 25 5948650057 ps
T321 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2995466419 Feb 09 02:11:35 PM UTC 25 Feb 09 02:11:37 PM UTC 25 66228921 ps
T322 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1633367154 Feb 09 02:11:37 PM UTC 25 Feb 09 02:11:39 PM UTC 25 13543700 ps
T323 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3235638188 Feb 09 02:11:06 PM UTC 25 Feb 09 02:11:41 PM UTC 25 20040945593 ps
T324 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.4032827742 Feb 09 02:11:36 PM UTC 25 Feb 09 02:11:41 PM UTC 25 140123900 ps
T325 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.2970835652 Feb 09 02:10:28 PM UTC 25 Feb 09 02:11:41 PM UTC 25 3993890914 ps
T326 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3620661665 Feb 09 02:10:41 PM UTC 25 Feb 09 02:11:41 PM UTC 25 1027972443 ps
T327 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.3096670991 Feb 09 02:11:23 PM UTC 25 Feb 09 02:11:42 PM UTC 25 2616045485 ps
T328 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.2112461754 Feb 09 02:10:49 PM UTC 25 Feb 09 02:11:42 PM UTC 25 1707612191 ps
T329 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3824219196 Feb 09 02:11:33 PM UTC 25 Feb 09 02:11:44 PM UTC 25 244489346 ps
T330 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2719378524 Feb 09 02:10:08 PM UTC 25 Feb 09 02:11:45 PM UTC 25 2215103979 ps
T331 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.576871573 Feb 09 02:11:05 PM UTC 25 Feb 09 02:11:46 PM UTC 25 6647931536 ps
T332 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3481226162 Feb 09 02:11:41 PM UTC 25 Feb 09 02:11:46 PM UTC 25 180216498 ps
T333 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2686892212 Feb 09 02:11:17 PM UTC 25 Feb 09 02:11:47 PM UTC 25 197327534 ps
T334 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1469714991 Feb 09 02:11:40 PM UTC 25 Feb 09 02:11:48 PM UTC 25 113746535 ps
T335 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3309654202 Feb 09 02:11:32 PM UTC 25 Feb 09 02:11:50 PM UTC 25 329973971 ps
T336 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.2438662452 Feb 09 02:11:42 PM UTC 25 Feb 09 02:11:56 PM UTC 25 383477434 ps
T337 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3936775452 Feb 09 02:11:02 PM UTC 25 Feb 09 02:11:57 PM UTC 25 2468752140 ps
T44 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3227306475 Feb 09 02:11:46 PM UTC 25 Feb 09 02:11:57 PM UTC 25 1015929621 ps
T217 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1018821887 Feb 09 02:11:42 PM UTC 25 Feb 09 02:11:58 PM UTC 25 1489432729 ps
T338 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2331057490 Feb 09 02:11:58 PM UTC 25 Feb 09 02:12:00 PM UTC 25 29941847 ps
T339 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1246114893 Feb 09 02:11:58 PM UTC 25 Feb 09 02:12:01 PM UTC 25 52221224 ps
T340 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4202738942 Feb 09 02:11:59 PM UTC 25 Feb 09 02:12:01 PM UTC 25 22179610 ps
T341 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.3305041347 Feb 09 02:11:42 PM UTC 25 Feb 09 02:12:04 PM UTC 25 1131204111 ps
T342 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1243648280 Feb 09 02:11:48 PM UTC 25 Feb 09 02:12:05 PM UTC 25 280412528 ps
T343 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.4104944420 Feb 09 02:11:33 PM UTC 25 Feb 09 02:12:05 PM UTC 25 1221181403 ps
T344 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.3367650771 Feb 09 02:12:02 PM UTC 25 Feb 09 02:12:07 PM UTC 25 109036444 ps
T345 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2798258429 Feb 09 02:11:45 PM UTC 25 Feb 09 02:12:07 PM UTC 25 567817554 ps
T346 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.744338330 Feb 09 02:11:47 PM UTC 25 Feb 09 02:12:08 PM UTC 25 2553079588 ps
T347 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.4091132492 Feb 09 02:11:49 PM UTC 25 Feb 09 02:12:08 PM UTC 25 336820786 ps
T348 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3547161944 Feb 09 02:11:28 PM UTC 25 Feb 09 02:12:11 PM UTC 25 1135655112 ps
T349 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2861957417 Feb 09 02:12:02 PM UTC 25 Feb 09 02:12:12 PM UTC 25 327236243 ps
T72 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1803409962 Feb 09 02:12:06 PM UTC 25 Feb 09 02:12:18 PM UTC 25 1102311184 ps
T350 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3357981349 Feb 09 02:12:12 PM UTC 25 Feb 09 02:12:18 PM UTC 25 146436918 ps
T218 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3109527468 Feb 09 02:12:06 PM UTC 25 Feb 09 02:12:19 PM UTC 25 1260379433 ps
T351 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.4033720141 Feb 09 02:11:44 PM UTC 25 Feb 09 02:12:20 PM UTC 25 4254719694 ps
T352 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.4216774414 Feb 09 02:10:48 PM UTC 25 Feb 09 02:12:23 PM UTC 25 2327761755 ps
T353 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.3909068715 Feb 09 02:12:09 PM UTC 25 Feb 09 02:12:24 PM UTC 25 1750080608 ps
T354 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2309346408 Feb 09 02:12:22 PM UTC 25 Feb 09 02:12:24 PM UTC 25 47987003 ps
T355 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.1784063666 Feb 09 02:11:27 PM UTC 25 Feb 09 02:12:25 PM UTC 25 7342073890 ps
T356 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1128106147 Feb 09 02:12:25 PM UTC 25 Feb 09 02:12:27 PM UTC 25 47132574 ps
T357 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.1790935704 Feb 09 02:12:13 PM UTC 25 Feb 09 02:12:28 PM UTC 25 802611054 ps
T358 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.3812847498 Feb 09 02:11:23 PM UTC 25 Feb 09 02:12:29 PM UTC 25 5299109700 ps
T359 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1734728397 Feb 09 02:12:24 PM UTC 25 Feb 09 02:12:29 PM UTC 25 552451857 ps
T360 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.3694954198 Feb 09 02:12:17 PM UTC 25 Feb 09 02:12:30 PM UTC 25 1675589770 ps
T361 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.2204701787 Feb 09 02:11:38 PM UTC 25 Feb 09 02:12:30 PM UTC 25 498842634 ps
T362 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3386651093 Feb 09 02:12:18 PM UTC 25 Feb 09 02:12:32 PM UTC 25 481456841 ps
T363 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.453231890 Feb 09 02:12:08 PM UTC 25 Feb 09 02:12:32 PM UTC 25 525527551 ps
T364 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.54929510 Feb 09 02:12:28 PM UTC 25 Feb 09 02:12:32 PM UTC 25 184533189 ps
T365 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1317107090 Feb 09 02:13:50 PM UTC 25 Feb 09 02:13:54 PM UTC 25 132500986 ps
T366 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2104491200 Feb 09 02:12:09 PM UTC 25 Feb 09 02:12:33 PM UTC 25 1229493526 ps