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67 always_ff @(posedge clk_i or negedge rst_ni) begin
68 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
69 1/1 err_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
71 1/1 err_q <= 1'b1;
Tests: T61 T62 T63
72 end
MISSING_ELSE
73 end
74
75 // integrity error output is permanent and should be used for alert generation
76 // register errors are transactional
77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
78
79 // outgoing integrity generation
80 tlul_pkg::tl_d2h_t tl_o_pre;
81 tlul_rsp_intg_gen #(
82 .EnableRspIntgGen(1),
83 .EnableDataIntgGen(1)
84 ) u_rsp_intg_gen (
85 .tl_i(tl_o_pre),
86 .tl_o(tl_o)
87 );
88
89 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
90 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
91
92 tlul_adapter_reg #(
93 .RegAw(AW),
94 .RegDw(DW),
95 .EnableDataIntgGen(0)
96 ) u_reg_if (
97 .clk_i (clk_i),
98 .rst_ni (rst_ni),
99
100 .tl_i (tl_reg_h2d),
101 .tl_o (tl_reg_d2h),
102
103 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104 .intg_error_o(),
105
106 .we_o (reg_we),
107 .re_o (reg_re),
108 .addr_o (reg_addr),
109 .wdata_o (reg_wdata),
110 .be_o (reg_be),
111 .busy_i (reg_busy),
112 .rdata_i (reg_rdata),
113 .error_i (reg_error)
114 );
115
116 // cdc oversampling signals
117
118 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T5 T6 T7
119 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T1 T2 T3
120
121 // Define SW related signals
122 // Format: <reg>_<field>_{wd|we|qs}
123 // or <reg>_{wd|we|qs} if field == 1 or 0
124 logic alert_test_we;
125 logic alert_test_fatal_prog_error_wd;
126 logic alert_test_fatal_state_error_wd;
127 logic alert_test_fatal_bus_integ_error_wd;
128 logic status_re;
129 logic status_initialized_qs;
130 logic status_ready_qs;
131 logic status_ext_clock_switched_qs;
132 logic status_transition_successful_qs;
133 logic status_transition_count_error_qs;
134 logic status_transition_error_qs;
135 logic status_token_error_qs;
136 logic status_flash_rma_error_qs;
137 logic status_otp_error_qs;
138 logic status_state_error_qs;
139 logic status_bus_integ_error_qs;
140 logic status_otp_partition_error_qs;
141 logic claim_transition_if_regwen_we;
142 logic claim_transition_if_regwen_qs;
143 logic claim_transition_if_regwen_wd;
144 logic claim_transition_if_re;
145 logic claim_transition_if_we;
146 logic [7:0] claim_transition_if_qs;
147 logic [7:0] claim_transition_if_wd;
148 logic transition_regwen_re;
149 logic transition_regwen_qs;
150 logic transition_cmd_we;
151 logic transition_cmd_wd;
152 logic transition_ctrl_re;
153 logic transition_ctrl_we;
154 logic transition_ctrl_ext_clock_en_qs;
155 logic transition_ctrl_ext_clock_en_wd;
156 logic transition_ctrl_volatile_raw_unlock_qs;
157 logic transition_ctrl_volatile_raw_unlock_wd;
158 logic transition_token_0_re;
159 logic transition_token_0_we;
160 logic [31:0] transition_token_0_qs;
161 logic [31:0] transition_token_0_wd;
162 logic transition_token_1_re;
163 logic transition_token_1_we;
164 logic [31:0] transition_token_1_qs;
165 logic [31:0] transition_token_1_wd;
166 logic transition_token_2_re;
167 logic transition_token_2_we;
168 logic [31:0] transition_token_2_qs;
169 logic [31:0] transition_token_2_wd;
170 logic transition_token_3_re;
171 logic transition_token_3_we;
172 logic [31:0] transition_token_3_qs;
173 logic [31:0] transition_token_3_wd;
174 logic transition_target_re;
175 logic transition_target_we;
176 logic [29:0] transition_target_qs;
177 logic [29:0] transition_target_wd;
178 logic otp_vendor_test_ctrl_re;
179 logic otp_vendor_test_ctrl_we;
180 logic [31:0] otp_vendor_test_ctrl_qs;
181 logic [31:0] otp_vendor_test_ctrl_wd;
182 logic otp_vendor_test_status_re;
183 logic [31:0] otp_vendor_test_status_qs;
184 logic lc_state_re;
185 logic [29:0] lc_state_qs;
186 logic lc_transition_cnt_re;
187 logic [4:0] lc_transition_cnt_qs;
188 logic lc_id_state_re;
189 logic [31:0] lc_id_state_qs;
190 logic hw_revision0_re;
191 logic [15:0] hw_revision0_product_id_qs;
192 logic [15:0] hw_revision0_silicon_creator_id_qs;
193 logic hw_revision1_re;
194 logic [7:0] hw_revision1_revision_id_qs;
195 logic [23:0] hw_revision1_reserved_qs;
196 logic device_id_0_re;
197 logic [31:0] device_id_0_qs;
198 logic device_id_1_re;
199 logic [31:0] device_id_1_qs;
200 logic device_id_2_re;
201 logic [31:0] device_id_2_qs;
202 logic device_id_3_re;
203 logic [31:0] device_id_3_qs;
204 logic device_id_4_re;
205 logic [31:0] device_id_4_qs;
206 logic device_id_5_re;
207 logic [31:0] device_id_5_qs;
208 logic device_id_6_re;
209 logic [31:0] device_id_6_qs;
210 logic device_id_7_re;
211 logic [31:0] device_id_7_qs;
212 logic manuf_state_0_re;
213 logic [31:0] manuf_state_0_qs;
214 logic manuf_state_1_re;
215 logic [31:0] manuf_state_1_qs;
216 logic manuf_state_2_re;
217 logic [31:0] manuf_state_2_qs;
218 logic manuf_state_3_re;
219 logic [31:0] manuf_state_3_qs;
220 logic manuf_state_4_re;
221 logic [31:0] manuf_state_4_qs;
222 logic manuf_state_5_re;
223 logic [31:0] manuf_state_5_qs;
224 logic manuf_state_6_re;
225 logic [31:0] manuf_state_6_qs;
226 logic manuf_state_7_re;
227 logic [31:0] manuf_state_7_qs;
228
229 // Register instances
230 // R[alert_test]: V(True)
231 logic alert_test_qe;
232 logic [2:0] alert_test_flds_we;
233 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T1 T2 T3
234 // F[fatal_prog_error]: 0:0
235 prim_subreg_ext #(
236 .DW (1)
237 ) u_alert_test_fatal_prog_error (
238 .re (1'b0),
239 .we (alert_test_we),
240 .wd (alert_test_fatal_prog_error_wd),
241 .d ('0),
242 .qre (),
243 .qe (alert_test_flds_we[0]),
244 .q (reg2hw.alert_test.fatal_prog_error.q),
245 .ds (),
246 .qs ()
247 );
248 1/1 assign reg2hw.alert_test.fatal_prog_error.qe = alert_test_qe;
Tests: T1 T2 T3
249
250 // F[fatal_state_error]: 1:1
251 prim_subreg_ext #(
252 .DW (1)
253 ) u_alert_test_fatal_state_error (
254 .re (1'b0),
255 .we (alert_test_we),
256 .wd (alert_test_fatal_state_error_wd),
257 .d ('0),
258 .qre (),
259 .qe (alert_test_flds_we[1]),
260 .q (reg2hw.alert_test.fatal_state_error.q),
261 .ds (),
262 .qs ()
263 );
264 1/1 assign reg2hw.alert_test.fatal_state_error.qe = alert_test_qe;
Tests: T1 T2 T3
265
266 // F[fatal_bus_integ_error]: 2:2
267 prim_subreg_ext #(
268 .DW (1)
269 ) u_alert_test_fatal_bus_integ_error (
270 .re (1'b0),
271 .we (alert_test_we),
272 .wd (alert_test_fatal_bus_integ_error_wd),
273 .d ('0),
274 .qre (),
275 .qe (alert_test_flds_we[2]),
276 .q (reg2hw.alert_test.fatal_bus_integ_error.q),
277 .ds (),
278 .qs ()
279 );
280 1/1 assign reg2hw.alert_test.fatal_bus_integ_error.qe = alert_test_qe;
Tests: T1 T2 T3
281
282
283 // R[status]: V(True)
284 // F[initialized]: 0:0
285 prim_subreg_ext #(
286 .DW (1)
287 ) u_status_initialized (
288 .re (status_re),
289 .we (1'b0),
290 .wd ('0),
291 .d (hw2reg.status.initialized.d),
292 .qre (),
293 .qe (),
294 .q (),
295 .ds (),
296 .qs (status_initialized_qs)
297 );
298
299 // F[ready]: 1:1
300 prim_subreg_ext #(
301 .DW (1)
302 ) u_status_ready (
303 .re (status_re),
304 .we (1'b0),
305 .wd ('0),
306 .d (hw2reg.status.ready.d),
307 .qre (),
308 .qe (),
309 .q (),
310 .ds (),
311 .qs (status_ready_qs)
312 );
313
314 // F[ext_clock_switched]: 2:2
315 prim_subreg_ext #(
316 .DW (1)
317 ) u_status_ext_clock_switched (
318 .re (status_re),
319 .we (1'b0),
320 .wd ('0),
321 .d (hw2reg.status.ext_clock_switched.d),
322 .qre (),
323 .qe (),
324 .q (),
325 .ds (),
326 .qs (status_ext_clock_switched_qs)
327 );
328
329 // F[transition_successful]: 3:3
330 prim_subreg_ext #(
331 .DW (1)
332 ) u_status_transition_successful (
333 .re (status_re),
334 .we (1'b0),
335 .wd ('0),
336 .d (hw2reg.status.transition_successful.d),
337 .qre (),
338 .qe (),
339 .q (),
340 .ds (),
341 .qs (status_transition_successful_qs)
342 );
343
344 // F[transition_count_error]: 4:4
345 prim_subreg_ext #(
346 .DW (1)
347 ) u_status_transition_count_error (
348 .re (status_re),
349 .we (1'b0),
350 .wd ('0),
351 .d (hw2reg.status.transition_count_error.d),
352 .qre (),
353 .qe (),
354 .q (),
355 .ds (),
356 .qs (status_transition_count_error_qs)
357 );
358
359 // F[transition_error]: 5:5
360 prim_subreg_ext #(
361 .DW (1)
362 ) u_status_transition_error (
363 .re (status_re),
364 .we (1'b0),
365 .wd ('0),
366 .d (hw2reg.status.transition_error.d),
367 .qre (),
368 .qe (),
369 .q (),
370 .ds (),
371 .qs (status_transition_error_qs)
372 );
373
374 // F[token_error]: 6:6
375 prim_subreg_ext #(
376 .DW (1)
377 ) u_status_token_error (
378 .re (status_re),
379 .we (1'b0),
380 .wd ('0),
381 .d (hw2reg.status.token_error.d),
382 .qre (),
383 .qe (),
384 .q (),
385 .ds (),
386 .qs (status_token_error_qs)
387 );
388
389 // F[flash_rma_error]: 7:7
390 prim_subreg_ext #(
391 .DW (1)
392 ) u_status_flash_rma_error (
393 .re (status_re),
394 .we (1'b0),
395 .wd ('0),
396 .d (hw2reg.status.flash_rma_error.d),
397 .qre (),
398 .qe (),
399 .q (),
400 .ds (),
401 .qs (status_flash_rma_error_qs)
402 );
403
404 // F[otp_error]: 8:8
405 prim_subreg_ext #(
406 .DW (1)
407 ) u_status_otp_error (
408 .re (status_re),
409 .we (1'b0),
410 .wd ('0),
411 .d (hw2reg.status.otp_error.d),
412 .qre (),
413 .qe (),
414 .q (),
415 .ds (),
416 .qs (status_otp_error_qs)
417 );
418
419 // F[state_error]: 9:9
420 prim_subreg_ext #(
421 .DW (1)
422 ) u_status_state_error (
423 .re (status_re),
424 .we (1'b0),
425 .wd ('0),
426 .d (hw2reg.status.state_error.d),
427 .qre (),
428 .qe (),
429 .q (),
430 .ds (),
431 .qs (status_state_error_qs)
432 );
433
434 // F[bus_integ_error]: 10:10
435 prim_subreg_ext #(
436 .DW (1)
437 ) u_status_bus_integ_error (
438 .re (status_re),
439 .we (1'b0),
440 .wd ('0),
441 .d (hw2reg.status.bus_integ_error.d),
442 .qre (),
443 .qe (),
444 .q (),
445 .ds (),
446 .qs (status_bus_integ_error_qs)
447 );
448
449 // F[otp_partition_error]: 11:11
450 prim_subreg_ext #(
451 .DW (1)
452 ) u_status_otp_partition_error (
453 .re (status_re),
454 .we (1'b0),
455 .wd ('0),
456 .d (hw2reg.status.otp_partition_error.d),
457 .qre (),
458 .qe (),
459 .q (),
460 .ds (),
461 .qs (status_otp_partition_error_qs)
462 );
463
464
465 // R[claim_transition_if_regwen]: V(False)
466 prim_subreg #(
467 .DW (1),
468 .SwAccess(prim_subreg_pkg::SwAccessW0C),
469 .RESVAL (1'h1),
470 .Mubi (1'b0)
471 ) u_claim_transition_if_regwen (
472 .clk_i (clk_i),
473 .rst_ni (rst_ni),
474
475 // from register interface
476 .we (claim_transition_if_regwen_we),
477 .wd (claim_transition_if_regwen_wd),
478
479 // from internal hardware
480 .de (1'b0),
481 .d ('0),
482
483 // to internal hardware
484 .qe (),
485 .q (),
486 .ds (),
487
488 // to register interface (read)
489 .qs (claim_transition_if_regwen_qs)
490 );
491
492
493 // R[claim_transition_if]: V(True)
494 logic claim_transition_if_qe;
495 logic [0:0] claim_transition_if_flds_we;
496 1/1 assign claim_transition_if_qe = &claim_transition_if_flds_we;
Tests: T1 T2 T3
497 // Create REGWEN-gated WE signal
498 logic claim_transition_if_gated_we;
499 1/1 assign claim_transition_if_gated_we = claim_transition_if_we & claim_transition_if_regwen_qs;
Tests: T1 T2 T3
500 prim_subreg_ext #(
501 .DW (8)
502 ) u_claim_transition_if (
503 .re (claim_transition_if_re),
504 .we (claim_transition_if_gated_we),
505 .wd (claim_transition_if_wd),
506 .d (hw2reg.claim_transition_if.d),
507 .qre (),
508 .qe (claim_transition_if_flds_we[0]),
509 .q (reg2hw.claim_transition_if.q),
510 .ds (),
511 .qs (claim_transition_if_qs)
512 );
513 1/1 assign reg2hw.claim_transition_if.qe = claim_transition_if_qe;
Tests: T1 T2 T3
514
515
516 // R[transition_regwen]: V(True)
517 prim_subreg_ext #(
518 .DW (1)
519 ) u_transition_regwen (
520 .re (transition_regwen_re),
521 .we (1'b0),
522 .wd ('0),
523 .d (hw2reg.transition_regwen.d),
524 .qre (),
525 .qe (),
526 .q (),
527 .ds (),
528 .qs (transition_regwen_qs)
529 );
530
531
532 // R[transition_cmd]: V(True)
533 logic transition_cmd_qe;
534 logic [0:0] transition_cmd_flds_we;
535 1/1 assign transition_cmd_qe = &transition_cmd_flds_we;
Tests: T1 T2 T3
536 // Create REGWEN-gated WE signal
537 logic transition_cmd_gated_we;
538 1/1 assign transition_cmd_gated_we = transition_cmd_we & transition_regwen_qs;
Tests: T1 T2 T3
539 prim_subreg_ext #(
540 .DW (1)
541 ) u_transition_cmd (
542 .re (1'b0),
543 .we (transition_cmd_gated_we),
544 .wd (transition_cmd_wd),
545 .d ('0),
546 .qre (),
547 .qe (transition_cmd_flds_we[0]),
548 .q (reg2hw.transition_cmd.q),
549 .ds (),
550 .qs ()
551 );
552 1/1 assign reg2hw.transition_cmd.qe = transition_cmd_qe;
Tests: T1 T2 T3
553
554
555 // R[transition_ctrl]: V(True)
556 logic transition_ctrl_qe;
557 logic [1:0] transition_ctrl_flds_we;
558 1/1 assign transition_ctrl_qe = &transition_ctrl_flds_we;
Tests: T1 T2 T3
559 // Create REGWEN-gated WE signal
560 logic transition_ctrl_gated_we;
561 1/1 assign transition_ctrl_gated_we = transition_ctrl_we & transition_regwen_qs;
Tests: T1 T2 T3
562 // F[ext_clock_en]: 0:0
563 prim_subreg_ext #(
564 .DW (1)
565 ) u_transition_ctrl_ext_clock_en (
566 .re (transition_ctrl_re),
567 .we (transition_ctrl_gated_we),
568 .wd (transition_ctrl_ext_clock_en_wd),
569 .d (hw2reg.transition_ctrl.ext_clock_en.d),
570 .qre (),
571 .qe (transition_ctrl_flds_we[0]),
572 .q (reg2hw.transition_ctrl.ext_clock_en.q),
573 .ds (),
574 .qs (transition_ctrl_ext_clock_en_qs)
575 );
576 1/1 assign reg2hw.transition_ctrl.ext_clock_en.qe = transition_ctrl_qe;
Tests: T1 T2 T3
577
578 // F[volatile_raw_unlock]: 1:1
579 prim_subreg_ext #(
580 .DW (1)
581 ) u_transition_ctrl_volatile_raw_unlock (
582 .re (transition_ctrl_re),
583 .we (transition_ctrl_gated_we),
584 .wd (transition_ctrl_volatile_raw_unlock_wd),
585 .d (hw2reg.transition_ctrl.volatile_raw_unlock.d),
586 .qre (),
587 .qe (transition_ctrl_flds_we[1]),
588 .q (reg2hw.transition_ctrl.volatile_raw_unlock.q),
589 .ds (),
590 .qs (transition_ctrl_volatile_raw_unlock_qs)
591 );
592 1/1 assign reg2hw.transition_ctrl.volatile_raw_unlock.qe = transition_ctrl_qe;
Tests: T1 T2 T3
593
594
595 // Subregister 0 of Multireg transition_token
596 // R[transition_token_0]: V(True)
597 logic transition_token_0_qe;
598 logic [0:0] transition_token_0_flds_we;
599 1/1 assign transition_token_0_qe = &transition_token_0_flds_we;
Tests: T1 T2 T3
600 // Create REGWEN-gated WE signal
601 logic transition_token_0_gated_we;
602 1/1 assign transition_token_0_gated_we = transition_token_0_we & transition_regwen_qs;
Tests: T1 T2 T3
603 prim_subreg_ext #(
604 .DW (32)
605 ) u_transition_token_0 (
606 .re (transition_token_0_re),
607 .we (transition_token_0_gated_we),
608 .wd (transition_token_0_wd),
609 .d (hw2reg.transition_token[0].d),
610 .qre (),
611 .qe (transition_token_0_flds_we[0]),
612 .q (reg2hw.transition_token[0].q),
613 .ds (),
614 .qs (transition_token_0_qs)
615 );
616 1/1 assign reg2hw.transition_token[0].qe = transition_token_0_qe;
Tests: T1 T2 T3
617
618
619 // Subregister 1 of Multireg transition_token
620 // R[transition_token_1]: V(True)
621 logic transition_token_1_qe;
622 logic [0:0] transition_token_1_flds_we;
623 1/1 assign transition_token_1_qe = &transition_token_1_flds_we;
Tests: T1 T2 T3
624 // Create REGWEN-gated WE signal
625 logic transition_token_1_gated_we;
626 1/1 assign transition_token_1_gated_we = transition_token_1_we & transition_regwen_qs;
Tests: T1 T2 T3
627 prim_subreg_ext #(
628 .DW (32)
629 ) u_transition_token_1 (
630 .re (transition_token_1_re),
631 .we (transition_token_1_gated_we),
632 .wd (transition_token_1_wd),
633 .d (hw2reg.transition_token[1].d),
634 .qre (),
635 .qe (transition_token_1_flds_we[0]),
636 .q (reg2hw.transition_token[1].q),
637 .ds (),
638 .qs (transition_token_1_qs)
639 );
640 1/1 assign reg2hw.transition_token[1].qe = transition_token_1_qe;
Tests: T1 T2 T3
641
642
643 // Subregister 2 of Multireg transition_token
644 // R[transition_token_2]: V(True)
645 logic transition_token_2_qe;
646 logic [0:0] transition_token_2_flds_we;
647 1/1 assign transition_token_2_qe = &transition_token_2_flds_we;
Tests: T1 T2 T3
648 // Create REGWEN-gated WE signal
649 logic transition_token_2_gated_we;
650 1/1 assign transition_token_2_gated_we = transition_token_2_we & transition_regwen_qs;
Tests: T1 T2 T3
651 prim_subreg_ext #(
652 .DW (32)
653 ) u_transition_token_2 (
654 .re (transition_token_2_re),
655 .we (transition_token_2_gated_we),
656 .wd (transition_token_2_wd),
657 .d (hw2reg.transition_token[2].d),
658 .qre (),
659 .qe (transition_token_2_flds_we[0]),
660 .q (reg2hw.transition_token[2].q),
661 .ds (),
662 .qs (transition_token_2_qs)
663 );
664 1/1 assign reg2hw.transition_token[2].qe = transition_token_2_qe;
Tests: T1 T2 T3
665
666
667 // Subregister 3 of Multireg transition_token
668 // R[transition_token_3]: V(True)
669 logic transition_token_3_qe;
670 logic [0:0] transition_token_3_flds_we;
671 1/1 assign transition_token_3_qe = &transition_token_3_flds_we;
Tests: T1 T2 T3
672 // Create REGWEN-gated WE signal
673 logic transition_token_3_gated_we;
674 1/1 assign transition_token_3_gated_we = transition_token_3_we & transition_regwen_qs;
Tests: T1 T2 T3
675 prim_subreg_ext #(
676 .DW (32)
677 ) u_transition_token_3 (
678 .re (transition_token_3_re),
679 .we (transition_token_3_gated_we),
680 .wd (transition_token_3_wd),
681 .d (hw2reg.transition_token[3].d),
682 .qre (),
683 .qe (transition_token_3_flds_we[0]),
684 .q (reg2hw.transition_token[3].q),
685 .ds (),
686 .qs (transition_token_3_qs)
687 );
688 1/1 assign reg2hw.transition_token[3].qe = transition_token_3_qe;
Tests: T1 T2 T3
689
690
691 // R[transition_target]: V(True)
692 logic transition_target_qe;
693 logic [0:0] transition_target_flds_we;
694 1/1 assign transition_target_qe = &transition_target_flds_we;
Tests: T1 T2 T3
695 // Create REGWEN-gated WE signal
696 logic transition_target_gated_we;
697 1/1 assign transition_target_gated_we = transition_target_we & transition_regwen_qs;
Tests: T1 T2 T3
698 prim_subreg_ext #(
699 .DW (30)
700 ) u_transition_target (
701 .re (transition_target_re),
702 .we (transition_target_gated_we),
703 .wd (transition_target_wd),
704 .d (hw2reg.transition_target.d),
705 .qre (),
706 .qe (transition_target_flds_we[0]),
707 .q (reg2hw.transition_target.q),
708 .ds (),
709 .qs (transition_target_qs)
710 );
711 1/1 assign reg2hw.transition_target.qe = transition_target_qe;
Tests: T1 T2 T3
712
713
714 // R[otp_vendor_test_ctrl]: V(True)
715 logic otp_vendor_test_ctrl_qe;
716 logic [0:0] otp_vendor_test_ctrl_flds_we;
717 1/1 assign otp_vendor_test_ctrl_qe = &otp_vendor_test_ctrl_flds_we;
Tests: T1 T2 T3
718 // Create REGWEN-gated WE signal
719 logic otp_vendor_test_ctrl_gated_we;
720 1/1 assign otp_vendor_test_ctrl_gated_we = otp_vendor_test_ctrl_we & transition_regwen_qs;
Tests: T1 T2 T3
721 prim_subreg_ext #(
722 .DW (32)
723 ) u_otp_vendor_test_ctrl (
724 .re (otp_vendor_test_ctrl_re),
725 .we (otp_vendor_test_ctrl_gated_we),
726 .wd (otp_vendor_test_ctrl_wd),
727 .d (hw2reg.otp_vendor_test_ctrl.d),
728 .qre (),
729 .qe (otp_vendor_test_ctrl_flds_we[0]),
730 .q (reg2hw.otp_vendor_test_ctrl.q),
731 .ds (),
732 .qs (otp_vendor_test_ctrl_qs)
733 );
734 1/1 assign reg2hw.otp_vendor_test_ctrl.qe = otp_vendor_test_ctrl_qe;
Tests: T1 T2 T3
735
736
737 // R[otp_vendor_test_status]: V(True)
738 prim_subreg_ext #(
739 .DW (32)
740 ) u_otp_vendor_test_status (
741 .re (otp_vendor_test_status_re),
742 .we (1'b0),
743 .wd ('0),
744 .d (hw2reg.otp_vendor_test_status.d),
745 .qre (),
746 .qe (),
747 .q (),
748 .ds (),
749 .qs (otp_vendor_test_status_qs)
750 );
751
752
753 // R[lc_state]: V(True)
754 prim_subreg_ext #(
755 .DW (30)
756 ) u_lc_state (
757 .re (lc_state_re),
758 .we (1'b0),
759 .wd ('0),
760 .d (hw2reg.lc_state.d),
761 .qre (),
762 .qe (),
763 .q (),
764 .ds (),
765 .qs (lc_state_qs)
766 );
767
768
769 // R[lc_transition_cnt]: V(True)
770 prim_subreg_ext #(
771 .DW (5)
772 ) u_lc_transition_cnt (
773 .re (lc_transition_cnt_re),
774 .we (1'b0),
775 .wd ('0),
776 .d (hw2reg.lc_transition_cnt.d),
777 .qre (),
778 .qe (),
779 .q (),
780 .ds (),
781 .qs (lc_transition_cnt_qs)
782 );
783
784
785 // R[lc_id_state]: V(True)
786 prim_subreg_ext #(
787 .DW (32)
788 ) u_lc_id_state (
789 .re (lc_id_state_re),
790 .we (1'b0),
791 .wd ('0),
792 .d (hw2reg.lc_id_state.d),
793 .qre (),
794 .qe (),
795 .q (),
796 .ds (),
797 .qs (lc_id_state_qs)
798 );
799
800
801 // R[hw_revision0]: V(True)
802 // F[product_id]: 15:0
803 prim_subreg_ext #(
804 .DW (16)
805 ) u_hw_revision0_product_id (
806 .re (hw_revision0_re),
807 .we (1'b0),
808 .wd ('0),
809 .d (hw2reg.hw_revision0.product_id.d),
810 .qre (),
811 .qe (),
812 .q (),
813 .ds (),
814 .qs (hw_revision0_product_id_qs)
815 );
816
817 // F[silicon_creator_id]: 31:16
818 prim_subreg_ext #(
819 .DW (16)
820 ) u_hw_revision0_silicon_creator_id (
821 .re (hw_revision0_re),
822 .we (1'b0),
823 .wd ('0),
824 .d (hw2reg.hw_revision0.silicon_creator_id.d),
825 .qre (),
826 .qe (),
827 .q (),
828 .ds (),
829 .qs (hw_revision0_silicon_creator_id_qs)
830 );
831
832
833 // R[hw_revision1]: V(True)
834 // F[revision_id]: 7:0
835 prim_subreg_ext #(
836 .DW (8)
837 ) u_hw_revision1_revision_id (
838 .re (hw_revision1_re),
839 .we (1'b0),
840 .wd ('0),
841 .d (hw2reg.hw_revision1.revision_id.d),
842 .qre (),
843 .qe (),
844 .q (),
845 .ds (),
846 .qs (hw_revision1_revision_id_qs)
847 );
848
849 // F[reserved]: 31:8
850 prim_subreg_ext #(
851 .DW (24)
852 ) u_hw_revision1_reserved (
853 .re (hw_revision1_re),
854 .we (1'b0),
855 .wd ('0),
856 .d (hw2reg.hw_revision1.reserved.d),
857 .qre (),
858 .qe (),
859 .q (),
860 .ds (),
861 .qs (hw_revision1_reserved_qs)
862 );
863
864
865 // Subregister 0 of Multireg device_id
866 // R[device_id_0]: V(True)
867 prim_subreg_ext #(
868 .DW (32)
869 ) u_device_id_0 (
870 .re (device_id_0_re),
871 .we (1'b0),
872 .wd ('0),
873 .d (hw2reg.device_id[0].d),
874 .qre (),
875 .qe (),
876 .q (),
877 .ds (),
878 .qs (device_id_0_qs)
879 );
880
881
882 // Subregister 1 of Multireg device_id
883 // R[device_id_1]: V(True)
884 prim_subreg_ext #(
885 .DW (32)
886 ) u_device_id_1 (
887 .re (device_id_1_re),
888 .we (1'b0),
889 .wd ('0),
890 .d (hw2reg.device_id[1].d),
891 .qre (),
892 .qe (),
893 .q (),
894 .ds (),
895 .qs (device_id_1_qs)
896 );
897
898
899 // Subregister 2 of Multireg device_id
900 // R[device_id_2]: V(True)
901 prim_subreg_ext #(
902 .DW (32)
903 ) u_device_id_2 (
904 .re (device_id_2_re),
905 .we (1'b0),
906 .wd ('0),
907 .d (hw2reg.device_id[2].d),
908 .qre (),
909 .qe (),
910 .q (),
911 .ds (),
912 .qs (device_id_2_qs)
913 );
914
915
916 // Subregister 3 of Multireg device_id
917 // R[device_id_3]: V(True)
918 prim_subreg_ext #(
919 .DW (32)
920 ) u_device_id_3 (
921 .re (device_id_3_re),
922 .we (1'b0),
923 .wd ('0),
924 .d (hw2reg.device_id[3].d),
925 .qre (),
926 .qe (),
927 .q (),
928 .ds (),
929 .qs (device_id_3_qs)
930 );
931
932
933 // Subregister 4 of Multireg device_id
934 // R[device_id_4]: V(True)
935 prim_subreg_ext #(
936 .DW (32)
937 ) u_device_id_4 (
938 .re (device_id_4_re),
939 .we (1'b0),
940 .wd ('0),
941 .d (hw2reg.device_id[4].d),
942 .qre (),
943 .qe (),
944 .q (),
945 .ds (),
946 .qs (device_id_4_qs)
947 );
948
949
950 // Subregister 5 of Multireg device_id
951 // R[device_id_5]: V(True)
952 prim_subreg_ext #(
953 .DW (32)
954 ) u_device_id_5 (
955 .re (device_id_5_re),
956 .we (1'b0),
957 .wd ('0),
958 .d (hw2reg.device_id[5].d),
959 .qre (),
960 .qe (),
961 .q (),
962 .ds (),
963 .qs (device_id_5_qs)
964 );
965
966
967 // Subregister 6 of Multireg device_id
968 // R[device_id_6]: V(True)
969 prim_subreg_ext #(
970 .DW (32)
971 ) u_device_id_6 (
972 .re (device_id_6_re),
973 .we (1'b0),
974 .wd ('0),
975 .d (hw2reg.device_id[6].d),
976 .qre (),
977 .qe (),
978 .q (),
979 .ds (),
980 .qs (device_id_6_qs)
981 );
982
983
984 // Subregister 7 of Multireg device_id
985 // R[device_id_7]: V(True)
986 prim_subreg_ext #(
987 .DW (32)
988 ) u_device_id_7 (
989 .re (device_id_7_re),
990 .we (1'b0),
991 .wd ('0),
992 .d (hw2reg.device_id[7].d),
993 .qre (),
994 .qe (),
995 .q (),
996 .ds (),
997 .qs (device_id_7_qs)
998 );
999
1000
1001 // Subregister 0 of Multireg manuf_state
1002 // R[manuf_state_0]: V(True)
1003 prim_subreg_ext #(
1004 .DW (32)
1005 ) u_manuf_state_0 (
1006 .re (manuf_state_0_re),
1007 .we (1'b0),
1008 .wd ('0),
1009 .d (hw2reg.manuf_state[0].d),
1010 .qre (),
1011 .qe (),
1012 .q (),
1013 .ds (),
1014 .qs (manuf_state_0_qs)
1015 );
1016
1017
1018 // Subregister 1 of Multireg manuf_state
1019 // R[manuf_state_1]: V(True)
1020 prim_subreg_ext #(
1021 .DW (32)
1022 ) u_manuf_state_1 (
1023 .re (manuf_state_1_re),
1024 .we (1'b0),
1025 .wd ('0),
1026 .d (hw2reg.manuf_state[1].d),
1027 .qre (),
1028 .qe (),
1029 .q (),
1030 .ds (),
1031 .qs (manuf_state_1_qs)
1032 );
1033
1034
1035 // Subregister 2 of Multireg manuf_state
1036 // R[manuf_state_2]: V(True)
1037 prim_subreg_ext #(
1038 .DW (32)
1039 ) u_manuf_state_2 (
1040 .re (manuf_state_2_re),
1041 .we (1'b0),
1042 .wd ('0),
1043 .d (hw2reg.manuf_state[2].d),
1044 .qre (),
1045 .qe (),
1046 .q (),
1047 .ds (),
1048 .qs (manuf_state_2_qs)
1049 );
1050
1051
1052 // Subregister 3 of Multireg manuf_state
1053 // R[manuf_state_3]: V(True)
1054 prim_subreg_ext #(
1055 .DW (32)
1056 ) u_manuf_state_3 (
1057 .re (manuf_state_3_re),
1058 .we (1'b0),
1059 .wd ('0),
1060 .d (hw2reg.manuf_state[3].d),
1061 .qre (),
1062 .qe (),
1063 .q (),
1064 .ds (),
1065 .qs (manuf_state_3_qs)
1066 );
1067
1068
1069 // Subregister 4 of Multireg manuf_state
1070 // R[manuf_state_4]: V(True)
1071 prim_subreg_ext #(
1072 .DW (32)
1073 ) u_manuf_state_4 (
1074 .re (manuf_state_4_re),
1075 .we (1'b0),
1076 .wd ('0),
1077 .d (hw2reg.manuf_state[4].d),
1078 .qre (),
1079 .qe (),
1080 .q (),
1081 .ds (),
1082 .qs (manuf_state_4_qs)
1083 );
1084
1085
1086 // Subregister 5 of Multireg manuf_state
1087 // R[manuf_state_5]: V(True)
1088 prim_subreg_ext #(
1089 .DW (32)
1090 ) u_manuf_state_5 (
1091 .re (manuf_state_5_re),
1092 .we (1'b0),
1093 .wd ('0),
1094 .d (hw2reg.manuf_state[5].d),
1095 .qre (),
1096 .qe (),
1097 .q (),
1098 .ds (),
1099 .qs (manuf_state_5_qs)
1100 );
1101
1102
1103 // Subregister 6 of Multireg manuf_state
1104 // R[manuf_state_6]: V(True)
1105 prim_subreg_ext #(
1106 .DW (32)
1107 ) u_manuf_state_6 (
1108 .re (manuf_state_6_re),
1109 .we (1'b0),
1110 .wd ('0),
1111 .d (hw2reg.manuf_state[6].d),
1112 .qre (),
1113 .qe (),
1114 .q (),
1115 .ds (),
1116 .qs (manuf_state_6_qs)
1117 );
1118
1119
1120 // Subregister 7 of Multireg manuf_state
1121 // R[manuf_state_7]: V(True)
1122 prim_subreg_ext #(
1123 .DW (32)
1124 ) u_manuf_state_7 (
1125 .re (manuf_state_7_re),
1126 .we (1'b0),
1127 .wd ('0),
1128 .d (hw2reg.manuf_state[7].d),
1129 .qre (),
1130 .qe (),
1131 .q (),
1132 .ds (),
1133 .qs (manuf_state_7_qs)
1134 );
1135
1136
1137
1138 logic [34:0] addr_hit;
1139 always_comb begin
1140 1/1 addr_hit = '0;
Tests: T5 T6 T7
1141 1/1 addr_hit[ 0] = (reg_addr == LC_CTRL_ALERT_TEST_OFFSET);
Tests: T5 T6 T7
1142 1/1 addr_hit[ 1] = (reg_addr == LC_CTRL_STATUS_OFFSET);
Tests: T5 T6 T7
1143 1/1 addr_hit[ 2] = (reg_addr == LC_CTRL_CLAIM_TRANSITION_IF_REGWEN_OFFSET);
Tests: T5 T6 T7
1144 1/1 addr_hit[ 3] = (reg_addr == LC_CTRL_CLAIM_TRANSITION_IF_OFFSET);
Tests: T5 T6 T7
1145 1/1 addr_hit[ 4] = (reg_addr == LC_CTRL_TRANSITION_REGWEN_OFFSET);
Tests: T5 T6 T7
1146 1/1 addr_hit[ 5] = (reg_addr == LC_CTRL_TRANSITION_CMD_OFFSET);
Tests: T5 T6 T7
1147 1/1 addr_hit[ 6] = (reg_addr == LC_CTRL_TRANSITION_CTRL_OFFSET);
Tests: T5 T6 T7
1148 1/1 addr_hit[ 7] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_0_OFFSET);
Tests: T5 T6 T7
1149 1/1 addr_hit[ 8] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_1_OFFSET);
Tests: T5 T6 T7
1150 1/1 addr_hit[ 9] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_2_OFFSET);
Tests: T5 T6 T7
1151 1/1 addr_hit[10] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_3_OFFSET);
Tests: T5 T6 T7
1152 1/1 addr_hit[11] = (reg_addr == LC_CTRL_TRANSITION_TARGET_OFFSET);
Tests: T5 T6 T7
1153 1/1 addr_hit[12] = (reg_addr == LC_CTRL_OTP_VENDOR_TEST_CTRL_OFFSET);
Tests: T5 T6 T7
1154 1/1 addr_hit[13] = (reg_addr == LC_CTRL_OTP_VENDOR_TEST_STATUS_OFFSET);
Tests: T5 T6 T7
1155 1/1 addr_hit[14] = (reg_addr == LC_CTRL_LC_STATE_OFFSET);
Tests: T5 T6 T7
1156 1/1 addr_hit[15] = (reg_addr == LC_CTRL_LC_TRANSITION_CNT_OFFSET);
Tests: T5 T6 T7
1157 1/1 addr_hit[16] = (reg_addr == LC_CTRL_LC_ID_STATE_OFFSET);
Tests: T5 T6 T7
1158 1/1 addr_hit[17] = (reg_addr == LC_CTRL_HW_REVISION0_OFFSET);
Tests: T5 T6 T7
1159 1/1 addr_hit[18] = (reg_addr == LC_CTRL_HW_REVISION1_OFFSET);
Tests: T5 T6 T7
1160 1/1 addr_hit[19] = (reg_addr == LC_CTRL_DEVICE_ID_0_OFFSET);
Tests: T5 T6 T7
1161 1/1 addr_hit[20] = (reg_addr == LC_CTRL_DEVICE_ID_1_OFFSET);
Tests: T5 T6 T7
1162 1/1 addr_hit[21] = (reg_addr == LC_CTRL_DEVICE_ID_2_OFFSET);
Tests: T5 T6 T7
1163 1/1 addr_hit[22] = (reg_addr == LC_CTRL_DEVICE_ID_3_OFFSET);
Tests: T5 T6 T7
1164 1/1 addr_hit[23] = (reg_addr == LC_CTRL_DEVICE_ID_4_OFFSET);
Tests: T5 T6 T7
1165 1/1 addr_hit[24] = (reg_addr == LC_CTRL_DEVICE_ID_5_OFFSET);
Tests: T5 T6 T7
1166 1/1 addr_hit[25] = (reg_addr == LC_CTRL_DEVICE_ID_6_OFFSET);
Tests: T5 T6 T7
1167 1/1 addr_hit[26] = (reg_addr == LC_CTRL_DEVICE_ID_7_OFFSET);
Tests: T5 T6 T7
1168 1/1 addr_hit[27] = (reg_addr == LC_CTRL_MANUF_STATE_0_OFFSET);
Tests: T5 T6 T7
1169 1/1 addr_hit[28] = (reg_addr == LC_CTRL_MANUF_STATE_1_OFFSET);
Tests: T5 T6 T7
1170 1/1 addr_hit[29] = (reg_addr == LC_CTRL_MANUF_STATE_2_OFFSET);
Tests: T5 T6 T7
1171 1/1 addr_hit[30] = (reg_addr == LC_CTRL_MANUF_STATE_3_OFFSET);
Tests: T5 T6 T7
1172 1/1 addr_hit[31] = (reg_addr == LC_CTRL_MANUF_STATE_4_OFFSET);
Tests: T5 T6 T7
1173 1/1 addr_hit[32] = (reg_addr == LC_CTRL_MANUF_STATE_5_OFFSET);
Tests: T5 T6 T7
1174 1/1 addr_hit[33] = (reg_addr == LC_CTRL_MANUF_STATE_6_OFFSET);
Tests: T5 T6 T7
1175 1/1 addr_hit[34] = (reg_addr == LC_CTRL_MANUF_STATE_7_OFFSET);
Tests: T5 T6 T7
1176 end
1177
1178 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
1179
1180 // Check sub-word write is permitted
1181 always_comb begin
1182 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
1183 ((addr_hit[ 0] & (|(LC_CTRL_PERMIT[ 0] & ~reg_be))) |
1184 (addr_hit[ 1] & (|(LC_CTRL_PERMIT[ 1] & ~reg_be))) |
1185 (addr_hit[ 2] & (|(LC_CTRL_PERMIT[ 2] & ~reg_be))) |
1186 (addr_hit[ 3] & (|(LC_CTRL_PERMIT[ 3] & ~reg_be))) |
1187 (addr_hit[ 4] & (|(LC_CTRL_PERMIT[ 4] & ~reg_be))) |
1188 (addr_hit[ 5] & (|(LC_CTRL_PERMIT[ 5] & ~reg_be))) |
1189 (addr_hit[ 6] & (|(LC_CTRL_PERMIT[ 6] & ~reg_be))) |
1190 (addr_hit[ 7] & (|(LC_CTRL_PERMIT[ 7] & ~reg_be))) |
1191 (addr_hit[ 8] & (|(LC_CTRL_PERMIT[ 8] & ~reg_be))) |
1192 (addr_hit[ 9] & (|(LC_CTRL_PERMIT[ 9] & ~reg_be))) |
1193 (addr_hit[10] & (|(LC_CTRL_PERMIT[10] & ~reg_be))) |
1194 (addr_hit[11] & (|(LC_CTRL_PERMIT[11] & ~reg_be))) |
1195 (addr_hit[12] & (|(LC_CTRL_PERMIT[12] & ~reg_be))) |
1196 (addr_hit[13] & (|(LC_CTRL_PERMIT[13] & ~reg_be))) |
1197 (addr_hit[14] & (|(LC_CTRL_PERMIT[14] & ~reg_be))) |
1198 (addr_hit[15] & (|(LC_CTRL_PERMIT[15] & ~reg_be))) |
1199 (addr_hit[16] & (|(LC_CTRL_PERMIT[16] & ~reg_be))) |
1200 (addr_hit[17] & (|(LC_CTRL_PERMIT[17] & ~reg_be))) |
1201 (addr_hit[18] & (|(LC_CTRL_PERMIT[18] & ~reg_be))) |
1202 (addr_hit[19] & (|(LC_CTRL_PERMIT[19] & ~reg_be))) |
1203 (addr_hit[20] & (|(LC_CTRL_PERMIT[20] & ~reg_be))) |
1204 (addr_hit[21] & (|(LC_CTRL_PERMIT[21] & ~reg_be))) |
1205 (addr_hit[22] & (|(LC_CTRL_PERMIT[22] & ~reg_be))) |
1206 (addr_hit[23] & (|(LC_CTRL_PERMIT[23] & ~reg_be))) |
1207 (addr_hit[24] & (|(LC_CTRL_PERMIT[24] & ~reg_be))) |
1208 (addr_hit[25] & (|(LC_CTRL_PERMIT[25] & ~reg_be))) |
1209 (addr_hit[26] & (|(LC_CTRL_PERMIT[26] & ~reg_be))) |
1210 (addr_hit[27] & (|(LC_CTRL_PERMIT[27] & ~reg_be))) |
1211 (addr_hit[28] & (|(LC_CTRL_PERMIT[28] & ~reg_be))) |
1212 (addr_hit[29] & (|(LC_CTRL_PERMIT[29] & ~reg_be))) |
1213 (addr_hit[30] & (|(LC_CTRL_PERMIT[30] & ~reg_be))) |
1214 (addr_hit[31] & (|(LC_CTRL_PERMIT[31] & ~reg_be))) |
1215 (addr_hit[32] & (|(LC_CTRL_PERMIT[32] & ~reg_be))) |
1216 (addr_hit[33] & (|(LC_CTRL_PERMIT[33] & ~reg_be))) |
1217 (addr_hit[34] & (|(LC_CTRL_PERMIT[34] & ~reg_be)))));
1218 end
1219
1220 // Generate write-enables
1221 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
1222
1223 1/1 assign alert_test_fatal_prog_error_wd = reg_wdata[0];
Tests: T5 T6 T7
1224
1225 1/1 assign alert_test_fatal_state_error_wd = reg_wdata[1];
Tests: T5 T6 T7
1226
1227 1/1 assign alert_test_fatal_bus_integ_error_wd = reg_wdata[2];
Tests: T5 T6 T7
1228 1/1 assign status_re = addr_hit[1] & reg_re & !reg_error;
Tests: T1 T2 T3
1229 1/1 assign claim_transition_if_regwen_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
1230
1231 1/1 assign claim_transition_if_regwen_wd = reg_wdata[0];
Tests: T5 T6 T7
1232 1/1 assign claim_transition_if_re = addr_hit[3] & reg_re & !reg_error;
Tests: T1 T2 T3
1233 1/1 assign claim_transition_if_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
1234
1235 1/1 assign claim_transition_if_wd = reg_wdata[7:0];
Tests: T5 T6 T7
1236 1/1 assign transition_regwen_re = addr_hit[4] & reg_re & !reg_error;
Tests: T1 T2 T3
1237 1/1 assign transition_cmd_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
1238
1239 1/1 assign transition_cmd_wd = reg_wdata[0];
Tests: T5 T6 T7
1240 1/1 assign transition_ctrl_re = addr_hit[6] & reg_re & !reg_error;
Tests: T1 T2 T3
1241 1/1 assign transition_ctrl_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
1242
1243 1/1 assign transition_ctrl_ext_clock_en_wd = reg_wdata[0];
Tests: T5 T6 T7
1244
1245 1/1 assign transition_ctrl_volatile_raw_unlock_wd = reg_wdata[1];
Tests: T5 T6 T7
1246 1/1 assign transition_token_0_re = addr_hit[7] & reg_re & !reg_error;
Tests: T1 T2 T3
1247 1/1 assign transition_token_0_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
1248
1249 1/1 assign transition_token_0_wd = reg_wdata[31:0];
Tests: T5 T6 T7
1250 1/1 assign transition_token_1_re = addr_hit[8] & reg_re & !reg_error;
Tests: T1 T2 T3
1251 1/1 assign transition_token_1_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
1252
1253 1/1 assign transition_token_1_wd = reg_wdata[31:0];
Tests: T5 T6 T7
1254 1/1 assign transition_token_2_re = addr_hit[9] & reg_re & !reg_error;
Tests: T1 T2 T3
1255 1/1 assign transition_token_2_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
1256
1257 1/1 assign transition_token_2_wd = reg_wdata[31:0];
Tests: T5 T6 T7
1258 1/1 assign transition_token_3_re = addr_hit[10] & reg_re & !reg_error;
Tests: T1 T2 T3
1259 1/1 assign transition_token_3_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
1260
1261 1/1 assign transition_token_3_wd = reg_wdata[31:0];
Tests: T5 T6 T7
1262 1/1 assign transition_target_re = addr_hit[11] & reg_re & !reg_error;
Tests: T1 T2 T3
1263 1/1 assign transition_target_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
1264
1265 1/1 assign transition_target_wd = reg_wdata[29:0];
Tests: T5 T6 T7
1266 1/1 assign otp_vendor_test_ctrl_re = addr_hit[12] & reg_re & !reg_error;
Tests: T1 T2 T3
1267 1/1 assign otp_vendor_test_ctrl_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
1268
1269 1/1 assign otp_vendor_test_ctrl_wd = reg_wdata[31:0];
Tests: T5 T6 T7
1270 1/1 assign otp_vendor_test_status_re = addr_hit[13] & reg_re & !reg_error;
Tests: T1 T2 T3
1271 1/1 assign lc_state_re = addr_hit[14] & reg_re & !reg_error;
Tests: T1 T2 T3
1272 1/1 assign lc_transition_cnt_re = addr_hit[15] & reg_re & !reg_error;
Tests: T1 T2 T3
1273 1/1 assign lc_id_state_re = addr_hit[16] & reg_re & !reg_error;
Tests: T1 T2 T3
1274 1/1 assign hw_revision0_re = addr_hit[17] & reg_re & !reg_error;
Tests: T1 T2 T3
1275 1/1 assign hw_revision1_re = addr_hit[18] & reg_re & !reg_error;
Tests: T1 T2 T3
1276 1/1 assign device_id_0_re = addr_hit[19] & reg_re & !reg_error;
Tests: T1 T2 T3
1277 1/1 assign device_id_1_re = addr_hit[20] & reg_re & !reg_error;
Tests: T1 T2 T3
1278 1/1 assign device_id_2_re = addr_hit[21] & reg_re & !reg_error;
Tests: T1 T2 T3
1279 1/1 assign device_id_3_re = addr_hit[22] & reg_re & !reg_error;
Tests: T1 T2 T3
1280 1/1 assign device_id_4_re = addr_hit[23] & reg_re & !reg_error;
Tests: T1 T2 T3
1281 1/1 assign device_id_5_re = addr_hit[24] & reg_re & !reg_error;
Tests: T1 T2 T3
1282 1/1 assign device_id_6_re = addr_hit[25] & reg_re & !reg_error;
Tests: T1 T2 T3
1283 1/1 assign device_id_7_re = addr_hit[26] & reg_re & !reg_error;
Tests: T1 T2 T3
1284 1/1 assign manuf_state_0_re = addr_hit[27] & reg_re & !reg_error;
Tests: T1 T2 T3
1285 1/1 assign manuf_state_1_re = addr_hit[28] & reg_re & !reg_error;
Tests: T1 T2 T3
1286 1/1 assign manuf_state_2_re = addr_hit[29] & reg_re & !reg_error;
Tests: T1 T2 T3
1287 1/1 assign manuf_state_3_re = addr_hit[30] & reg_re & !reg_error;
Tests: T1 T2 T3
1288 1/1 assign manuf_state_4_re = addr_hit[31] & reg_re & !reg_error;
Tests: T1 T2 T3
1289 1/1 assign manuf_state_5_re = addr_hit[32] & reg_re & !reg_error;
Tests: T1 T2 T3
1290 1/1 assign manuf_state_6_re = addr_hit[33] & reg_re & !reg_error;
Tests: T1 T2 T3
1291 1/1 assign manuf_state_7_re = addr_hit[34] & reg_re & !reg_error;
Tests: T1 T2 T3
1292
1293 // Assign write-enables to checker logic vector.
1294 always_comb begin
1295 1/1 reg_we_check = '0;
Tests: T1 T2 T3
1296 1/1 reg_we_check[0] = alert_test_we;
Tests: T1 T2 T3
1297 1/1 reg_we_check[1] = 1'b0;
Tests: T1 T2 T3
1298 1/1 reg_we_check[2] = claim_transition_if_regwen_we;
Tests: T1 T2 T3
1299 1/1 reg_we_check[3] = claim_transition_if_gated_we;
Tests: T1 T2 T3
1300 1/1 reg_we_check[4] = 1'b0;
Tests: T1 T2 T3
1301 1/1 reg_we_check[5] = transition_cmd_gated_we;
Tests: T1 T2 T3
1302 1/1 reg_we_check[6] = transition_ctrl_gated_we;
Tests: T1 T2 T3
1303 1/1 reg_we_check[7] = transition_token_0_gated_we;
Tests: T1 T2 T3
1304 1/1 reg_we_check[8] = transition_token_1_gated_we;
Tests: T1 T2 T3
1305 1/1 reg_we_check[9] = transition_token_2_gated_we;
Tests: T1 T2 T3
1306 1/1 reg_we_check[10] = transition_token_3_gated_we;
Tests: T1 T2 T3
1307 1/1 reg_we_check[11] = transition_target_gated_we;
Tests: T1 T2 T3
1308 1/1 reg_we_check[12] = otp_vendor_test_ctrl_gated_we;
Tests: T1 T2 T3
1309 1/1 reg_we_check[13] = 1'b0;
Tests: T1 T2 T3
1310 1/1 reg_we_check[14] = 1'b0;
Tests: T1 T2 T3
1311 1/1 reg_we_check[15] = 1'b0;
Tests: T1 T2 T3
1312 1/1 reg_we_check[16] = 1'b0;
Tests: T1 T2 T3
1313 1/1 reg_we_check[17] = 1'b0;
Tests: T1 T2 T3
1314 1/1 reg_we_check[18] = 1'b0;
Tests: T1 T2 T3
1315 1/1 reg_we_check[19] = 1'b0;
Tests: T1 T2 T3
1316 1/1 reg_we_check[20] = 1'b0;
Tests: T1 T2 T3
1317 1/1 reg_we_check[21] = 1'b0;
Tests: T1 T2 T3
1318 1/1 reg_we_check[22] = 1'b0;
Tests: T1 T2 T3
1319 1/1 reg_we_check[23] = 1'b0;
Tests: T1 T2 T3
1320 1/1 reg_we_check[24] = 1'b0;
Tests: T1 T2 T3
1321 1/1 reg_we_check[25] = 1'b0;
Tests: T1 T2 T3
1322 1/1 reg_we_check[26] = 1'b0;
Tests: T1 T2 T3
1323 1/1 reg_we_check[27] = 1'b0;
Tests: T1 T2 T3
1324 1/1 reg_we_check[28] = 1'b0;
Tests: T1 T2 T3
1325 1/1 reg_we_check[29] = 1'b0;
Tests: T1 T2 T3
1326 1/1 reg_we_check[30] = 1'b0;
Tests: T1 T2 T3
1327 1/1 reg_we_check[31] = 1'b0;
Tests: T1 T2 T3
1328 1/1 reg_we_check[32] = 1'b0;
Tests: T1 T2 T3
1329 1/1 reg_we_check[33] = 1'b0;
Tests: T1 T2 T3
1330 1/1 reg_we_check[34] = 1'b0;
Tests: T1 T2 T3
1331 end
1332
1333 // Read data return
1334 always_comb begin
1335 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
1336 1/1 unique case (1'b1)
Tests: T1 T2 T3
1337 addr_hit[0]: begin
1338 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1339 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1340 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
1341 end
1342
1343 addr_hit[1]: begin
1344 1/1 reg_rdata_next[0] = status_initialized_qs;
Tests: T1 T2 T3
1345 1/1 reg_rdata_next[1] = status_ready_qs;
Tests: T1 T2 T3
1346 1/1 reg_rdata_next[2] = status_ext_clock_switched_qs;
Tests: T1 T2 T3
1347 1/1 reg_rdata_next[3] = status_transition_successful_qs;
Tests: T1 T2 T3
1348 1/1 reg_rdata_next[4] = status_transition_count_error_qs;
Tests: T1 T2 T3
1349 1/1 reg_rdata_next[5] = status_transition_error_qs;
Tests: T1 T2 T3
1350 1/1 reg_rdata_next[6] = status_token_error_qs;
Tests: T1 T2 T3
1351 1/1 reg_rdata_next[7] = status_flash_rma_error_qs;
Tests: T1 T2 T3
1352 1/1 reg_rdata_next[8] = status_otp_error_qs;
Tests: T1 T2 T3
1353 1/1 reg_rdata_next[9] = status_state_error_qs;
Tests: T1 T2 T3
1354 1/1 reg_rdata_next[10] = status_bus_integ_error_qs;
Tests: T1 T2 T3
1355 1/1 reg_rdata_next[11] = status_otp_partition_error_qs;
Tests: T1 T2 T3
1356 end
1357
1358 addr_hit[2]: begin
1359 1/1 reg_rdata_next[0] = claim_transition_if_regwen_qs;
Tests: T1 T2 T3
1360 end
1361
1362 addr_hit[3]: begin
1363 1/1 reg_rdata_next[7:0] = claim_transition_if_qs;
Tests: T1 T2 T3
1364 end
1365
1366 addr_hit[4]: begin
1367 1/1 reg_rdata_next[0] = transition_regwen_qs;
Tests: T1 T2 T3
1368 end
1369
1370 addr_hit[5]: begin
1371 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1372 end
1373
1374 addr_hit[6]: begin
1375 1/1 reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs;
Tests: T1 T2 T3
1376 1/1 reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs;
Tests: T1 T2 T3
1377 end
1378
1379 addr_hit[7]: begin
1380 1/1 reg_rdata_next[31:0] = transition_token_0_qs;
Tests: T1 T2 T3
1381 end
1382
1383 addr_hit[8]: begin
1384 1/1 reg_rdata_next[31:0] = transition_token_1_qs;
Tests: T1 T2 T3
1385 end
1386
1387 addr_hit[9]: begin
1388 1/1 reg_rdata_next[31:0] = transition_token_2_qs;
Tests: T1 T2 T3
1389 end
1390
1391 addr_hit[10]: begin
1392 1/1 reg_rdata_next[31:0] = transition_token_3_qs;
Tests: T1 T2 T3
1393 end
1394
1395 addr_hit[11]: begin
1396 1/1 reg_rdata_next[29:0] = transition_target_qs;
Tests: T1 T2 T3
1397 end
1398
1399 addr_hit[12]: begin
1400 1/1 reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs;
Tests: T1 T2 T3
1401 end
1402
1403 addr_hit[13]: begin
1404 1/1 reg_rdata_next[31:0] = otp_vendor_test_status_qs;
Tests: T1 T2 T3
1405 end
1406
1407 addr_hit[14]: begin
1408 1/1 reg_rdata_next[29:0] = lc_state_qs;
Tests: T1 T2 T3
1409 end
1410
1411 addr_hit[15]: begin
1412 1/1 reg_rdata_next[4:0] = lc_transition_cnt_qs;
Tests: T1 T2 T3
1413 end
1414
1415 addr_hit[16]: begin
1416 1/1 reg_rdata_next[31:0] = lc_id_state_qs;
Tests: T1 T2 T3
1417 end
1418
1419 addr_hit[17]: begin
1420 1/1 reg_rdata_next[15:0] = hw_revision0_product_id_qs;
Tests: T1 T2 T3
1421 1/1 reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs;
Tests: T1 T2 T3
1422 end
1423
1424 addr_hit[18]: begin
1425 1/1 reg_rdata_next[7:0] = hw_revision1_revision_id_qs;
Tests: T1 T2 T3
1426 1/1 reg_rdata_next[31:8] = hw_revision1_reserved_qs;
Tests: T1 T2 T3
1427 end
1428
1429 addr_hit[19]: begin
1430 1/1 reg_rdata_next[31:0] = device_id_0_qs;
Tests: T1 T2 T3
1431 end
1432
1433 addr_hit[20]: begin
1434 1/1 reg_rdata_next[31:0] = device_id_1_qs;
Tests: T1 T2 T3
1435 end
1436
1437 addr_hit[21]: begin
1438 1/1 reg_rdata_next[31:0] = device_id_2_qs;
Tests: T1 T2 T3
1439 end
1440
1441 addr_hit[22]: begin
1442 1/1 reg_rdata_next[31:0] = device_id_3_qs;
Tests: T1 T2 T3
1443 end
1444
1445 addr_hit[23]: begin
1446 1/1 reg_rdata_next[31:0] = device_id_4_qs;
Tests: T1 T2 T3
1447 end
1448
1449 addr_hit[24]: begin
1450 1/1 reg_rdata_next[31:0] = device_id_5_qs;
Tests: T1 T2 T3
1451 end
1452
1453 addr_hit[25]: begin
1454 1/1 reg_rdata_next[31:0] = device_id_6_qs;
Tests: T1 T2 T3
1455 end
1456
1457 addr_hit[26]: begin
1458 1/1 reg_rdata_next[31:0] = device_id_7_qs;
Tests: T1 T2 T3
1459 end
1460
1461 addr_hit[27]: begin
1462 1/1 reg_rdata_next[31:0] = manuf_state_0_qs;
Tests: T1 T2 T3
1463 end
1464
1465 addr_hit[28]: begin
1466 1/1 reg_rdata_next[31:0] = manuf_state_1_qs;
Tests: T1 T2 T3
1467 end
1468
1469 addr_hit[29]: begin
1470 1/1 reg_rdata_next[31:0] = manuf_state_2_qs;
Tests: T1 T2 T3
1471 end
1472
1473 addr_hit[30]: begin
1474 1/1 reg_rdata_next[31:0] = manuf_state_3_qs;
Tests: T1 T2 T3
1475 end
1476
1477 addr_hit[31]: begin
1478 1/1 reg_rdata_next[31:0] = manuf_state_4_qs;
Tests: T1 T2 T3
1479 end
1480
1481 addr_hit[32]: begin
1482 1/1 reg_rdata_next[31:0] = manuf_state_5_qs;
Tests: T1 T2 T3
1483 end
1484
1485 addr_hit[33]: begin
1486 1/1 reg_rdata_next[31:0] = manuf_state_6_qs;
Tests: T1 T2 T3
1487 end
1488
1489 addr_hit[34]: begin
1490 1/1 reg_rdata_next[31:0] = manuf_state_7_qs;
Tests: T1 T2 T3
1491 end
1492
1493 default: begin
1494 reg_rdata_next = '1;
1495 end
1496 endcase
1497 end
1498
1499 // shadow busy
1500 logic shadow_busy;
1501 assign shadow_busy = 1'b0;
1502
1503 // register busy
1504 unreachable assign reg_busy = shadow_busy;
1505
1506 // Unused signal tieoff
1507
1508 // wdata / byte enable are not always fully used
1509 // add a blanket unused statement to handle lint waivers
1510 logic unused_wdata;
1511 logic unused_be;
1512 1/1 assign unused_wdata = ^reg_wdata;
Tests: T5 T6 T7
1513 1/1 assign unused_be = ^reg_be;
Tests: T5 T6 T7