Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93769305

1

T1

22509

T2

19201

T3

19967

auto[1]

1364821

1

T2

9463

T3

1881

T11

3168

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93757348

1

T1

22509

T2

18652

T3

20561

auto[1]

1376778

1

T2

10012

T3

1287

T11

3267

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6794594	1			T1	6313		T2	6890		T3	6888
auto[IdleSt]	19087334	1			T1	2229		T2	6776		T3	1697
auto[ClkMuxSt]	33709	1			T1	66		T2	59		T3	52
auto[CntIncrSt]	33364	1			T1	66		T2	59		T3	52
auto[CntProgSt]	1427426	1			T1	2970		T2	112		T3	92
auto[TransCheckSt]	26180	1			T1	66		T2	48		T3	40
auto[TokenHashSt]	39770461	1			T1	730		T2	355		T3	444
auto[FlashRmaSt]	27728	1			T2	73		T3	67		T12	62
auto[TokenCheck0St]	12149	1			T2	25		T3	30		T12	32
auto[TokenCheck1St]	8948	1			T2	25		T3	17		T12	16
auto[TransProgSt]	338855	1			T2	38		T3	34		T12	368
auto[PostTransSt]	11213355	1			T1	10069		T2	21		T3	6788
auto[ScrapSt]	179210	1			T2	6		T19	44		T49	6
auto[EscalateSt]	6127853	1			T2	14177		T3	4065		T11	8892
auto[InvalidSt]	10050953	1			T3	1582		T11	9234		T12	2541

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2007	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10050953	1			T3	1582		T11	9234		T12	2541
EscalateSt	6127853	1			T2	14177		T3	4065		T11	8892
ScrapSt	179210	1			T2	6		T19	44		T49	6
PostTransSt	11213355	1			T1	10069		T2	21		T3	6788
TransProgSt	338855	1			T2	38		T3	34		T12	368
TokenCheck1St	8948	1			T2	25		T3	17		T12	16
TokenCheck0St	12149	1			T2	25		T3	30		T12	32
FlashRmaSt	27728	1			T2	73		T3	67		T12	62
TokenHashSt	39770461	1			T1	730		T2	355		T3	444
TransCheckSt	26180	1			T1	66		T2	48		T3	40
CntProgSt	1427426	1			T1	2970		T2	112		T3	92
CntIncrSt	33364	1			T1	66		T2	59		T3	52
ClkMuxSt	33709	1			T1	66		T2	59		T3	52
IdleSt	19087334	1			T1	2229		T2	6776		T3	1697
ResetSt	6794594	1			T1	6313		T2	6890		T3	6888
arcs[ResetSt=>IdleSt]	52527	1			T1	67		T2	69		T3	73
arcs[IdleSt=>ScrapSt]	275	1			T2	2		T19	1		T49	2
arcs[IdleSt=>ClkMuxSt]	33405	1			T1	66		T2	59		T3	52
arcs[ClkMuxSt=>CntIncrSt]	33364	1			T1	66		T2	59		T3	52
arcs[CntIncrSt=>PostTransSt]	1714	1			T23	15		T24	4		T44	14
arcs[CntIncrSt=>CntProgSt]	31588	1			T1	66		T2	59		T3	52
arcs[CntProgSt=>PostTransSt]	4410	1			T3	12		T12	13		T16	19
arcs[CntProgSt=>TransCheckSt]	26180	1			T1	66		T2	48		T3	40
arcs[TransCheckSt=>PostTransSt]	3649	1			T51	48		T58	30		T23	25
arcs[TransCheckSt=>TokenHashSt]	22392	1			T1	66		T2	41		T3	40
arcs[TokenHashSt=>PostTransSt]	9500	1			T1	66		T3	10		T12	5
arcs[TokenHashSt=>FlashRmaSt]	12238	1			T2	28		T3	30		T12	32
arcs[FlashRmaSt=>TokenCheck0St]	12149	1			T2	25		T3	30		T12	32
arcs[TokenCheck0St=>PostTransSt]	3169	1			T3	13		T12	16		T27	9
arcs[TokenCheck0St=>TokenCheck1St]	8948	1			T2	25		T3	17		T12	16
arcs[TokenCheck1St=>PostTransSt]	653	1			T45	1		T51	6		T58	5
arcs[TransProgSt=>PostTransSt]	7489	1			T2	12		T3	17		T12	16
arcs[IdleSt=>EscalateSt]	178	1			T2	7		T59	2		T49	3
arcs[ClkMuxSt=>EscalateSt]	41	1			T59	1		T49	1		T60	3
arcs[CntIncrSt=>EscalateSt]	62	1			T59	1		T49	2		T60	3
arcs[CntProgSt=>EscalateSt]	998	1			T2	11		T59	20		T49	19
arcs[TransCheckSt=>EscalateSt]	139	1			T2	7		T49	3		T65	6
arcs[TokenHashSt=>EscalateSt]	654	1			T2	13		T59	6		T49	10
arcs[FlashRmaSt=>EscalateSt]	89	1			T2	3		T59	1		T49	1
arcs[TokenCheck0St=>EscalateSt]	32	1			T49	1		T63	2		T64	1
arcs[TokenCheck1St=>EscalateSt]	145	1			T2	3		T59	4		T49	5
arcs[TransProgSt=>EscalateSt]	661	1			T2	10		T59	12		T49	17
arcs[PostTransSt=>EscalateSt]	4657	1			T2	12		T3	12		T12	13
arcs[InvalidSt=>EscalateSt]	14484	1			T3	20		T11	65		T12	13

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6794426	1			T1	6313		T2	6887		T3	6888
auto[0]	auto[IdleSt]	19087219	1			T1	2229		T2	6772		T3	1697
auto[0]	auto[ClkMuxSt]	33681	1			T1	66		T2	59		T3	52
auto[0]	auto[CntIncrSt]	33324	1			T1	66		T2	59		T3	52
auto[0]	auto[CntProgSt]	1426766	1			T1	2970		T2	106		T3	92
auto[0]	auto[TransCheckSt]	26093	1			T1	66		T2	45		T3	40
auto[0]	auto[TokenHashSt]	39770026	1			T1	730		T2	344		T3	444
auto[0]	auto[FlashRmaSt]	27671	1			T2	70		T3	67		T12	62
auto[0]	auto[TokenCheck0St]	12126	1			T2	25		T3	30		T12	32
auto[0]	auto[TokenCheck1St]	8843	1			T2	22		T3	17		T12	16
auto[0]	auto[TransProgSt]	338422	1			T2	32		T3	34		T12	368
auto[0]	auto[PostTransSt]	11210964	1			T1	10069		T2	13		T3	6782
auto[0]	auto[ScrapSt]	179179	1			T2	5		T19	44		T49	4
auto[0]	auto[EscalateSt]	4774789	1			T2	4762		T3	2203		T11	5756
auto[0]	auto[InvalidSt]	10043769	1			T3	1569		T11	9202		T12	2539
auto[1]	auto[ResetSt]	168	1			T2	3		T59	7		T49	2
auto[1]	auto[IdleSt]	115	1			T2	4		T59	1		T49	1
auto[1]	auto[ClkMuxSt]	28	1			T59	1		T49	1		T60	3
auto[1]	auto[CntIncrSt]	40	1			T59	1		T49	1		T60	1
auto[1]	auto[CntProgSt]	660	1			T2	6		T59	14		T49	14
auto[1]	auto[TransCheckSt]	87	1			T2	3		T49	1		T65	5
auto[1]	auto[TokenHashSt]	435	1			T2	11		T59	5		T49	8
auto[1]	auto[FlashRmaSt]	57	1			T2	3		T49	1		T60	1
auto[1]	auto[TokenCheck0St]	23	1			T49	1		T213	1		T163	2
auto[1]	auto[TokenCheck1St]	105	1			T2	3		T59	3		T49	4
auto[1]	auto[TransProgSt]	433	1			T2	6		T59	6		T49	11
auto[1]	auto[PostTransSt]	2391	1			T2	8		T3	6		T12	6
auto[1]	auto[ScrapSt]	31	1			T2	1		T49	2		T60	1
auto[1]	auto[EscalateSt]	1353064	1			T2	9415		T3	1862		T11	3136
auto[1]	auto[InvalidSt]	7184	1			T3	13		T11	32		T12	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6794424	1			T1	6313		T2	6887		T3	6888
auto[0]	auto[IdleSt]	19087212	1			T1	2229		T2	6771		T3	1697
auto[0]	auto[ClkMuxSt]	33677	1			T1	66		T2	59		T3	52
auto[0]	auto[CntIncrSt]	33323	1			T1	66		T2	59		T3	52
auto[0]	auto[CntProgSt]	1426767	1			T1	2970		T2	105		T3	92
auto[0]	auto[TransCheckSt]	26086	1			T1	66		T2	42		T3	40
auto[0]	auto[TokenHashSt]	39770036	1			T1	730		T2	347		T3	444
auto[0]	auto[FlashRmaSt]	27666	1			T2	71		T3	67		T12	62
auto[0]	auto[TokenCheck0St]	12128	1			T2	25		T3	30		T12	32
auto[0]	auto[TokenCheck1St]	8855	1			T2	24		T3	17		T12	16
auto[0]	auto[TransProgSt]	338398	1			T2	29		T3	34		T12	368
auto[0]	auto[PostTransSt]	11211002	1			T1	10069		T2	13		T3	6782
auto[0]	auto[ScrapSt]	179160	1			T2	5		T19	44		T49	5
auto[0]	auto[EscalateSt]	4762954	1			T2	4215		T3	2791		T11	5658
auto[0]	auto[InvalidSt]	10043653	1			T3	1575		T11	9201		T12	2530
auto[1]	auto[ResetSt]	170	1			T2	3		T59	10		T49	2
auto[1]	auto[IdleSt]	122	1			T2	5		T59	1		T49	3
auto[1]	auto[ClkMuxSt]	32	1			T59	1		T49	1		T60	1
auto[1]	auto[CntIncrSt]	41	1			T49	1		T60	3		T214	1
auto[1]	auto[CntProgSt]	659	1			T2	7		T59	12		T49	14
auto[1]	auto[TransCheckSt]	94	1			T2	6		T49	2		T65	4
auto[1]	auto[TokenHashSt]	425	1			T2	8		T59	3		T49	8
auto[1]	auto[FlashRmaSt]	62	1			T2	2		T59	1		T49	1
auto[1]	auto[TokenCheck0St]	21	1			T49	1		T63	2		T64	1
auto[1]	auto[TokenCheck1St]	93	1			T2	1		T59	3		T49	3
auto[1]	auto[TransProgSt]	457	1			T2	9		T59	7		T49	13
auto[1]	auto[PostTransSt]	2353	1			T2	8		T3	6		T12	7
auto[1]	auto[ScrapSt]	50	1			T2	1		T49	1		T60	3
auto[1]	auto[EscalateSt]	1364899	1			T2	9962		T3	1274		T11	3234
auto[1]	auto[InvalidSt]	7300	1			T3	7		T11	33		T12	11