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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.89 95.68 93.31 100.00 98.55 99.00 96.29


Total test records in report: 997
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T804 /workspace/coverage/default/9.lc_ctrl_security_escalation.712412805 Apr 21 01:31:14 PM PDT 24 Apr 21 01:31:22 PM PDT 24 342360809 ps
T805 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1971106793 Apr 21 01:34:45 PM PDT 24 Apr 21 01:34:56 PM PDT 24 487056740 ps
T806 /workspace/coverage/default/28.lc_ctrl_state_post_trans.3850143982 Apr 21 01:33:01 PM PDT 24 Apr 21 01:33:07 PM PDT 24 61744739 ps
T807 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.873900049 Apr 21 01:32:02 PM PDT 24 Apr 21 01:32:15 PM PDT 24 2643133600 ps
T808 /workspace/coverage/default/21.lc_ctrl_sec_mubi.2543826865 Apr 21 01:32:31 PM PDT 24 Apr 21 01:32:41 PM PDT 24 630161585 ps
T809 /workspace/coverage/default/49.lc_ctrl_errors.2333669298 Apr 21 01:34:41 PM PDT 24 Apr 21 01:34:57 PM PDT 24 697403729 ps
T810 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3246384227 Apr 21 01:31:31 PM PDT 24 Apr 21 01:32:09 PM PDT 24 1780521539 ps
T811 /workspace/coverage/default/42.lc_ctrl_prog_failure.1864182407 Apr 21 01:34:10 PM PDT 24 Apr 21 01:34:14 PM PDT 24 134588536 ps
T812 /workspace/coverage/default/18.lc_ctrl_state_post_trans.1633075153 Apr 21 01:32:12 PM PDT 24 Apr 21 01:32:20 PM PDT 24 496558015 ps
T813 /workspace/coverage/default/6.lc_ctrl_errors.3850591573 Apr 21 01:30:49 PM PDT 24 Apr 21 01:31:00 PM PDT 24 947277355 ps
T814 /workspace/coverage/default/15.lc_ctrl_smoke.882955022 Apr 21 01:31:50 PM PDT 24 Apr 21 01:31:51 PM PDT 24 45044932 ps
T815 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.248728125 Apr 21 01:29:55 PM PDT 24 Apr 21 01:30:02 PM PDT 24 735566438 ps
T816 /workspace/coverage/default/32.lc_ctrl_jtag_access.2876931155 Apr 21 01:33:25 PM PDT 24 Apr 21 01:33:32 PM PDT 24 2333889539 ps
T817 /workspace/coverage/default/46.lc_ctrl_state_failure.2667863598 Apr 21 01:34:25 PM PDT 24 Apr 21 01:34:57 PM PDT 24 319845157 ps
T818 /workspace/coverage/default/0.lc_ctrl_jtag_priority.643778090 Apr 21 01:29:56 PM PDT 24 Apr 21 01:29:59 PM PDT 24 856551247 ps
T819 /workspace/coverage/default/1.lc_ctrl_smoke.2879697194 Apr 21 01:29:57 PM PDT 24 Apr 21 01:29:59 PM PDT 24 171973882 ps
T820 /workspace/coverage/default/41.lc_ctrl_prog_failure.3465008275 Apr 21 01:34:03 PM PDT 24 Apr 21 01:34:05 PM PDT 24 27860577 ps
T821 /workspace/coverage/default/25.lc_ctrl_alert_test.2831615642 Apr 21 01:32:52 PM PDT 24 Apr 21 01:32:53 PM PDT 24 63390347 ps
T822 /workspace/coverage/default/15.lc_ctrl_jtag_access.4145149395 Apr 21 01:31:53 PM PDT 24 Apr 21 01:32:04 PM PDT 24 1750224651 ps
T823 /workspace/coverage/default/48.lc_ctrl_alert_test.4126302213 Apr 21 01:34:39 PM PDT 24 Apr 21 01:34:40 PM PDT 24 24975794 ps
T824 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.384542236 Apr 21 01:33:04 PM PDT 24 Apr 21 01:33:06 PM PDT 24 16804160 ps
T113 /workspace/coverage/default/0.lc_ctrl_sec_cm.2600332865 Apr 21 01:29:58 PM PDT 24 Apr 21 01:30:37 PM PDT 24 1059704495 ps
T825 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1412810806 Apr 21 01:32:06 PM PDT 24 Apr 21 01:32:14 PM PDT 24 762313719 ps
T826 /workspace/coverage/default/27.lc_ctrl_smoke.3679408 Apr 21 01:32:59 PM PDT 24 Apr 21 01:33:03 PM PDT 24 58149602 ps
T827 /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2923199218 Apr 21 01:34:26 PM PDT 24 Apr 21 02:10:49 PM PDT 24 31621957880 ps
T828 /workspace/coverage/default/28.lc_ctrl_smoke.3126939455 Apr 21 01:33:02 PM PDT 24 Apr 21 01:33:05 PM PDT 24 257858655 ps
T829 /workspace/coverage/default/45.lc_ctrl_state_post_trans.2841488527 Apr 21 01:34:24 PM PDT 24 Apr 21 01:34:27 PM PDT 24 130849921 ps
T830 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2803081688 Apr 21 01:34:00 PM PDT 24 Apr 21 01:34:07 PM PDT 24 211946293 ps
T831 /workspace/coverage/default/21.lc_ctrl_stress_all.3145186693 Apr 21 01:32:32 PM PDT 24 Apr 21 01:33:08 PM PDT 24 2063207161 ps
T832 /workspace/coverage/default/4.lc_ctrl_smoke.1182270421 Apr 21 01:30:22 PM PDT 24 Apr 21 01:30:24 PM PDT 24 82080667 ps
T833 /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.698444205 Apr 21 01:30:36 PM PDT 24 Apr 21 01:36:41 PM PDT 24 16727448813 ps
T834 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2706835251 Apr 21 01:30:32 PM PDT 24 Apr 21 01:31:07 PM PDT 24 3256907013 ps
T835 /workspace/coverage/default/48.lc_ctrl_state_post_trans.128015771 Apr 21 01:34:37 PM PDT 24 Apr 21 01:34:43 PM PDT 24 414784836 ps
T836 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3723348952 Apr 21 01:31:52 PM PDT 24 Apr 21 01:31:56 PM PDT 24 802035750 ps
T837 /workspace/coverage/default/5.lc_ctrl_sec_mubi.1552256880 Apr 21 01:30:43 PM PDT 24 Apr 21 01:31:02 PM PDT 24 456627287 ps
T838 /workspace/coverage/default/47.lc_ctrl_errors.1592173823 Apr 21 01:34:30 PM PDT 24 Apr 21 01:34:47 PM PDT 24 636633341 ps
T839 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.730298505 Apr 21 01:30:38 PM PDT 24 Apr 21 01:30:50 PM PDT 24 500600648 ps
T840 /workspace/coverage/default/27.lc_ctrl_security_escalation.894916748 Apr 21 01:32:59 PM PDT 24 Apr 21 01:33:07 PM PDT 24 1285539310 ps
T841 /workspace/coverage/default/23.lc_ctrl_errors.4256901287 Apr 21 01:32:37 PM PDT 24 Apr 21 01:32:46 PM PDT 24 308932286 ps
T842 /workspace/coverage/default/46.lc_ctrl_sec_mubi.2188478763 Apr 21 01:34:28 PM PDT 24 Apr 21 01:34:42 PM PDT 24 266450030 ps
T161 /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3630250147 Apr 21 01:33:20 PM PDT 24 Apr 21 01:55:50 PM PDT 24 40404940264 ps
T843 /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.533949989 Apr 21 01:33:38 PM PDT 24 Apr 21 02:01:58 PM PDT 24 138659082821 ps
T844 /workspace/coverage/default/10.lc_ctrl_state_post_trans.600425801 Apr 21 01:31:18 PM PDT 24 Apr 21 01:31:26 PM PDT 24 79186045 ps
T845 /workspace/coverage/default/6.lc_ctrl_state_failure.895360915 Apr 21 01:30:45 PM PDT 24 Apr 21 01:31:09 PM PDT 24 880369744 ps
T846 /workspace/coverage/default/30.lc_ctrl_state_failure.1161655842 Apr 21 01:33:15 PM PDT 24 Apr 21 01:33:45 PM PDT 24 486543312 ps
T847 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1114465327 Apr 21 01:31:14 PM PDT 24 Apr 21 01:32:01 PM PDT 24 7446873242 ps
T848 /workspace/coverage/default/43.lc_ctrl_state_post_trans.1729808413 Apr 21 01:34:19 PM PDT 24 Apr 21 01:34:31 PM PDT 24 1453810728 ps
T849 /workspace/coverage/default/8.lc_ctrl_stress_all.4082116092 Apr 21 01:31:08 PM PDT 24 Apr 21 01:34:38 PM PDT 24 12662621360 ps
T850 /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3114223234 Apr 21 01:31:46 PM PDT 24 Apr 21 01:32:01 PM PDT 24 470904571 ps
T851 /workspace/coverage/default/31.lc_ctrl_errors.863133667 Apr 21 01:33:15 PM PDT 24 Apr 21 01:33:27 PM PDT 24 1205500312 ps
T852 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3592112578 Apr 21 01:31:45 PM PDT 24 Apr 21 01:32:22 PM PDT 24 2142989031 ps
T853 /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1177110308 Apr 21 01:29:48 PM PDT 24 Apr 21 01:30:10 PM PDT 24 652839869 ps
T854 /workspace/coverage/default/41.lc_ctrl_sec_mubi.232667950 Apr 21 01:34:06 PM PDT 24 Apr 21 01:34:20 PM PDT 24 1502493854 ps
T855 /workspace/coverage/default/20.lc_ctrl_prog_failure.2686765579 Apr 21 01:32:24 PM PDT 24 Apr 21 01:32:26 PM PDT 24 359147946 ps
T856 /workspace/coverage/default/44.lc_ctrl_state_post_trans.4081695281 Apr 21 01:34:18 PM PDT 24 Apr 21 01:34:26 PM PDT 24 768033692 ps
T857 /workspace/coverage/default/9.lc_ctrl_state_post_trans.4257719478 Apr 21 01:31:12 PM PDT 24 Apr 21 01:31:16 PM PDT 24 379138311 ps
T858 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2642310065 Apr 21 01:32:32 PM PDT 24 Apr 21 01:32:40 PM PDT 24 1686724295 ps
T859 /workspace/coverage/default/28.lc_ctrl_security_escalation.2409229752 Apr 21 01:33:04 PM PDT 24 Apr 21 01:33:16 PM PDT 24 310062319 ps
T860 /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2170120926 Apr 21 01:30:48 PM PDT 24 Apr 21 01:30:54 PM PDT 24 678310593 ps
T861 /workspace/coverage/default/49.lc_ctrl_state_failure.2476904942 Apr 21 01:34:43 PM PDT 24 Apr 21 01:35:08 PM PDT 24 555793002 ps
T862 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3644877828 Apr 21 01:31:16 PM PDT 24 Apr 21 01:31:49 PM PDT 24 4010326862 ps
T863 /workspace/coverage/default/2.lc_ctrl_errors.2863421948 Apr 21 01:30:07 PM PDT 24 Apr 21 01:30:23 PM PDT 24 1371536925 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2366642108 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:10 PM PDT 24 39732586 ps
T122 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.475724400 Apr 21 12:49:22 PM PDT 24 Apr 21 12:49:31 PM PDT 24 293344681 ps
T130 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3166298937 Apr 21 12:49:36 PM PDT 24 Apr 21 12:49:38 PM PDT 24 148660479 ps
T123 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.649006000 Apr 21 12:49:25 PM PDT 24 Apr 21 12:49:28 PM PDT 24 136584680 ps
T131 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2566594956 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:13 PM PDT 24 37419515 ps
T124 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1536523188 Apr 21 12:49:16 PM PDT 24 Apr 21 12:49:20 PM PDT 24 292390727 ps
T200 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2309941287 Apr 21 12:49:20 PM PDT 24 Apr 21 12:49:22 PM PDT 24 13369902 ps
T201 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2615500477 Apr 21 12:49:18 PM PDT 24 Apr 21 12:49:20 PM PDT 24 162411972 ps
T126 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3635274590 Apr 21 12:49:13 PM PDT 24 Apr 21 12:49:15 PM PDT 24 76077210 ps
T127 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4236364908 Apr 21 12:49:23 PM PDT 24 Apr 21 12:49:25 PM PDT 24 144750249 ps
T155 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1833976108 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:10 PM PDT 24 215858634 ps
T125 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1093931852 Apr 21 12:49:30 PM PDT 24 Apr 21 12:49:33 PM PDT 24 891470399 ps
T149 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4267490204 Apr 21 12:49:02 PM PDT 24 Apr 21 12:49:06 PM PDT 24 64946095 ps
T152 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.254152157 Apr 21 12:49:01 PM PDT 24 Apr 21 12:49:04 PM PDT 24 344362059 ps
T191 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3829136769 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:11 PM PDT 24 13594445 ps
T128 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3803554787 Apr 21 12:49:29 PM PDT 24 Apr 21 12:49:31 PM PDT 24 251456138 ps
T153 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.136789430 Apr 21 12:49:15 PM PDT 24 Apr 21 12:49:21 PM PDT 24 502778907 ps
T154 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4241886091 Apr 21 12:48:58 PM PDT 24 Apr 21 12:49:01 PM PDT 24 78994002 ps
T137 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3650294331 Apr 21 12:49:38 PM PDT 24 Apr 21 12:49:42 PM PDT 24 114372281 ps
T129 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2515655358 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:13 PM PDT 24 1585218969 ps
T202 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2946050971 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:09 PM PDT 24 53726658 ps
T142 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2318262517 Apr 21 12:49:01 PM PDT 24 Apr 21 12:49:05 PM PDT 24 126573993 ps
T864 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2528168054 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:17 PM PDT 24 144233364 ps
T141 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1586454463 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:14 PM PDT 24 49058295 ps
T162 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2086538541 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:23 PM PDT 24 27829295 ps
T865 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3916991299 Apr 21 12:48:58 PM PDT 24 Apr 21 12:49:02 PM PDT 24 341734723 ps
T203 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2002921507 Apr 21 12:49:35 PM PDT 24 Apr 21 12:49:37 PM PDT 24 29638529 ps
T135 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2453870352 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:12 PM PDT 24 34470130 ps
T866 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.804130541 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:10 PM PDT 24 33279238 ps
T867 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2336587532 Apr 21 12:49:14 PM PDT 24 Apr 21 12:49:30 PM PDT 24 5528223070 ps
T204 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.805567747 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:10 PM PDT 24 90807968 ps
T868 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1625271132 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:06 PM PDT 24 438395053 ps
T869 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1601281991 Apr 21 12:49:34 PM PDT 24 Apr 21 12:49:35 PM PDT 24 52389918 ps
T870 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1400359901 Apr 21 12:49:17 PM PDT 24 Apr 21 12:49:20 PM PDT 24 351698512 ps
T145 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.352914226 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:14 PM PDT 24 21718250 ps
T871 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1706261684 Apr 21 12:49:02 PM PDT 24 Apr 21 12:49:04 PM PDT 24 30488191 ps
T205 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3711940137 Apr 21 12:49:19 PM PDT 24 Apr 21 12:49:20 PM PDT 24 50212459 ps
T872 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2107651546 Apr 21 12:49:27 PM PDT 24 Apr 21 12:49:29 PM PDT 24 61589853 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1734618666 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:09 PM PDT 24 1405777251 ps
T874 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.966754182 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:14 PM PDT 24 135941231 ps
T875 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.890345298 Apr 21 12:49:26 PM PDT 24 Apr 21 12:49:45 PM PDT 24 2990360243 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1805079788 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:06 PM PDT 24 54678723 ps
T138 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.527052075 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:13 PM PDT 24 108918562 ps
T877 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2561742854 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:08 PM PDT 24 284366259 ps
T878 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2007763804 Apr 21 12:49:15 PM PDT 24 Apr 21 12:49:18 PM PDT 24 75280671 ps
T139 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2192110207 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:06 PM PDT 24 497604318 ps
T206 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2394664389 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:14 PM PDT 24 538122566 ps
T879 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2370796944 Apr 21 12:49:22 PM PDT 24 Apr 21 12:49:23 PM PDT 24 25529156 ps
T143 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2611920246 Apr 21 12:49:37 PM PDT 24 Apr 21 12:49:41 PM PDT 24 128312696 ps
T880 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2497534021 Apr 21 12:49:18 PM PDT 24 Apr 21 12:49:20 PM PDT 24 150655682 ps
T146 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1844636200 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:13 PM PDT 24 77084767 ps
T881 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3713827262 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:13 PM PDT 24 259180210 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.375552365 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:12 PM PDT 24 227323717 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.704589675 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:17 PM PDT 24 21650157 ps
T884 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4037680048 Apr 21 12:49:20 PM PDT 24 Apr 21 12:49:21 PM PDT 24 14796992 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3670019835 Apr 21 12:49:16 PM PDT 24 Apr 21 12:49:18 PM PDT 24 327349995 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2220934087 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:20 PM PDT 24 1343652260 ps
T147 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2593340533 Apr 21 12:49:17 PM PDT 24 Apr 21 12:49:23 PM PDT 24 480857364 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.974394501 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:12 PM PDT 24 273569151 ps
T888 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1729071139 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:23 PM PDT 24 1211632217 ps
T889 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2748109912 Apr 21 12:49:39 PM PDT 24 Apr 21 12:49:40 PM PDT 24 43806241 ps
T890 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1271061896 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:10 PM PDT 24 54151800 ps
T192 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2313716583 Apr 21 12:49:27 PM PDT 24 Apr 21 12:49:29 PM PDT 24 25628332 ps
T891 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.35473335 Apr 21 12:49:06 PM PDT 24 Apr 21 12:49:09 PM PDT 24 81889996 ps
T892 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2289991622 Apr 21 12:49:38 PM PDT 24 Apr 21 12:49:40 PM PDT 24 221464574 ps
T893 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1879578704 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:14 PM PDT 24 140948453 ps
T894 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3940759078 Apr 21 12:49:29 PM PDT 24 Apr 21 12:49:30 PM PDT 24 47409062 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1255781995 Apr 21 12:49:05 PM PDT 24 Apr 21 12:49:07 PM PDT 24 211525988 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3316401006 Apr 21 12:49:06 PM PDT 24 Apr 21 12:49:13 PM PDT 24 1283838342 ps
T897 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3921665324 Apr 21 12:49:32 PM PDT 24 Apr 21 12:49:34 PM PDT 24 58810839 ps
T898 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3309205905 Apr 21 12:49:20 PM PDT 24 Apr 21 12:49:23 PM PDT 24 54828399 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1470077999 Apr 21 12:49:06 PM PDT 24 Apr 21 12:49:08 PM PDT 24 14593211 ps
T900 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1767298702 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:12 PM PDT 24 362270443 ps
T901 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3007719971 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:05 PM PDT 24 100381383 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1721253549 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:12 PM PDT 24 193967158 ps
T903 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2228466414 Apr 21 12:49:02 PM PDT 24 Apr 21 12:49:15 PM PDT 24 2138831071 ps
T904 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3712120357 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:13 PM PDT 24 160066460 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2813036144 Apr 21 12:49:05 PM PDT 24 Apr 21 12:49:07 PM PDT 24 29108202 ps
T193 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2472015688 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:05 PM PDT 24 36656708 ps
T906 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3477959096 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:12 PM PDT 24 33854800 ps
T907 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2541368948 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:20 PM PDT 24 783631590 ps
T908 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.878854315 Apr 21 12:49:22 PM PDT 24 Apr 21 12:49:25 PM PDT 24 231495576 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2579565251 Apr 21 12:49:00 PM PDT 24 Apr 21 12:49:03 PM PDT 24 50777181 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2973283842 Apr 21 12:49:06 PM PDT 24 Apr 21 12:49:09 PM PDT 24 171248138 ps
T911 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3024105072 Apr 21 12:49:05 PM PDT 24 Apr 21 12:49:09 PM PDT 24 776879972 ps
T912 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1399671245 Apr 21 12:49:00 PM PDT 24 Apr 21 12:49:08 PM PDT 24 3371122120 ps
T913 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2310200148 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:28 PM PDT 24 984886298 ps
T914 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1199048215 Apr 21 12:49:41 PM PDT 24 Apr 21 12:49:44 PM PDT 24 125113993 ps
T915 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.420601412 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:13 PM PDT 24 23448904 ps
T916 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1034179208 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:05 PM PDT 24 34913664 ps
T917 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1735434552 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:07 PM PDT 24 43670125 ps
T918 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3807817002 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:06 PM PDT 24 55191091 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3254508708 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:15 PM PDT 24 130943136 ps
T920 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2786414867 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:26 PM PDT 24 3749805311 ps
T921 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2715130816 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:26 PM PDT 24 1075931843 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1580251061 Apr 21 12:49:06 PM PDT 24 Apr 21 12:49:08 PM PDT 24 22042489 ps
T923 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.921937386 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:11 PM PDT 24 176526204 ps
T924 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.689119723 Apr 21 12:49:25 PM PDT 24 Apr 21 12:49:26 PM PDT 24 52909992 ps
T925 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3624617684 Apr 21 12:49:18 PM PDT 24 Apr 21 12:49:20 PM PDT 24 42642693 ps
T926 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2855096336 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:14 PM PDT 24 26017156 ps
T927 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2549292766 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:17 PM PDT 24 360849147 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.802138401 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:10 PM PDT 24 46939014 ps
T929 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1243605916 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:16 PM PDT 24 476048607 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.889109578 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:13 PM PDT 24 210851669 ps
T931 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3178848816 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:14 PM PDT 24 427746714 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.138436737 Apr 21 12:48:59 PM PDT 24 Apr 21 12:49:25 PM PDT 24 1074629236 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1116064758 Apr 21 12:49:18 PM PDT 24 Apr 21 12:49:21 PM PDT 24 1252809753 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1352320221 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:09 PM PDT 24 43475723 ps
T935 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.959854749 Apr 21 12:49:06 PM PDT 24 Apr 21 12:49:09 PM PDT 24 80296291 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3517850374 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:06 PM PDT 24 139005462 ps
T937 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2289442929 Apr 21 12:49:18 PM PDT 24 Apr 21 12:49:20 PM PDT 24 121707112 ps
T938 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3563567818 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:12 PM PDT 24 79682802 ps
T939 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.264594443 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:15 PM PDT 24 33791999 ps
T940 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1371594965 Apr 21 12:49:21 PM PDT 24 Apr 21 12:49:24 PM PDT 24 101247902 ps
T941 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.572843170 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:13 PM PDT 24 191134078 ps
T942 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2269045418 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:11 PM PDT 24 38936524 ps
T943 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.611344918 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:06 PM PDT 24 28556263 ps
T944 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2859117441 Apr 21 12:49:15 PM PDT 24 Apr 21 12:49:16 PM PDT 24 66950751 ps
T144 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3314197334 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:12 PM PDT 24 49682535 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1737427739 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:07 PM PDT 24 196289754 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3008910001 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:10 PM PDT 24 352596076 ps
T947 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1698084120 Apr 21 12:49:05 PM PDT 24 Apr 21 12:49:16 PM PDT 24 470847348 ps
T948 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3414701016 Apr 21 12:49:33 PM PDT 24 Apr 21 12:49:34 PM PDT 24 36579193 ps
T949 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2638379669 Apr 21 12:49:27 PM PDT 24 Apr 21 12:49:28 PM PDT 24 38107016 ps
T950 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1981996581 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:09 PM PDT 24 58967367 ps
T951 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1788358047 Apr 21 12:49:05 PM PDT 24 Apr 21 12:49:16 PM PDT 24 862293064 ps
T952 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1329120988 Apr 21 12:49:04 PM PDT 24 Apr 21 12:49:07 PM PDT 24 506697217 ps
T953 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4047958150 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:12 PM PDT 24 54966745 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4285562783 Apr 21 12:48:56 PM PDT 24 Apr 21 12:48:58 PM PDT 24 153490329 ps
T194 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.23004666 Apr 21 12:49:17 PM PDT 24 Apr 21 12:49:19 PM PDT 24 20425286 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3028300809 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:17 PM PDT 24 186885488 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3669654658 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:13 PM PDT 24 372839986 ps
T195 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1146712897 Apr 21 12:49:27 PM PDT 24 Apr 21 12:49:28 PM PDT 24 21731239 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2674174604 Apr 21 12:49:32 PM PDT 24 Apr 21 12:49:38 PM PDT 24 185574410 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1095850015 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:11 PM PDT 24 16647121 ps
T136 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3857104149 Apr 21 12:49:26 PM PDT 24 Apr 21 12:49:30 PM PDT 24 193493186 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1612051719 Apr 21 12:49:24 PM PDT 24 Apr 21 12:49:25 PM PDT 24 12697931 ps
T960 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1298242361 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:13 PM PDT 24 36798907 ps
T961 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3606133240 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:13 PM PDT 24 32791362 ps
T140 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1027518393 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:14 PM PDT 24 64758393 ps
T962 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3634036777 Apr 21 12:49:19 PM PDT 24 Apr 21 12:49:24 PM PDT 24 135557615 ps
T148 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1869433825 Apr 21 12:49:23 PM PDT 24 Apr 21 12:49:26 PM PDT 24 61202350 ps
T963 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1339892390 Apr 21 12:49:20 PM PDT 24 Apr 21 12:49:23 PM PDT 24 44459811 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3998971980 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:13 PM PDT 24 30815630 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2987484910 Apr 21 12:49:19 PM PDT 24 Apr 21 12:49:21 PM PDT 24 21563142 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1045996366 Apr 21 12:48:53 PM PDT 24 Apr 21 12:48:55 PM PDT 24 19481702 ps
T967 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2438355774 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:22 PM PDT 24 1942245798 ps
T132 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1041270374 Apr 21 12:49:14 PM PDT 24 Apr 21 12:49:17 PM PDT 24 302488725 ps
T968 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.640969391 Apr 21 12:49:03 PM PDT 24 Apr 21 12:49:08 PM PDT 24 128991886 ps
T969 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3808162892 Apr 21 12:49:02 PM PDT 24 Apr 21 12:49:04 PM PDT 24 123666357 ps
T151 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.599379621 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:14 PM PDT 24 66847328 ps
T970 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.534792761 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:12 PM PDT 24 42279356 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4219272718 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:14 PM PDT 24 24062188 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2732824678 Apr 21 12:49:46 PM PDT 24 Apr 21 12:49:48 PM PDT 24 280698593 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3497216936 Apr 21 12:49:00 PM PDT 24 Apr 21 12:49:02 PM PDT 24 114009488 ps
T974 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2225481990 Apr 21 12:49:09 PM PDT 24 Apr 21 12:49:12 PM PDT 24 167405857 ps
T975 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2088249997 Apr 21 12:49:20 PM PDT 24 Apr 21 12:49:21 PM PDT 24 28716483 ps
T196 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1338274485 Apr 21 12:49:31 PM PDT 24 Apr 21 12:49:33 PM PDT 24 14349780 ps
T197 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3585290552 Apr 21 12:49:20 PM PDT 24 Apr 21 12:49:22 PM PDT 24 179307766 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2826896824 Apr 21 12:49:01 PM PDT 24 Apr 21 12:49:03 PM PDT 24 73413508 ps
T977 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1099329617 Apr 21 12:49:36 PM PDT 24 Apr 21 12:49:38 PM PDT 24 46111573 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3475955889 Apr 21 12:49:13 PM PDT 24 Apr 21 12:49:15 PM PDT 24 69933097 ps
T134 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1373507543 Apr 21 12:49:05 PM PDT 24 Apr 21 12:49:08 PM PDT 24 132738911 ps
T979 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4205387637 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:09 PM PDT 24 257338219 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3715067427 Apr 21 12:49:16 PM PDT 24 Apr 21 12:49:18 PM PDT 24 157257898 ps
T150 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1965172865 Apr 21 12:49:17 PM PDT 24 Apr 21 12:49:21 PM PDT 24 105643616 ps
T981 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3258335783 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:12 PM PDT 24 15691828 ps
T982 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2695044469 Apr 21 12:49:26 PM PDT 24 Apr 21 12:49:28 PM PDT 24 81411089 ps
T983 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.846350548 Apr 21 12:49:35 PM PDT 24 Apr 21 12:49:37 PM PDT 24 52317736 ps
T984 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3000364310 Apr 21 12:49:18 PM PDT 24 Apr 21 12:49:20 PM PDT 24 22066682 ps
T985 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2877323104 Apr 21 12:49:15 PM PDT 24 Apr 21 12:49:16 PM PDT 24 59176127 ps
T986 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3615563483 Apr 21 12:49:08 PM PDT 24 Apr 21 12:49:10 PM PDT 24 69752817 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3387169721 Apr 21 12:49:07 PM PDT 24 Apr 21 12:49:09 PM PDT 24 43951381 ps
T988 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3728272359 Apr 21 12:49:12 PM PDT 24 Apr 21 12:49:14 PM PDT 24 167069528 ps
T198 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3889828040 Apr 21 12:49:05 PM PDT 24 Apr 21 12:49:07 PM PDT 24 75606479 ps
T989 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.751204537 Apr 21 12:49:17 PM PDT 24 Apr 21 12:49:19 PM PDT 24 56452000 ps
T990 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.635614261 Apr 21 12:49:31 PM PDT 24 Apr 21 12:49:33 PM PDT 24 44800543 ps
T199 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3449050314 Apr 21 12:49:22 PM PDT 24 Apr 21 12:49:23 PM PDT 24 17489330 ps
T991 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2580858873 Apr 21 12:48:57 PM PDT 24 Apr 21 12:49:00 PM PDT 24 304791300 ps
T992 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3084754414 Apr 21 12:49:20 PM PDT 24 Apr 21 12:49:22 PM PDT 24 657790813 ps
T993 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4280750321 Apr 21 12:49:10 PM PDT 24 Apr 21 12:49:16 PM PDT 24 399199994 ps
T994 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3286582414 Apr 21 12:49:11 PM PDT 24 Apr 21 12:49:14 PM PDT 24 35486083 ps
T995 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2337799488 Apr 21 12:49:25 PM PDT 24 Apr 21 12:49:27 PM PDT 24 76383543 ps
T996 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4171724076 Apr 21 12:49:16 PM PDT 24 Apr 21 12:49:18 PM PDT 24 351361857 ps
T997 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2467330023 Apr 21 12:49:06 PM PDT 24 Apr 21 12:49:07 PM PDT 24 14992949 ps

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3795911187
Short name T2
Test name
Test status
Simulation time 1194393146 ps
CPU time 12.39 seconds
Started Apr 21 01:34:07 PM PDT 24
Finished Apr 21 01:34:20 PM PDT 24
Peak memory 225992 kb
Host smart-9780df8f-4909-458b-941b-6f93d24dfce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795911187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3795911187
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3932178204
Short name T23
Test name
Test status
Simulation time 51438297626 ps
CPU time 431.22 seconds
Started Apr 21 01:33:50 PM PDT 24
Finished Apr 21 01:41:02 PM PDT 24
Peak memory 300212 kb
Host smart-e508ecab-8ed2-47ba-b044-63f45a199d75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3932178204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3932178204
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.846488257
Short name T12
Test name
Test status
Simulation time 1242451671 ps
CPU time 9.39 seconds
Started Apr 21 01:32:28 PM PDT 24
Finished Apr 21 01:32:38 PM PDT 24
Peak memory 225968 kb
Host smart-0b5a5dca-4e66-41c5-b3da-1096ad05e4b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846488257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.846488257
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3031306037
Short name T163
Test name
Test status
Simulation time 475451291 ps
CPU time 10.58 seconds
Started Apr 21 01:33:28 PM PDT 24
Finished Apr 21 01:33:39 PM PDT 24
Peak memory 225964 kb
Host smart-e7a2b1c8-4477-4a79-812c-0b7403a8e13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031306037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3031306037
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1331396859
Short name T52
Test name
Test status
Simulation time 34851262269 ps
CPU time 2032.41 seconds
Started Apr 21 01:34:16 PM PDT 24
Finished Apr 21 02:08:09 PM PDT 24
Peak memory 1537612 kb
Host smart-98751227-c4bc-4dbd-a903-414c055f8e11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1331396859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1331396859
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1536523188
Short name T124
Test name
Test status
Simulation time 292390727 ps
CPU time 3.32 seconds
Started Apr 21 12:49:16 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 222664 kb
Host smart-23ccea5e-bd8e-43e9-9aa5-b73c225a3b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536523188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1536523188
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1585352295
Short name T14
Test name
Test status
Simulation time 18016429 ps
CPU time 0.73 seconds
Started Apr 21 01:31:21 PM PDT 24
Finished Apr 21 01:31:22 PM PDT 24
Peak memory 208360 kb
Host smart-c16d6028-f58b-4707-8a03-a8c206ff77f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585352295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1585352295
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2515655358
Short name T129
Test name
Test status
Simulation time 1585218969 ps
CPU time 4.96 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 218204 kb
Host smart-cf83a5c3-4784-463c-ab4b-68b5ed84eaa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251565
5358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2515655358
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3818754796
Short name T61
Test name
Test status
Simulation time 239641662 ps
CPU time 21.07 seconds
Started Apr 21 01:30:06 PM PDT 24
Finished Apr 21 01:30:28 PM PDT 24
Peak memory 281352 kb
Host smart-4cda2cd3-1eec-45b4-9d77-84c79c0cdae6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818754796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3818754796
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3072197414
Short name T11
Test name
Test status
Simulation time 547462528 ps
CPU time 27.38 seconds
Started Apr 21 01:30:26 PM PDT 24
Finished Apr 21 01:30:54 PM PDT 24
Peak memory 248576 kb
Host smart-5ec1aafe-e36d-473c-9177-5d79ca491432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072197414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3072197414
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2007199268
Short name T9
Test name
Test status
Simulation time 1414722817 ps
CPU time 2.88 seconds
Started Apr 21 01:31:44 PM PDT 24
Finished Apr 21 01:31:48 PM PDT 24
Peak memory 209468 kb
Host smart-1eee2515-b7cb-4e68-bbde-eb97c9b92f8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007199268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2007199268
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1381825188
Short name T51
Test name
Test status
Simulation time 2787235862 ps
CPU time 13.21 seconds
Started Apr 21 01:30:01 PM PDT 24
Finished Apr 21 01:30:15 PM PDT 24
Peak memory 217984 kb
Host smart-58ef3cde-d596-4948-a748-c5430a722e75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381825188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
381825188
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1642854175
Short name T15
Test name
Test status
Simulation time 17329451 ps
CPU time 0.91 seconds
Started Apr 21 01:32:28 PM PDT 24
Finished Apr 21 01:32:29 PM PDT 24
Peak memory 209444 kb
Host smart-17dee55b-26c6-4744-bb1e-70e67354f513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642854175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1642854175
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2366642108
Short name T133
Test name
Test status
Simulation time 39732586 ps
CPU time 1.29 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 209148 kb
Host smart-04ac51ab-3221-4c42-8248-600c9b584f37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366642108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2366642108
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3334677081
Short name T48
Test name
Test status
Simulation time 54410227 ps
CPU time 7.45 seconds
Started Apr 21 01:32:06 PM PDT 24
Finished Apr 21 01:32:14 PM PDT 24
Peak memory 248708 kb
Host smart-ed6c8333-8658-427b-b579-c9665e4fa7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334677081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3334677081
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1334355932
Short name T90
Test name
Test status
Simulation time 54041502571 ps
CPU time 441.81 seconds
Started Apr 21 01:33:59 PM PDT 24
Finished Apr 21 01:41:21 PM PDT 24
Peak memory 447648 kb
Host smart-946d0e1d-2808-4939-a6e3-60abad83a529
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1334355932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1334355932
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3712120357
Short name T904
Test name
Test status
Simulation time 160066460 ps
CPU time 4.22 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 217860 kb
Host smart-6132f620-9ab4-42c1-aee8-89eb20fedc86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712120357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3712120357
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3171559852
Short name T49
Test name
Test status
Simulation time 525316289 ps
CPU time 10.09 seconds
Started Apr 21 01:32:30 PM PDT 24
Finished Apr 21 01:32:41 PM PDT 24
Peak memory 217928 kb
Host smart-5e333d5c-b524-4a60-95ad-11f05b94fa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171559852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3171559852
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.475724400
Short name T122
Test name
Test status
Simulation time 293344681 ps
CPU time 3.27 seconds
Started Apr 21 12:49:22 PM PDT 24
Finished Apr 21 12:49:31 PM PDT 24
Peak memory 217720 kb
Host smart-4e2f1f93-4b6d-4108-8afe-7a45d27f3e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475724400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.475724400
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1965172865
Short name T150
Test name
Test status
Simulation time 105643616 ps
CPU time 2.86 seconds
Started Apr 21 12:49:17 PM PDT 24
Finished Apr 21 12:49:21 PM PDT 24
Peak memory 222480 kb
Host smart-6ffeec78-8c53-4545-8037-bca0e6aafb3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965172865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1965172865
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2507590885
Short name T96
Test name
Test status
Simulation time 16052468009 ps
CPU time 584.88 seconds
Started Apr 21 01:33:43 PM PDT 24
Finished Apr 21 01:43:28 PM PDT 24
Peak memory 513312 kb
Host smart-15f26403-e7c9-45e0-ac51-46821beb45e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2507590885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2507590885
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4127290692
Short name T3
Test name
Test status
Simulation time 949959207 ps
CPU time 11.96 seconds
Started Apr 21 01:33:35 PM PDT 24
Finished Apr 21 01:33:47 PM PDT 24
Peak memory 217920 kb
Host smart-d2f8cfe5-c3db-4389-a94d-287dce59ad3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127290692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4127290692
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2566594956
Short name T131
Test name
Test status
Simulation time 37419515 ps
CPU time 1.83 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 211504 kb
Host smart-27c47b57-9487-447c-b870-35aef2fd0c0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566594956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2566594956
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.184009414
Short name T99
Test name
Test status
Simulation time 68052395122 ps
CPU time 811 seconds
Started Apr 21 01:32:17 PM PDT 24
Finished Apr 21 01:45:48 PM PDT 24
Peak memory 282276 kb
Host smart-3eda1404-b26a-406d-ba04-b33f4b78ee43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=184009414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.184009414
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3857104149
Short name T136
Test name
Test status
Simulation time 193493186 ps
CPU time 3.31 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:49:30 PM PDT 24
Peak memory 221960 kb
Host smart-1c720d90-5966-4d32-8e95-a58d4f00dfc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857104149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3857104149
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1093931852
Short name T125
Test name
Test status
Simulation time 891470399 ps
CPU time 2.48 seconds
Started Apr 21 12:49:30 PM PDT 24
Finished Apr 21 12:49:33 PM PDT 24
Peak memory 217816 kb
Host smart-34d760b4-cfeb-4f1c-9b5e-e4ae89b048df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093931852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1093931852
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3650294331
Short name T137
Test name
Test status
Simulation time 114372281 ps
CPU time 3.15 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:49:42 PM PDT 24
Peak memory 222172 kb
Host smart-27185912-194f-42eb-bed5-9d659c596c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650294331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3650294331
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.599379621
Short name T151
Test name
Test status
Simulation time 66847328 ps
CPU time 1.95 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 222260 kb
Host smart-eecfd3bd-e3dd-423c-a8f3-d82b503c20c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599379621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.599379621
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1168154649
Short name T211
Test name
Test status
Simulation time 12953086 ps
CPU time 1.01 seconds
Started Apr 21 01:29:52 PM PDT 24
Finished Apr 21 01:29:53 PM PDT 24
Peak memory 209440 kb
Host smart-f358e458-9e95-4b29-b7df-7a4fb0a1bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168154649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1168154649
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2336050141
Short name T209
Test name
Test status
Simulation time 13786275 ps
CPU time 0.98 seconds
Started Apr 21 01:29:59 PM PDT 24
Finished Apr 21 01:30:01 PM PDT 24
Peak memory 209420 kb
Host smart-42535e40-181a-4e75-a59b-60976e15b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336050141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2336050141
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1206423002
Short name T208
Test name
Test status
Simulation time 12863606 ps
CPU time 0.92 seconds
Started Apr 21 01:30:14 PM PDT 24
Finished Apr 21 01:30:15 PM PDT 24
Peak memory 209388 kb
Host smart-29172e8c-8a2b-43e7-aab1-0a93809b87f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206423002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1206423002
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2330025571
Short name T212
Test name
Test status
Simulation time 33893638 ps
CPU time 0.75 seconds
Started Apr 21 01:30:52 PM PDT 24
Finished Apr 21 01:30:54 PM PDT 24
Peak memory 209292 kb
Host smart-d535d52b-450a-473c-a53d-dea20b1c1d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330025571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2330025571
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4286700636
Short name T47
Test name
Test status
Simulation time 363540703 ps
CPU time 14.79 seconds
Started Apr 21 01:33:02 PM PDT 24
Finished Apr 21 01:33:17 PM PDT 24
Peak memory 217964 kb
Host smart-85c150c4-b514-4158-a6c6-051a8fec16bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286700636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4286700636
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1734618666
Short name T873
Test name
Test status
Simulation time 1405777251 ps
CPU time 3.69 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 209196 kb
Host smart-731ba86b-68d0-48dc-afb4-8279b4458949
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734618666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1734618666
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3314197334
Short name T144
Test name
Test status
Simulation time 49682535 ps
CPU time 2.51 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 217780 kb
Host smart-25a8c736-c150-4729-bb9e-8160ab1c1af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314197334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3314197334
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1027518393
Short name T140
Test name
Test status
Simulation time 64758393 ps
CPU time 2.03 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 221836 kb
Host smart-713c09bd-6b08-4897-a7e7-4ce12d027b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027518393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1027518393
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1041270374
Short name T132
Test name
Test status
Simulation time 302488725 ps
CPU time 2.49 seconds
Started Apr 21 12:49:14 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 222268 kb
Host smart-8d1d8d45-e362-44aa-93be-79236b2522ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041270374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1041270374
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4267490204
Short name T149
Test name
Test status
Simulation time 64946095 ps
CPU time 2.66 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 217776 kb
Host smart-f88b2b1c-6494-4c95-934f-1dc607236d71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267490204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4267490204
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.498376083
Short name T237
Test name
Test status
Simulation time 157686907 ps
CPU time 5.68 seconds
Started Apr 21 01:31:39 PM PDT 24
Finished Apr 21 01:31:44 PM PDT 24
Peak memory 217860 kb
Host smart-940a3837-33ef-4671-9039-23b72b5db78c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498376083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.498376083
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.4187455566
Short name T25
Test name
Test status
Simulation time 96334317 ps
CPU time 7.65 seconds
Started Apr 21 01:29:47 PM PDT 24
Finished Apr 21 01:29:55 PM PDT 24
Peak memory 246864 kb
Host smart-3a3b7863-57e0-42ff-b786-cc29029b65c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187455566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.4187455566
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3007719971
Short name T901
Test name
Test status
Simulation time 100381383 ps
CPU time 1.02 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 209584 kb
Host smart-efb3eb20-3b78-432a-ae23-81649f05b343
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007719971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3007719971
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4285562783
Short name T954
Test name
Test status
Simulation time 153490329 ps
CPU time 2.17 seconds
Started Apr 21 12:48:56 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 209500 kb
Host smart-38654a7c-b0d1-49db-bd94-fb155517b7f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285562783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.4285562783
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1271061896
Short name T890
Test name
Test status
Simulation time 54151800 ps
CPU time 0.98 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 209980 kb
Host smart-e52c20fa-50bd-465d-be11-782c8a3ddab9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271061896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1271061896
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.959854749
Short name T935
Test name
Test status
Simulation time 80296291 ps
CPU time 1.78 seconds
Started Apr 21 12:49:06 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 219756 kb
Host smart-93878a84-45b0-46e7-a087-f5067722cc15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959854749 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.959854749
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1034179208
Short name T916
Test name
Test status
Simulation time 34913664 ps
CPU time 0.96 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 209492 kb
Host smart-8ed10849-8322-49b2-a6f8-47f2b596ab5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034179208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1034179208
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3715067427
Short name T980
Test name
Test status
Simulation time 157257898 ps
CPU time 1.36 seconds
Started Apr 21 12:49:16 PM PDT 24
Finished Apr 21 12:49:18 PM PDT 24
Peak memory 209416 kb
Host smart-3f7c84b5-1c10-4d28-81c0-5db668d149d7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715067427 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3715067427
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.138436737
Short name T932
Test name
Test status
Simulation time 1074629236 ps
CPU time 25.02 seconds
Started Apr 21 12:48:59 PM PDT 24
Finished Apr 21 12:49:25 PM PDT 24
Peak memory 209480 kb
Host smart-02ff44a6-406d-4f7e-a301-09991dff42f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138436737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.138436737
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3669654658
Short name T956
Test name
Test status
Simulation time 372839986 ps
CPU time 2.05 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 210856 kb
Host smart-fb5fbfbc-9464-4ee3-9cac-64bbdcf2c3b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669654658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3669654658
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1243605916
Short name T929
Test name
Test status
Simulation time 476048607 ps
CPU time 3.28 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:16 PM PDT 24
Peak memory 218132 kb
Host smart-d9372dec-a93b-4579-ac81-3ac9f0dd0dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124360
5916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1243605916
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.254152157
Short name T152
Test name
Test status
Simulation time 344362059 ps
CPU time 2.76 seconds
Started Apr 21 12:49:01 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 209536 kb
Host smart-83d9e918-8e9f-479e-85ad-fea599545320
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254152157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.254152157
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3808162892
Short name T969
Test name
Test status
Simulation time 123666357 ps
CPU time 1.09 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 209656 kb
Host smart-94e890e5-cac0-42bd-bbc7-5222285186f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808162892 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3808162892
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2826896824
Short name T976
Test name
Test status
Simulation time 73413508 ps
CPU time 1.48 seconds
Started Apr 21 12:49:01 PM PDT 24
Finished Apr 21 12:49:03 PM PDT 24
Peak memory 211600 kb
Host smart-51b54404-f3b5-483c-a29c-732f0c2f645a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826896824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2826896824
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2580858873
Short name T991
Test name
Test status
Simulation time 304791300 ps
CPU time 2.43 seconds
Started Apr 21 12:48:57 PM PDT 24
Finished Apr 21 12:49:00 PM PDT 24
Peak memory 218016 kb
Host smart-b206796c-30db-4286-aaa4-723030e124e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580858873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2580858873
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1255781995
Short name T895
Test name
Test status
Simulation time 211525988 ps
CPU time 1.08 seconds
Started Apr 21 12:49:05 PM PDT 24
Finished Apr 21 12:49:07 PM PDT 24
Peak memory 209400 kb
Host smart-f6db036b-4b48-4d0a-936a-0b7987071b21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255781995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1255781995
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2269045418
Short name T942
Test name
Test status
Simulation time 38936524 ps
CPU time 1.73 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:11 PM PDT 24
Peak memory 208764 kb
Host smart-93106935-7e27-4843-938b-17a0e4bfdf98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269045418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2269045418
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3585290552
Short name T197
Test name
Test status
Simulation time 179307766 ps
CPU time 0.92 seconds
Started Apr 21 12:49:20 PM PDT 24
Finished Apr 21 12:49:22 PM PDT 24
Peak memory 209800 kb
Host smart-cdc9de68-23e4-4c77-9ac1-5439b257e931
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585290552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3585290552
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.611344918
Short name T943
Test name
Test status
Simulation time 28556263 ps
CPU time 1.34 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 219464 kb
Host smart-6b658306-fcba-42bd-b06b-41e43b790317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611344918 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.611344918
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1470077999
Short name T899
Test name
Test status
Simulation time 14593211 ps
CPU time 0.86 seconds
Started Apr 21 12:49:06 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 209608 kb
Host smart-2e2fac21-120a-41c6-a90c-809a5e2ad3f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470077999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1470077999
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3497216936
Short name T973
Test name
Test status
Simulation time 114009488 ps
CPU time 1.44 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 209448 kb
Host smart-67c12523-daf3-4588-9721-906c0135170f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497216936 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3497216936
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2310200148
Short name T913
Test name
Test status
Simulation time 984886298 ps
CPU time 20.72 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 209216 kb
Host smart-104b25b5-3645-4f90-8e83-c7e6a67f1693
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310200148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2310200148
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1399671245
Short name T912
Test name
Test status
Simulation time 3371122120 ps
CPU time 7.48 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 208756 kb
Host smart-8437fc8b-78a7-4626-b900-8d27a6fe3789
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399671245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1399671245
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.974394501
Short name T887
Test name
Test status
Simulation time 273569151 ps
CPU time 1.8 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 210916 kb
Host smart-bc921946-3f53-4d3a-b96e-46a7071ce02a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974394501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.974394501
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2561742854
Short name T877
Test name
Test status
Simulation time 284366259 ps
CPU time 3.98 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 219792 kb
Host smart-4fa6a171-0488-4eb5-878b-94207d4a126c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256174
2854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2561742854
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2007763804
Short name T878
Test name
Test status
Simulation time 75280671 ps
CPU time 1.95 seconds
Started Apr 21 12:49:15 PM PDT 24
Finished Apr 21 12:49:18 PM PDT 24
Peak memory 209496 kb
Host smart-a19db335-df2b-4165-9edb-50ee5abbb727
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007763804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2007763804
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3563567818
Short name T938
Test name
Test status
Simulation time 79682802 ps
CPU time 1.27 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 209596 kb
Host smart-f441b07e-8369-4fa2-a987-3516d9679741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563567818 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3563567818
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.35473335
Short name T891
Test name
Test status
Simulation time 81889996 ps
CPU time 2.92 seconds
Started Apr 21 12:49:06 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 218028 kb
Host smart-608fd7db-d752-454c-b946-5c5873b80f94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.35473335
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2318262517
Short name T142
Test name
Test status
Simulation time 126573993 ps
CPU time 2.64 seconds
Started Apr 21 12:49:01 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 217700 kb
Host smart-c51ca54b-458a-46be-9c2d-4c9f0e52d5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318262517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2318262517
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2289991622
Short name T892
Test name
Test status
Simulation time 221464574 ps
CPU time 1.18 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:49:40 PM PDT 24
Peak memory 219668 kb
Host smart-687b4d6f-96e8-4708-a738-3c0dd921195b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289991622 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2289991622
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3258335783
Short name T981
Test name
Test status
Simulation time 15691828 ps
CPU time 0.9 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 209144 kb
Host smart-9d36fc57-22bd-43d8-8140-a618a7ac7d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258335783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3258335783
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3606133240
Short name T961
Test name
Test status
Simulation time 32791362 ps
CPU time 1.33 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 209496 kb
Host smart-08d17186-cdbb-4414-9b10-ac7c041eb3b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606133240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3606133240
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.572843170
Short name T941
Test name
Test status
Simulation time 191134078 ps
CPU time 3.68 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 218064 kb
Host smart-b445ba8f-4b92-4436-a732-bcce675d4031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572843170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.572843170
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.878854315
Short name T908
Test name
Test status
Simulation time 231495576 ps
CPU time 2.58 seconds
Started Apr 21 12:49:22 PM PDT 24
Finished Apr 21 12:49:25 PM PDT 24
Peak memory 217784 kb
Host smart-a33d6466-e21a-4311-821f-b4a3f28840cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878854315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.878854315
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3940759078
Short name T894
Test name
Test status
Simulation time 47409062 ps
CPU time 1.09 seconds
Started Apr 21 12:49:29 PM PDT 24
Finished Apr 21 12:49:30 PM PDT 24
Peak memory 219616 kb
Host smart-35e0e836-b55e-448d-bbf4-f8e535774933
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940759078 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3940759078
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3414701016
Short name T948
Test name
Test status
Simulation time 36579193 ps
CPU time 0.95 seconds
Started Apr 21 12:49:33 PM PDT 24
Finished Apr 21 12:49:34 PM PDT 24
Peak memory 209548 kb
Host smart-3588781a-7342-404e-b06a-8252232a52b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414701016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3414701016
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2337799488
Short name T995
Test name
Test status
Simulation time 76383543 ps
CPU time 1.81 seconds
Started Apr 21 12:49:25 PM PDT 24
Finished Apr 21 12:49:27 PM PDT 24
Peak memory 209712 kb
Host smart-75c6ee87-ae2f-4ee7-aae2-1eb941de546c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337799488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2337799488
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3713827262
Short name T881
Test name
Test status
Simulation time 259180210 ps
CPU time 2.31 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 217880 kb
Host smart-ce7caf04-43b5-4e30-ab39-4339bcc762d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713827262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3713827262
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2370796944
Short name T879
Test name
Test status
Simulation time 25529156 ps
CPU time 1.27 seconds
Started Apr 21 12:49:22 PM PDT 24
Finished Apr 21 12:49:23 PM PDT 24
Peak memory 217784 kb
Host smart-e1d23e10-a637-4081-9218-413782591201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370796944 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2370796944
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1298242361
Short name T960
Test name
Test status
Simulation time 36798907 ps
CPU time 0.84 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 209432 kb
Host smart-c4196d57-025b-48ab-b92a-1edade30d8a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298242361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1298242361
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3166298937
Short name T130
Test name
Test status
Simulation time 148660479 ps
CPU time 1.31 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 209528 kb
Host smart-734ecf00-4022-49c4-ba3f-89bc190ba5ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166298937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3166298937
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4236364908
Short name T127
Test name
Test status
Simulation time 144750249 ps
CPU time 2.15 seconds
Started Apr 21 12:49:23 PM PDT 24
Finished Apr 21 12:49:25 PM PDT 24
Peak memory 217784 kb
Host smart-c0c46dba-ee56-4b82-a971-4475069376ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236364908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4236364908
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3624617684
Short name T925
Test name
Test status
Simulation time 42642693 ps
CPU time 1.42 seconds
Started Apr 21 12:49:18 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 217904 kb
Host smart-37d2c496-daf0-457f-a346-b1e5188784a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624617684 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3624617684
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2859117441
Short name T944
Test name
Test status
Simulation time 66950751 ps
CPU time 1.11 seconds
Started Apr 21 12:49:15 PM PDT 24
Finished Apr 21 12:49:16 PM PDT 24
Peak memory 209520 kb
Host smart-1f4d1eb8-037e-4ca5-817a-c523074952cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859117441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2859117441
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3000364310
Short name T984
Test name
Test status
Simulation time 22066682 ps
CPU time 1.38 seconds
Started Apr 21 12:49:18 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 211356 kb
Host smart-16b34407-2742-4c70-9948-8d6f7b9fc761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000364310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3000364310
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.649006000
Short name T123
Test name
Test status
Simulation time 136584680 ps
CPU time 1.98 seconds
Started Apr 21 12:49:25 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 219144 kb
Host smart-31316105-a6af-4694-aa32-139bbf3058ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649006000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.649006000
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2638379669
Short name T949
Test name
Test status
Simulation time 38107016 ps
CPU time 1.23 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 217936 kb
Host smart-959214dd-07df-4bef-986c-9e1b4996673d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638379669 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2638379669
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2748109912
Short name T889
Test name
Test status
Simulation time 43806241 ps
CPU time 0.87 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:49:40 PM PDT 24
Peak memory 209532 kb
Host smart-1d341424-12e1-4ce5-8c0c-fd375f5c67f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748109912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2748109912
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2695044469
Short name T982
Test name
Test status
Simulation time 81411089 ps
CPU time 1.25 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 209528 kb
Host smart-04337d03-c63d-4863-b584-328fc4d42ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695044469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2695044469
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2611920246
Short name T143
Test name
Test status
Simulation time 128312696 ps
CPU time 2.86 seconds
Started Apr 21 12:49:37 PM PDT 24
Finished Apr 21 12:49:41 PM PDT 24
Peak memory 218588 kb
Host smart-5e87f392-14c3-41e3-a940-fe22c340b0fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611920246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2611920246
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.352914226
Short name T145
Test name
Test status
Simulation time 21718250 ps
CPU time 1.43 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 218460 kb
Host smart-351f1da0-b32a-42ea-a165-4b2720deb502
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352914226 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.352914226
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2313716583
Short name T192
Test name
Test status
Simulation time 25628332 ps
CPU time 1.04 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 12:49:29 PM PDT 24
Peak memory 209220 kb
Host smart-d82a7e25-c170-4c12-b404-8079e021c103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313716583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2313716583
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3711940137
Short name T205
Test name
Test status
Simulation time 50212459 ps
CPU time 1.13 seconds
Started Apr 21 12:49:19 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 209608 kb
Host smart-ddf4b9c4-7fd9-4179-a709-b012d128730e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711940137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3711940137
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3309205905
Short name T898
Test name
Test status
Simulation time 54828399 ps
CPU time 2.03 seconds
Started Apr 21 12:49:20 PM PDT 24
Finished Apr 21 12:49:23 PM PDT 24
Peak memory 217920 kb
Host smart-f6aa9ec9-0a4f-4e73-a083-fcbc11986864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309205905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3309205905
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.751204537
Short name T989
Test name
Test status
Simulation time 56452000 ps
CPU time 1.26 seconds
Started Apr 21 12:49:17 PM PDT 24
Finished Apr 21 12:49:19 PM PDT 24
Peak memory 217832 kb
Host smart-8ddddc92-779d-4a26-8f6c-a7458252ac86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751204537 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.751204537
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1146712897
Short name T195
Test name
Test status
Simulation time 21731239 ps
CPU time 0.85 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 209524 kb
Host smart-edea0438-0073-46a6-858a-138159cd47b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146712897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1146712897
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2002921507
Short name T203
Test name
Test status
Simulation time 29638529 ps
CPU time 1.44 seconds
Started Apr 21 12:49:35 PM PDT 24
Finished Apr 21 12:49:37 PM PDT 24
Peak memory 209672 kb
Host smart-4798c428-c3a9-4384-8eff-30096195d259
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002921507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2002921507
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3803554787
Short name T128
Test name
Test status
Simulation time 251456138 ps
CPU time 1.73 seconds
Started Apr 21 12:49:29 PM PDT 24
Finished Apr 21 12:49:31 PM PDT 24
Peak memory 218620 kb
Host smart-72c4bdfb-2f7e-4f34-8ed2-ac555718afa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803554787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3803554787
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1601281991
Short name T869
Test name
Test status
Simulation time 52389918 ps
CPU time 1.02 seconds
Started Apr 21 12:49:34 PM PDT 24
Finished Apr 21 12:49:35 PM PDT 24
Peak memory 217752 kb
Host smart-0bcce7c2-6191-45c8-865c-8102aba177d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601281991 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1601281991
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1338274485
Short name T196
Test name
Test status
Simulation time 14349780 ps
CPU time 0.94 seconds
Started Apr 21 12:49:31 PM PDT 24
Finished Apr 21 12:49:33 PM PDT 24
Peak memory 209524 kb
Host smart-58f3a29a-1632-42e0-be15-98934e8d577c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338274485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1338274485
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4037680048
Short name T884
Test name
Test status
Simulation time 14796992 ps
CPU time 1.17 seconds
Started Apr 21 12:49:20 PM PDT 24
Finished Apr 21 12:49:21 PM PDT 24
Peak memory 209564 kb
Host smart-0411a689-992b-408a-8582-89ab26a17dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037680048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.4037680048
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3634036777
Short name T962
Test name
Test status
Simulation time 135557615 ps
CPU time 4.98 seconds
Started Apr 21 12:49:19 PM PDT 24
Finished Apr 21 12:49:24 PM PDT 24
Peak memory 217892 kb
Host smart-7c5069ec-0f5a-4462-8b44-3dd456173963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634036777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3634036777
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1371594965
Short name T940
Test name
Test status
Simulation time 101247902 ps
CPU time 3.02 seconds
Started Apr 21 12:49:21 PM PDT 24
Finished Apr 21 12:49:24 PM PDT 24
Peak memory 222320 kb
Host smart-327e703b-1aab-4c9b-aff9-c1e21977b8da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371594965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1371594965
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1099329617
Short name T977
Test name
Test status
Simulation time 46111573 ps
CPU time 2.04 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 223108 kb
Host smart-11cf5289-54af-4567-8649-d06c83e30a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099329617 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1099329617
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2877323104
Short name T985
Test name
Test status
Simulation time 59176127 ps
CPU time 0.84 seconds
Started Apr 21 12:49:15 PM PDT 24
Finished Apr 21 12:49:16 PM PDT 24
Peak memory 209488 kb
Host smart-1bb10d35-f216-4bcd-9a1f-d4918ed13505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877323104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2877323104
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.689119723
Short name T924
Test name
Test status
Simulation time 52909992 ps
CPU time 0.97 seconds
Started Apr 21 12:49:25 PM PDT 24
Finished Apr 21 12:49:26 PM PDT 24
Peak memory 209476 kb
Host smart-6891f3da-8720-4920-939b-01d7307e9027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689119723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.689119723
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3921665324
Short name T897
Test name
Test status
Simulation time 58810839 ps
CPU time 2.63 seconds
Started Apr 21 12:49:32 PM PDT 24
Finished Apr 21 12:49:34 PM PDT 24
Peak memory 217892 kb
Host smart-def8c5ad-e7f7-4d59-9693-4e2c525a228e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921665324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3921665324
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2289442929
Short name T937
Test name
Test status
Simulation time 121707112 ps
CPU time 1.39 seconds
Started Apr 21 12:49:18 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 219512 kb
Host smart-716e7520-e856-4da3-9634-8460349a3815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289442929 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2289442929
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3449050314
Short name T199
Test name
Test status
Simulation time 17489330 ps
CPU time 0.97 seconds
Started Apr 21 12:49:22 PM PDT 24
Finished Apr 21 12:49:23 PM PDT 24
Peak memory 209560 kb
Host smart-9cf71315-1263-47c6-8ae7-409e3004663a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449050314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3449050314
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2615500477
Short name T201
Test name
Test status
Simulation time 162411972 ps
CPU time 1.33 seconds
Started Apr 21 12:49:18 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 211640 kb
Host smart-1d764fa2-2c5b-42b6-b39f-4d2a10ac55c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615500477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2615500477
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.635614261
Short name T990
Test name
Test status
Simulation time 44800543 ps
CPU time 1.76 seconds
Started Apr 21 12:49:31 PM PDT 24
Finished Apr 21 12:49:33 PM PDT 24
Peak memory 217788 kb
Host smart-9773bbee-577b-4ece-9598-97d2168d9cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635614261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.635614261
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1869433825
Short name T148
Test name
Test status
Simulation time 61202350 ps
CPU time 2.71 seconds
Started Apr 21 12:49:23 PM PDT 24
Finished Apr 21 12:49:26 PM PDT 24
Peak memory 217844 kb
Host smart-6ebf1224-91e0-42e5-acd4-292336c7585f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869433825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1869433825
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2472015688
Short name T193
Test name
Test status
Simulation time 36656708 ps
CPU time 1.3 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 209588 kb
Host smart-3b7a420c-b8bb-422f-8612-1369778cc6bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472015688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2472015688
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3254508708
Short name T919
Test name
Test status
Simulation time 130943136 ps
CPU time 2.65 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:15 PM PDT 24
Peak memory 209564 kb
Host smart-70fbbafe-f1bf-4907-a0bf-e4bd3c1bb557
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254508708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3254508708
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3807817002
Short name T918
Test name
Test status
Simulation time 55191091 ps
CPU time 1.09 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 210072 kb
Host smart-39836b0b-8ce9-493f-9c63-1faae00f84e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807817002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3807817002
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1580251061
Short name T922
Test name
Test status
Simulation time 22042489 ps
CPU time 1.39 seconds
Started Apr 21 12:49:06 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 219248 kb
Host smart-13666f41-de59-46ef-a16c-02802ee2ab24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580251061 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1580251061
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1045996366
Short name T966
Test name
Test status
Simulation time 19481702 ps
CPU time 0.99 seconds
Started Apr 21 12:48:53 PM PDT 24
Finished Apr 21 12:48:55 PM PDT 24
Peak memory 209584 kb
Host smart-ec960659-a10d-4e52-b085-b0f328ae44dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045996366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1045996366
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1805079788
Short name T876
Test name
Test status
Simulation time 54678723 ps
CPU time 1.94 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 209440 kb
Host smart-b22fee79-6df3-4939-a802-c34a5ff6fd2d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805079788 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1805079788
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1698084120
Short name T947
Test name
Test status
Simulation time 470847348 ps
CPU time 10.14 seconds
Started Apr 21 12:49:05 PM PDT 24
Finished Apr 21 12:49:16 PM PDT 24
Peak memory 209316 kb
Host smart-7d286a14-6179-45a6-83c0-bcdb25d7c514
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698084120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1698084120
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3316401006
Short name T896
Test name
Test status
Simulation time 1283838342 ps
CPU time 6.31 seconds
Started Apr 21 12:49:06 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 209096 kb
Host smart-472ce6a8-da99-439f-b5a0-39dbbb17e13e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316401006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3316401006
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4280750321
Short name T993
Test name
Test status
Simulation time 399199994 ps
CPU time 5.23 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:16 PM PDT 24
Peak memory 211168 kb
Host smart-0a90b7c6-eacb-4c68-8af7-1cee1f197895
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280750321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4280750321
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4205387637
Short name T979
Test name
Test status
Simulation time 257338219 ps
CPU time 2.33 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 217732 kb
Host smart-bb265af7-fb3a-476a-9f06-d1a99aad2bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420538
7637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4205387637
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.804130541
Short name T866
Test name
Test status
Simulation time 33279238 ps
CPU time 1.09 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 209520 kb
Host smart-aa86bb56-eed3-4a6f-898e-caad07496fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804130541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.804130541
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.921937386
Short name T923
Test name
Test status
Simulation time 176526204 ps
CPU time 1.19 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:11 PM PDT 24
Peak memory 209664 kb
Host smart-2cf53d52-3c5d-4585-a78d-7211f585269b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921937386 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.921937386
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2946050971
Short name T202
Test name
Test status
Simulation time 53726658 ps
CPU time 1.02 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 209492 kb
Host smart-51b607dd-879b-4992-8cae-13a71e113325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946050971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2946050971
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3028300809
Short name T955
Test name
Test status
Simulation time 186885488 ps
CPU time 3.86 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 217752 kb
Host smart-8c0914c5-a395-4c97-9950-8e30743dd438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028300809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3028300809
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.802138401
Short name T928
Test name
Test status
Simulation time 46939014 ps
CPU time 1.94 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 217808 kb
Host smart-00d776c5-cdce-46cf-b893-2707faec3e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802138401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.802138401
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2973283842
Short name T910
Test name
Test status
Simulation time 171248138 ps
CPU time 1.63 seconds
Started Apr 21 12:49:06 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 209508 kb
Host smart-d005bce6-b5c1-4a10-9da7-61ac4d2bdcc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973283842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2973283842
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3889828040
Short name T198
Test name
Test status
Simulation time 75606479 ps
CPU time 1.16 seconds
Started Apr 21 12:49:05 PM PDT 24
Finished Apr 21 12:49:07 PM PDT 24
Peak memory 218436 kb
Host smart-3eb2864b-2d52-489d-a5ee-b45fcfd38da0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889828040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3889828040
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.534792761
Short name T970
Test name
Test status
Simulation time 42279356 ps
CPU time 1.56 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 219120 kb
Host smart-3e9623da-8ef9-4752-8ddd-638ab61a47a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534792761 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.534792761
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.704589675
Short name T883
Test name
Test status
Simulation time 21650157 ps
CPU time 0.85 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 209532 kb
Host smart-9e0e3ea1-f81c-4c12-ba21-54d98dcce4ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704589675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.704589675
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3517850374
Short name T936
Test name
Test status
Simulation time 139005462 ps
CPU time 1 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 208044 kb
Host smart-26e60ecb-1b08-4593-99bf-497e64664908
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517850374 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3517850374
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2541368948
Short name T907
Test name
Test status
Simulation time 783631590 ps
CPU time 8.46 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 209196 kb
Host smart-4a396f02-75c9-4d1a-b652-2ee398b3e135
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541368948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2541368948
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2715130816
Short name T921
Test name
Test status
Simulation time 1075931843 ps
CPU time 10.66 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:26 PM PDT 24
Peak memory 209152 kb
Host smart-0faae0b4-03b4-4d4f-bc99-f00acd3a40e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715130816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2715130816
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4241886091
Short name T154
Test name
Test status
Simulation time 78994002 ps
CPU time 2.75 seconds
Started Apr 21 12:48:58 PM PDT 24
Finished Apr 21 12:49:01 PM PDT 24
Peak memory 211056 kb
Host smart-1b689876-54c9-40dd-99d1-5f6fa5b5f653
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241886091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.4241886091
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2192110207
Short name T139
Test name
Test status
Simulation time 497604318 ps
CPU time 2.26 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 217848 kb
Host smart-eacafea6-f421-4efd-8264-3eeffde6bca1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219211
0207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2192110207
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2528168054
Short name T864
Test name
Test status
Simulation time 144233364 ps
CPU time 3.72 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 209592 kb
Host smart-a323088f-c0e8-46e5-b73d-701960531a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528168054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2528168054
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2579565251
Short name T909
Test name
Test status
Simulation time 50777181 ps
CPU time 2.25 seconds
Started Apr 21 12:49:00 PM PDT 24
Finished Apr 21 12:49:03 PM PDT 24
Peak memory 211636 kb
Host smart-29446ed9-b8fd-4801-9654-d6541af674c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579565251 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2579565251
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1352320221
Short name T934
Test name
Test status
Simulation time 43475723 ps
CPU time 1.37 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 209492 kb
Host smart-7f594635-ff0e-4fca-be10-b187e4f93c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352320221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1352320221
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.640969391
Short name T968
Test name
Test status
Simulation time 128991886 ps
CPU time 5.12 seconds
Started Apr 21 12:49:03 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 217912 kb
Host smart-b53d38e8-2965-4062-8528-598341902628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640969391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.640969391
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1373507543
Short name T134
Test name
Test status
Simulation time 132738911 ps
CPU time 2.75 seconds
Started Apr 21 12:49:05 PM PDT 24
Finished Apr 21 12:49:08 PM PDT 24
Peak memory 217712 kb
Host smart-82422b63-4538-4686-aa5f-e00b50859e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373507543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1373507543
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4219272718
Short name T971
Test name
Test status
Simulation time 24062188 ps
CPU time 0.94 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 209492 kb
Host smart-1726af09-d998-4e8d-97ba-0cec72d93e0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219272718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4219272718
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1737427739
Short name T945
Test name
Test status
Simulation time 196289754 ps
CPU time 1.43 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:07 PM PDT 24
Peak memory 209416 kb
Host smart-9f13f3a2-8a50-4bde-97da-ed037ff908c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737427739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1737427739
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3829136769
Short name T191
Test name
Test status
Simulation time 13594445 ps
CPU time 1.13 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:11 PM PDT 24
Peak memory 218228 kb
Host smart-18c0cef9-5f06-4bf4-a4df-0fb88268d40c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829136769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3829136769
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3475955889
Short name T978
Test name
Test status
Simulation time 69933097 ps
CPU time 1.43 seconds
Started Apr 21 12:49:13 PM PDT 24
Finished Apr 21 12:49:15 PM PDT 24
Peak memory 219840 kb
Host smart-9edc2273-59fa-4567-95cb-ff9ce441b579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475955889 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3475955889
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2467330023
Short name T997
Test name
Test status
Simulation time 14992949 ps
CPU time 0.85 seconds
Started Apr 21 12:49:06 PM PDT 24
Finished Apr 21 12:49:07 PM PDT 24
Peak memory 209476 kb
Host smart-2ba4ac3b-fa5d-4250-b546-7912902cff95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467330023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2467330023
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1706261684
Short name T871
Test name
Test status
Simulation time 30488191 ps
CPU time 0.87 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:04 PM PDT 24
Peak memory 208192 kb
Host smart-9f9ee9e3-a119-4122-ac2a-98b8cc3e3fed
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706261684 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1706261684
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.136789430
Short name T153
Test name
Test status
Simulation time 502778907 ps
CPU time 5.5 seconds
Started Apr 21 12:49:15 PM PDT 24
Finished Apr 21 12:49:21 PM PDT 24
Peak memory 209304 kb
Host smart-7912dfad-6829-4c52-8893-6768b3c8a1fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136789430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.136789430
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3916991299
Short name T865
Test name
Test status
Simulation time 341734723 ps
CPU time 4.04 seconds
Started Apr 21 12:48:58 PM PDT 24
Finished Apr 21 12:49:02 PM PDT 24
Peak memory 209272 kb
Host smart-c16d4bc5-c423-48c9-b22c-f9d5dbb44d51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916991299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3916991299
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3024105072
Short name T911
Test name
Test status
Simulation time 776879972 ps
CPU time 2.96 seconds
Started Apr 21 12:49:05 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 211200 kb
Host smart-8ea1f4f5-984a-47bf-a5f7-8b5a8c842b01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024105072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3024105072
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1735434552
Short name T917
Test name
Test status
Simulation time 43670125 ps
CPU time 1.92 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:07 PM PDT 24
Peak memory 209512 kb
Host smart-ec6a6fb2-4110-40aa-8674-a2c263d5623c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735434552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1735434552
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2813036144
Short name T905
Test name
Test status
Simulation time 29108202 ps
CPU time 1.43 seconds
Started Apr 21 12:49:05 PM PDT 24
Finished Apr 21 12:49:07 PM PDT 24
Peak memory 209488 kb
Host smart-3806e9b6-5c70-4445-bf25-af2e2cd0b5c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813036144 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2813036144
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.420601412
Short name T915
Test name
Test status
Simulation time 23448904 ps
CPU time 1.13 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 209668 kb
Host smart-509c5ef5-322b-4f44-9fa9-4557ded27065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420601412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.420601412
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3286582414
Short name T994
Test name
Test status
Simulation time 35486083 ps
CPU time 1.9 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 217936 kb
Host smart-6c9543df-650e-4cb8-9216-0583f12cbab4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286582414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3286582414
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1844636200
Short name T146
Test name
Test status
Simulation time 77084767 ps
CPU time 2 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 221488 kb
Host smart-f367d03b-0576-4f8c-b3ef-c3adfc23c7d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844636200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1844636200
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4047958150
Short name T953
Test name
Test status
Simulation time 54966745 ps
CPU time 1.35 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 219688 kb
Host smart-daf29d92-b48c-4a9d-a20e-2b36da84990e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047958150 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4047958150
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.23004666
Short name T194
Test name
Test status
Simulation time 20425286 ps
CPU time 0.93 seconds
Started Apr 21 12:49:17 PM PDT 24
Finished Apr 21 12:49:19 PM PDT 24
Peak memory 209136 kb
Host smart-608b3921-37d9-493c-aab6-4675a2821382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23004666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.23004666
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.375552365
Short name T882
Test name
Test status
Simulation time 227323717 ps
CPU time 1.64 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 209480 kb
Host smart-6c76c770-cedf-4712-bc62-57467c1fdaed
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375552365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.375552365
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2549292766
Short name T927
Test name
Test status
Simulation time 360849147 ps
CPU time 4.73 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 209328 kb
Host smart-42fa4771-6fa4-4eff-b724-29970377ccd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549292766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2549292766
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2786414867
Short name T920
Test name
Test status
Simulation time 3749805311 ps
CPU time 21 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:26 PM PDT 24
Peak memory 208800 kb
Host smart-d38414b9-0fcf-4c7b-90d3-e80b2cfab87a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786414867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2786414867
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1329120988
Short name T952
Test name
Test status
Simulation time 506697217 ps
CPU time 2.2 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:07 PM PDT 24
Peak memory 210976 kb
Host smart-52ee4490-c203-48d1-a8a2-975f7bfd3713
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329120988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1329120988
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1833976108
Short name T155
Test name
Test status
Simulation time 215858634 ps
CPU time 1.5 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 219516 kb
Host smart-65cd16a5-5b8b-42b0-a9c2-e94a04e95461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183397
6108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1833976108
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3728272359
Short name T988
Test name
Test status
Simulation time 167069528 ps
CPU time 1.6 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 209520 kb
Host smart-f1df705b-c1c4-4208-997e-a19023fe417e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728272359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3728272359
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2088249997
Short name T975
Test name
Test status
Simulation time 28716483 ps
CPU time 1.03 seconds
Started Apr 21 12:49:20 PM PDT 24
Finished Apr 21 12:49:21 PM PDT 24
Peak memory 209688 kb
Host smart-63a6a5df-40f0-4dca-8ef7-afdc4eb1dc6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088249997 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2088249997
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2086538541
Short name T162
Test name
Test status
Simulation time 27829295 ps
CPU time 1.11 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:23 PM PDT 24
Peak memory 209544 kb
Host smart-e26ecfca-2bdc-4dd1-9db9-dbfa5458ab9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086538541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2086538541
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3008910001
Short name T946
Test name
Test status
Simulation time 352596076 ps
CPU time 1.93 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 217932 kb
Host smart-f18ee5da-4164-40ca-b831-11c2178f77b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008910001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3008910001
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2107651546
Short name T872
Test name
Test status
Simulation time 61589853 ps
CPU time 2.04 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 12:49:29 PM PDT 24
Peak memory 222188 kb
Host smart-440e6dee-3ab1-4af0-affd-e49af5bf76f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107651546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2107651546
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1586454463
Short name T141
Test name
Test status
Simulation time 49058295 ps
CPU time 1.58 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 217932 kb
Host smart-641c1343-e0f6-4a95-ac53-98ebac8c4bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586454463 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1586454463
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3998971980
Short name T964
Test name
Test status
Simulation time 30815630 ps
CPU time 0.88 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 209560 kb
Host smart-000c92ac-f267-42e8-a795-601889046335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998971980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3998971980
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4171724076
Short name T996
Test name
Test status
Simulation time 351361857 ps
CPU time 2.15 seconds
Started Apr 21 12:49:16 PM PDT 24
Finished Apr 21 12:49:18 PM PDT 24
Peak memory 209476 kb
Host smart-9981680e-12e7-4228-87b5-68ca76ab3d28
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171724076 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.4171724076
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2438355774
Short name T967
Test name
Test status
Simulation time 1942245798 ps
CPU time 11.03 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:22 PM PDT 24
Peak memory 208608 kb
Host smart-a5e00fce-bb5d-48db-a45a-ab5dd31c77e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438355774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2438355774
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2228466414
Short name T903
Test name
Test status
Simulation time 2138831071 ps
CPU time 12.84 seconds
Started Apr 21 12:49:02 PM PDT 24
Finished Apr 21 12:49:15 PM PDT 24
Peak memory 208328 kb
Host smart-e4e6eb04-a98d-4763-822d-1b1c5b7eae8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228466414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2228466414
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3670019835
Short name T885
Test name
Test status
Simulation time 327349995 ps
CPU time 1.86 seconds
Started Apr 21 12:49:16 PM PDT 24
Finished Apr 21 12:49:18 PM PDT 24
Peak memory 211100 kb
Host smart-334de8d2-5255-4f29-b786-55460073ec3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670019835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3670019835
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1400359901
Short name T870
Test name
Test status
Simulation time 351698512 ps
CPU time 2.07 seconds
Started Apr 21 12:49:17 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 218976 kb
Host smart-a8408af7-2359-4930-b79e-b41cb17699bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140035
9901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1400359901
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2497534021
Short name T880
Test name
Test status
Simulation time 150655682 ps
CPU time 1.36 seconds
Started Apr 21 12:49:18 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 209492 kb
Host smart-ce8ace6a-696e-44b7-893c-81fb45599526
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497534021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2497534021
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2394664389
Short name T206
Test name
Test status
Simulation time 538122566 ps
CPU time 1.5 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 211656 kb
Host smart-1dd6f1d2-cd5a-4e19-a5fb-51af58384f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394664389 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2394664389
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1721253549
Short name T902
Test name
Test status
Simulation time 193967158 ps
CPU time 1.24 seconds
Started Apr 21 12:49:10 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 209676 kb
Host smart-35d2641c-293b-4403-b985-a63122abf305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721253549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1721253549
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2453870352
Short name T135
Test name
Test status
Simulation time 34470130 ps
CPU time 1.84 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 224120 kb
Host smart-06ae1822-5042-4696-88ea-d19d37c1775d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453870352 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2453870352
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1612051719
Short name T959
Test name
Test status
Simulation time 12697931 ps
CPU time 0.92 seconds
Started Apr 21 12:49:24 PM PDT 24
Finished Apr 21 12:49:25 PM PDT 24
Peak memory 209552 kb
Host smart-2bd14c47-cb67-44a5-b083-4cccab75cad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612051719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1612051719
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3615563483
Short name T986
Test name
Test status
Simulation time 69752817 ps
CPU time 0.87 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 207976 kb
Host smart-c0a3a300-f11d-4103-8b25-fd565770e892
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615563483 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3615563483
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1729071139
Short name T888
Test name
Test status
Simulation time 1211632217 ps
CPU time 14.39 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:23 PM PDT 24
Peak memory 209492 kb
Host smart-e912334c-159e-44f3-892c-9ad71170eb38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729071139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1729071139
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2336587532
Short name T867
Test name
Test status
Simulation time 5528223070 ps
CPU time 15.08 seconds
Started Apr 21 12:49:14 PM PDT 24
Finished Apr 21 12:49:30 PM PDT 24
Peak memory 209508 kb
Host smart-579e9043-8a82-4f49-8403-b107ed6c8dfb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336587532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2336587532
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.889109578
Short name T930
Test name
Test status
Simulation time 210851669 ps
CPU time 2.92 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 210984 kb
Host smart-72b07d27-d8ac-438e-b114-3985a17c8aa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889109578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.889109578
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3178848816
Short name T931
Test name
Test status
Simulation time 427746714 ps
CPU time 2.21 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 218052 kb
Host smart-fc2efb95-1b9d-429b-ae98-2b6dae23ac88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317884
8816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3178848816
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3084754414
Short name T992
Test name
Test status
Simulation time 657790813 ps
CPU time 2.21 seconds
Started Apr 21 12:49:20 PM PDT 24
Finished Apr 21 12:49:22 PM PDT 24
Peak memory 209532 kb
Host smart-7c292fb6-a1e8-4efc-88e7-9a9cf830d27f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084754414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3084754414
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1095850015
Short name T958
Test name
Test status
Simulation time 16647121 ps
CPU time 1 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:11 PM PDT 24
Peak memory 209548 kb
Host smart-9be42dc0-79a0-462b-b66c-b6db9b2ff0e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095850015 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1095850015
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.805567747
Short name T204
Test name
Test status
Simulation time 90807968 ps
CPU time 1.05 seconds
Started Apr 21 12:49:08 PM PDT 24
Finished Apr 21 12:49:10 PM PDT 24
Peak memory 209520 kb
Host smart-1a34e141-b7be-475e-a854-173505045952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805567747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.805567747
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.527052075
Short name T138
Test name
Test status
Simulation time 108918562 ps
CPU time 2.68 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 217856 kb
Host smart-dbaad5dd-385c-4ace-a256-91dfb2d80495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527052075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.527052075
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2593340533
Short name T147
Test name
Test status
Simulation time 480857364 ps
CPU time 4.74 seconds
Started Apr 21 12:49:17 PM PDT 24
Finished Apr 21 12:49:23 PM PDT 24
Peak memory 217760 kb
Host smart-31823031-5c65-48c1-b4b6-502b26f46da8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593340533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2593340533
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3635274590
Short name T126
Test name
Test status
Simulation time 76077210 ps
CPU time 1.35 seconds
Started Apr 21 12:49:13 PM PDT 24
Finished Apr 21 12:49:15 PM PDT 24
Peak memory 218992 kb
Host smart-49ae7e6c-2cfe-4d60-88b5-b6b4ec361ee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635274590 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3635274590
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2309941287
Short name T200
Test name
Test status
Simulation time 13369902 ps
CPU time 1.08 seconds
Started Apr 21 12:49:20 PM PDT 24
Finished Apr 21 12:49:22 PM PDT 24
Peak memory 209596 kb
Host smart-e30a3f1b-129c-4310-a940-3cbc3a11abb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309941287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2309941287
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1981996581
Short name T950
Test name
Test status
Simulation time 58967367 ps
CPU time 1.11 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 209496 kb
Host smart-ca26dd5d-9cfe-4a63-af02-c271b8875d4e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981996581 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1981996581
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1788358047
Short name T951
Test name
Test status
Simulation time 862293064 ps
CPU time 10.65 seconds
Started Apr 21 12:49:05 PM PDT 24
Finished Apr 21 12:49:16 PM PDT 24
Peak memory 209300 kb
Host smart-75d703e8-be89-4fad-8ae5-d2672147bfe1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788358047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1788358047
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2220934087
Short name T886
Test name
Test status
Simulation time 1343652260 ps
CPU time 9.51 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 208624 kb
Host smart-73ef44d8-b785-485a-abfb-112c38e293c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220934087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2220934087
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2225481990
Short name T974
Test name
Test status
Simulation time 167405857 ps
CPU time 1.57 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 210860 kb
Host smart-6b6d45ee-c4e3-40bd-95d1-5c9b16856117
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225481990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2225481990
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.966754182
Short name T874
Test name
Test status
Simulation time 135941231 ps
CPU time 1.41 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 217896 kb
Host smart-62d9c9a8-c54b-4c87-b793-48f7bbce2bf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966754
182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.966754182
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1116064758
Short name T933
Test name
Test status
Simulation time 1252809753 ps
CPU time 2.29 seconds
Started Apr 21 12:49:18 PM PDT 24
Finished Apr 21 12:49:21 PM PDT 24
Peak memory 209456 kb
Host smart-5cdd158e-13c8-44d8-b711-b6d2d5539dd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116064758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1116064758
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2855096336
Short name T926
Test name
Test status
Simulation time 26017156 ps
CPU time 1.03 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 209500 kb
Host smart-7928fcba-9974-41b7-8ae6-0b25bb50a1ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855096336 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2855096336
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2987484910
Short name T965
Test name
Test status
Simulation time 21563142 ps
CPU time 1.44 seconds
Started Apr 21 12:49:19 PM PDT 24
Finished Apr 21 12:49:21 PM PDT 24
Peak memory 211608 kb
Host smart-1017a1b2-97d2-4544-a417-a294e0a81c9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987484910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2987484910
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.264594443
Short name T939
Test name
Test status
Simulation time 33791999 ps
CPU time 2.51 seconds
Started Apr 21 12:49:11 PM PDT 24
Finished Apr 21 12:49:15 PM PDT 24
Peak memory 217936 kb
Host smart-ceafb3f0-6dfc-413e-8f22-fdccfa6b2ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264594443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.264594443
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3477959096
Short name T906
Test name
Test status
Simulation time 33854800 ps
CPU time 1.97 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 218908 kb
Host smart-06fa2700-2539-49f9-bbaf-48c27be3fab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477959096 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3477959096
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.846350548
Short name T983
Test name
Test status
Simulation time 52317736 ps
CPU time 0.84 seconds
Started Apr 21 12:49:35 PM PDT 24
Finished Apr 21 12:49:37 PM PDT 24
Peak memory 209520 kb
Host smart-99c43f0d-2959-4071-b665-4da5edcc43cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846350548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.846350548
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1879578704
Short name T893
Test name
Test status
Simulation time 140948453 ps
CPU time 1.35 seconds
Started Apr 21 12:49:12 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 209460 kb
Host smart-19b09228-2c19-4646-8690-936527795140
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879578704 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1879578704
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2674174604
Short name T957
Test name
Test status
Simulation time 185574410 ps
CPU time 5.48 seconds
Started Apr 21 12:49:32 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 209312 kb
Host smart-9417ebe0-8434-4465-ad44-7ff4651ffdb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674174604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2674174604
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.890345298
Short name T875
Test name
Test status
Simulation time 2990360243 ps
CPU time 18.1 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:49:45 PM PDT 24
Peak memory 209548 kb
Host smart-5039fbcf-9ab0-41a2-b995-f8fef2e95394
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890345298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.890345298
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2732824678
Short name T972
Test name
Test status
Simulation time 280698593 ps
CPU time 1.48 seconds
Started Apr 21 12:49:46 PM PDT 24
Finished Apr 21 12:49:48 PM PDT 24
Peak memory 210808 kb
Host smart-ecfa7234-1d65-4822-acbb-8e64c30a9fc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732824678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2732824678
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1767298702
Short name T900
Test name
Test status
Simulation time 362270443 ps
CPU time 1.8 seconds
Started Apr 21 12:49:09 PM PDT 24
Finished Apr 21 12:49:12 PM PDT 24
Peak memory 219208 kb
Host smart-ab44128a-53ce-4ffe-8124-c99d44c26f4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176729
8702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1767298702
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1625271132
Short name T868
Test name
Test status
Simulation time 438395053 ps
CPU time 1.33 seconds
Started Apr 21 12:49:04 PM PDT 24
Finished Apr 21 12:49:06 PM PDT 24
Peak memory 209636 kb
Host smart-4f97b38f-98d5-408c-a948-fae46bfd0112
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625271132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1625271132
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1339892390
Short name T963
Test name
Test status
Simulation time 44459811 ps
CPU time 1.94 seconds
Started Apr 21 12:49:20 PM PDT 24
Finished Apr 21 12:49:23 PM PDT 24
Peak memory 209568 kb
Host smart-1a5ac950-6d3b-4720-a456-b6c2f41d5f94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339892390 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1339892390
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3387169721
Short name T987
Test name
Test status
Simulation time 43951381 ps
CPU time 1.49 seconds
Started Apr 21 12:49:07 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 211396 kb
Host smart-8bac9bfc-b9ea-41f0-8870-03a2145a5277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387169721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3387169721
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1199048215
Short name T914
Test name
Test status
Simulation time 125113993 ps
CPU time 2.9 seconds
Started Apr 21 12:49:41 PM PDT 24
Finished Apr 21 12:49:44 PM PDT 24
Peak memory 219840 kb
Host smart-36ac1d1d-82ce-48b4-9269-cda07b02bba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199048215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1199048215
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3608844872
Short name T629
Test name
Test status
Simulation time 213418067 ps
CPU time 0.89 seconds
Started Apr 21 01:29:57 PM PDT 24
Finished Apr 21 01:29:58 PM PDT 24
Peak memory 209424 kb
Host smart-b5630b4d-5f47-45cd-8a0d-b7da4623bdbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608844872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3608844872
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1951336986
Short name T576
Test name
Test status
Simulation time 364412442 ps
CPU time 9.59 seconds
Started Apr 21 01:29:48 PM PDT 24
Finished Apr 21 01:29:58 PM PDT 24
Peak memory 217668 kb
Host smart-3bbf4a2d-b21d-4851-9c2e-4e63c17ce670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951336986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1951336986
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1408363366
Short name T554
Test name
Test status
Simulation time 1776194153 ps
CPU time 4.48 seconds
Started Apr 21 01:29:49 PM PDT 24
Finished Apr 21 01:29:53 PM PDT 24
Peak memory 217004 kb
Host smart-7263861a-d5b6-4a81-a61b-aea9e0970135
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408363366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1408363366
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3017048870
Short name T53
Test name
Test status
Simulation time 13990373900 ps
CPU time 50.56 seconds
Started Apr 21 01:29:52 PM PDT 24
Finished Apr 21 01:30:43 PM PDT 24
Peak memory 219432 kb
Host smart-2a1c9295-3099-4f56-8e1b-20498ee291e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017048870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3017048870
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.643778090
Short name T818
Test name
Test status
Simulation time 856551247 ps
CPU time 2.41 seconds
Started Apr 21 01:29:56 PM PDT 24
Finished Apr 21 01:29:59 PM PDT 24
Peak memory 216968 kb
Host smart-889ff55f-52d5-4d97-9ce5-0579454f8aac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643778090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.643778090
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3056872471
Short name T674
Test name
Test status
Simulation time 309439551 ps
CPU time 5 seconds
Started Apr 21 01:29:49 PM PDT 24
Finished Apr 21 01:29:55 PM PDT 24
Peak memory 217788 kb
Host smart-5894fefc-740b-4f19-9f37-d4ae317c9772
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056872471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3056872471
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4274509469
Short name T341
Test name
Test status
Simulation time 2625170243 ps
CPU time 10.6 seconds
Started Apr 21 01:29:53 PM PDT 24
Finished Apr 21 01:30:04 PM PDT 24
Peak memory 213172 kb
Host smart-45cdd525-aae7-4353-94cc-2b87acfa4970
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274509469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.4274509469
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1011380457
Short name T88
Test name
Test status
Simulation time 117427165 ps
CPU time 2.45 seconds
Started Apr 21 01:29:50 PM PDT 24
Finished Apr 21 01:29:53 PM PDT 24
Peak memory 212936 kb
Host smart-c3435225-67cb-4ab5-8dca-63330ead896f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011380457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1011380457
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1726337331
Short name T676
Test name
Test status
Simulation time 1100009251 ps
CPU time 50.63 seconds
Started Apr 21 01:29:50 PM PDT 24
Finished Apr 21 01:30:41 PM PDT 24
Peak memory 251568 kb
Host smart-ef95ea8a-d427-44d0-877f-f569e2a50938
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726337331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1726337331
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.719672491
Short name T662
Test name
Test status
Simulation time 687653046 ps
CPU time 14.9 seconds
Started Apr 21 01:29:51 PM PDT 24
Finished Apr 21 01:30:06 PM PDT 24
Peak memory 250780 kb
Host smart-46d0163c-dd85-480b-a005-a4687c5bfd0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719672491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.719672491
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1843545661
Short name T649
Test name
Test status
Simulation time 251675166 ps
CPU time 1.88 seconds
Started Apr 21 01:29:46 PM PDT 24
Finished Apr 21 01:29:48 PM PDT 24
Peak memory 217904 kb
Host smart-0c7be3f6-6a3b-4ed3-be57-dcb5ffd66b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843545661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1843545661
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1177110308
Short name T853
Test name
Test status
Simulation time 652839869 ps
CPU time 21.7 seconds
Started Apr 21 01:29:48 PM PDT 24
Finished Apr 21 01:30:10 PM PDT 24
Peak memory 217840 kb
Host smart-007ba40b-6b11-49eb-ac22-25bf6d58baf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177110308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1177110308
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2600332865
Short name T113
Test name
Test status
Simulation time 1059704495 ps
CPU time 39.2 seconds
Started Apr 21 01:29:58 PM PDT 24
Finished Apr 21 01:30:37 PM PDT 24
Peak memory 270748 kb
Host smart-0e2a9b69-a49f-4ae5-af11-177cd8ff7088
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600332865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2600332865
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1776654686
Short name T353
Test name
Test status
Simulation time 1447330215 ps
CPU time 14.15 seconds
Started Apr 21 01:29:55 PM PDT 24
Finished Apr 21 01:30:09 PM PDT 24
Peak memory 225964 kb
Host smart-a281a71e-a510-463a-b92b-f7717180d63a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776654686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1776654686
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.248728125
Short name T815
Test name
Test status
Simulation time 735566438 ps
CPU time 6.73 seconds
Started Apr 21 01:29:55 PM PDT 24
Finished Apr 21 01:30:02 PM PDT 24
Peak memory 217876 kb
Host smart-139c1b50-969c-4da7-b58c-d64e2006a2b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248728125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.248728125
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1157508608
Short name T340
Test name
Test status
Simulation time 1740097602 ps
CPU time 8.27 seconds
Started Apr 21 01:30:00 PM PDT 24
Finished Apr 21 01:30:08 PM PDT 24
Peak memory 217928 kb
Host smart-f65af6cd-c331-46cc-9e72-76a7724db726
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157508608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
157508608
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3397592369
Short name T245
Test name
Test status
Simulation time 2967731909 ps
CPU time 10.13 seconds
Started Apr 21 01:29:48 PM PDT 24
Finished Apr 21 01:29:58 PM PDT 24
Peak memory 225488 kb
Host smart-201c4f11-6b67-41fe-a261-3757b68ff921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397592369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3397592369
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1550609324
Short name T611
Test name
Test status
Simulation time 136714354 ps
CPU time 2.45 seconds
Started Apr 21 01:29:44 PM PDT 24
Finished Apr 21 01:29:47 PM PDT 24
Peak memory 214052 kb
Host smart-fabbee1a-821b-411e-b3fd-1c62f89e6077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550609324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1550609324
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2061611077
Short name T426
Test name
Test status
Simulation time 2814461704 ps
CPU time 33.5 seconds
Started Apr 21 01:29:43 PM PDT 24
Finished Apr 21 01:30:17 PM PDT 24
Peak memory 248776 kb
Host smart-78cdbd7e-f5be-4471-b23d-b282cf62b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061611077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2061611077
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1621078783
Short name T81
Test name
Test status
Simulation time 24947637 ps
CPU time 0.94 seconds
Started Apr 21 01:29:44 PM PDT 24
Finished Apr 21 01:29:45 PM PDT 24
Peak memory 212544 kb
Host smart-848aabcd-844c-4670-bcf0-ef7f3b296ca6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621078783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1621078783
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3098369236
Short name T325
Test name
Test status
Simulation time 104605023 ps
CPU time 1.2 seconds
Started Apr 21 01:30:05 PM PDT 24
Finished Apr 21 01:30:07 PM PDT 24
Peak memory 209388 kb
Host smart-98781eee-6254-4b7f-af24-6a1c8babc2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098369236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3098369236
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1882526377
Short name T103
Test name
Test status
Simulation time 437552946 ps
CPU time 14.11 seconds
Started Apr 21 01:29:58 PM PDT 24
Finished Apr 21 01:30:13 PM PDT 24
Peak memory 217876 kb
Host smart-5e665de6-9d61-4de9-9857-b267b7d99100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882526377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1882526377
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2697920803
Short name T704
Test name
Test status
Simulation time 772184162 ps
CPU time 3.68 seconds
Started Apr 21 01:30:03 PM PDT 24
Finished Apr 21 01:30:06 PM PDT 24
Peak memory 216716 kb
Host smart-95b71b05-0ca1-402b-b155-a3c912063200
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697920803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2697920803
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.4124450319
Short name T299
Test name
Test status
Simulation time 1719737034 ps
CPU time 46.9 seconds
Started Apr 21 01:30:03 PM PDT 24
Finished Apr 21 01:30:50 PM PDT 24
Peak memory 217692 kb
Host smart-a43be44d-46bc-4602-8c18-3f747ba359f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124450319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.4124450319
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2080485538
Short name T104
Test name
Test status
Simulation time 1518379851 ps
CPU time 34.62 seconds
Started Apr 21 01:30:05 PM PDT 24
Finished Apr 21 01:30:40 PM PDT 24
Peak memory 216856 kb
Host smart-8f5dd988-e1ae-4f2f-aa4a-b6849faad595
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080485538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
080485538
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.985796366
Short name T472
Test name
Test status
Simulation time 1779560395 ps
CPU time 11.8 seconds
Started Apr 21 01:30:02 PM PDT 24
Finished Apr 21 01:30:14 PM PDT 24
Peak memory 217804 kb
Host smart-5ddfc3ae-e7a0-4b20-b157-fcc2acd333aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985796366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.985796366
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2106986639
Short name T451
Test name
Test status
Simulation time 788808948 ps
CPU time 13.35 seconds
Started Apr 21 01:30:02 PM PDT 24
Finished Apr 21 01:30:16 PM PDT 24
Peak memory 213088 kb
Host smart-f989cd60-5ec7-4f2c-be27-42f6a60e288b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106986639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2106986639
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.4034844083
Short name T454
Test name
Test status
Simulation time 1344917093 ps
CPU time 4.9 seconds
Started Apr 21 01:30:01 PM PDT 24
Finished Apr 21 01:30:06 PM PDT 24
Peak memory 213244 kb
Host smart-78e09ef2-8c31-4ff2-9f4b-23cf3c136a5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034844083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
4034844083
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3829695371
Short name T284
Test name
Test status
Simulation time 7036997582 ps
CPU time 69.07 seconds
Started Apr 21 01:30:00 PM PDT 24
Finished Apr 21 01:31:09 PM PDT 24
Peak memory 274760 kb
Host smart-a99f091a-6a14-46a1-b53e-d3b13bfd858e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829695371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3829695371
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1501365757
Short name T286
Test name
Test status
Simulation time 1248135777 ps
CPU time 13.77 seconds
Started Apr 21 01:30:02 PM PDT 24
Finished Apr 21 01:30:16 PM PDT 24
Peak memory 250744 kb
Host smart-d14a1579-ec04-49ec-bf00-288a51720ccb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501365757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1501365757
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2626716603
Short name T389
Test name
Test status
Simulation time 184964769 ps
CPU time 2.26 seconds
Started Apr 21 01:29:56 PM PDT 24
Finished Apr 21 01:29:58 PM PDT 24
Peak memory 217980 kb
Host smart-5b488d78-2a90-4147-9578-083fcff47e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626716603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2626716603
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2911155491
Short name T644
Test name
Test status
Simulation time 262151688 ps
CPU time 5.72 seconds
Started Apr 21 01:30:02 PM PDT 24
Finished Apr 21 01:30:08 PM PDT 24
Peak memory 213968 kb
Host smart-15676979-78cc-4144-83c8-4c6520c92edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911155491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2911155491
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3792975125
Short name T256
Test name
Test status
Simulation time 415361076 ps
CPU time 10.83 seconds
Started Apr 21 01:30:08 PM PDT 24
Finished Apr 21 01:30:19 PM PDT 24
Peak memory 225968 kb
Host smart-d3165823-1632-4166-a68b-f2aaa94d3c2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792975125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3792975125
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3651855025
Short name T403
Test name
Test status
Simulation time 877201164 ps
CPU time 11.51 seconds
Started Apr 21 01:30:06 PM PDT 24
Finished Apr 21 01:30:18 PM PDT 24
Peak memory 217884 kb
Host smart-85be3aa1-6271-446c-9b7e-ef9339905deb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651855025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3651855025
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3160321397
Short name T360
Test name
Test status
Simulation time 1436551421 ps
CPU time 12.65 seconds
Started Apr 21 01:30:00 PM PDT 24
Finished Apr 21 01:30:13 PM PDT 24
Peak memory 225988 kb
Host smart-2069caff-ddca-4dd0-b9a7-adc1ab0d8eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160321397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3160321397
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2879697194
Short name T819
Test name
Test status
Simulation time 171973882 ps
CPU time 2.48 seconds
Started Apr 21 01:29:57 PM PDT 24
Finished Apr 21 01:29:59 PM PDT 24
Peak memory 213868 kb
Host smart-afd07174-801f-4dc4-8a8b-983c4d2efb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879697194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2879697194
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3338026952
Short name T659
Test name
Test status
Simulation time 473625187 ps
CPU time 21.23 seconds
Started Apr 21 01:29:57 PM PDT 24
Finished Apr 21 01:30:19 PM PDT 24
Peak memory 248140 kb
Host smart-2b90968f-902f-4af2-ba3c-550ba72d7ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338026952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3338026952
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2601174810
Short name T57
Test name
Test status
Simulation time 535247044 ps
CPU time 3.4 seconds
Started Apr 21 01:29:59 PM PDT 24
Finished Apr 21 01:30:02 PM PDT 24
Peak memory 226280 kb
Host smart-c7dc1c70-c462-4249-a50e-e4f8b45d104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601174810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2601174810
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2958318890
Short name T781
Test name
Test status
Simulation time 14016600924 ps
CPU time 71.69 seconds
Started Apr 21 01:30:05 PM PDT 24
Finished Apr 21 01:31:17 PM PDT 24
Peak memory 276484 kb
Host smart-c6f10148-9a68-4185-9c92-1ffd7f2123a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958318890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2958318890
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.697577764
Short name T43
Test name
Test status
Simulation time 18629512 ps
CPU time 0.8 seconds
Started Apr 21 01:30:09 PM PDT 24
Finished Apr 21 01:30:10 PM PDT 24
Peak memory 208616 kb
Host smart-e5b5a4e9-e2d7-4541-bea5-022315eda0d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697577764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.697577764
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3408798664
Short name T526
Test name
Test status
Simulation time 41840433 ps
CPU time 0.97 seconds
Started Apr 21 01:31:27 PM PDT 24
Finished Apr 21 01:31:28 PM PDT 24
Peak memory 209428 kb
Host smart-758443ae-31f1-4604-ab7c-35831ade0df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408798664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3408798664
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1964274076
Short name T370
Test name
Test status
Simulation time 1036078349 ps
CPU time 10.15 seconds
Started Apr 21 01:31:19 PM PDT 24
Finished Apr 21 01:31:29 PM PDT 24
Peak memory 225892 kb
Host smart-85c4d1ef-0709-4b2e-a7c5-6382747c7eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964274076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1964274076
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1114944371
Short name T782
Test name
Test status
Simulation time 707324589 ps
CPU time 7.9 seconds
Started Apr 21 01:31:22 PM PDT 24
Finished Apr 21 01:31:30 PM PDT 24
Peak memory 217236 kb
Host smart-d739bb4e-4c67-4718-8850-76e32c89cd28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114944371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1114944371
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1762714692
Short name T708
Test name
Test status
Simulation time 3256103177 ps
CPU time 29.52 seconds
Started Apr 21 01:31:21 PM PDT 24
Finished Apr 21 01:31:51 PM PDT 24
Peak memory 219008 kb
Host smart-5a93344d-5852-4dc5-bf09-a9383416441f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762714692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1762714692
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4060588564
Short name T493
Test name
Test status
Simulation time 432016261 ps
CPU time 12.79 seconds
Started Apr 21 01:31:23 PM PDT 24
Finished Apr 21 01:31:36 PM PDT 24
Peak memory 217856 kb
Host smart-13717eff-147c-4d57-bb76-c374ef9839af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060588564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4060588564
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3240594223
Short name T671
Test name
Test status
Simulation time 4443094694 ps
CPU time 5.96 seconds
Started Apr 21 01:31:22 PM PDT 24
Finished Apr 21 01:31:28 PM PDT 24
Peak memory 214076 kb
Host smart-78ac3e23-f887-4332-9786-867a2745da1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240594223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3240594223
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3146292125
Short name T466
Test name
Test status
Simulation time 1018039657 ps
CPU time 37.57 seconds
Started Apr 21 01:31:22 PM PDT 24
Finished Apr 21 01:32:00 PM PDT 24
Peak memory 268044 kb
Host smart-a7bb8a4c-77e4-4510-ab4b-3d7a9f7cecea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146292125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3146292125
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1908782809
Short name T253
Test name
Test status
Simulation time 8667858398 ps
CPU time 15.19 seconds
Started Apr 21 01:31:20 PM PDT 24
Finished Apr 21 01:31:36 PM PDT 24
Peak memory 250756 kb
Host smart-8add3da0-e509-42b6-92e0-622645401198
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908782809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1908782809
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.272399607
Short name T654
Test name
Test status
Simulation time 362794720 ps
CPU time 3.3 seconds
Started Apr 21 01:31:19 PM PDT 24
Finished Apr 21 01:31:23 PM PDT 24
Peak memory 217808 kb
Host smart-fe5d3676-786a-4065-bea6-2e5f85e6f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272399607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.272399607
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1708667551
Short name T345
Test name
Test status
Simulation time 1278190667 ps
CPU time 11.82 seconds
Started Apr 21 01:31:22 PM PDT 24
Finished Apr 21 01:31:34 PM PDT 24
Peak memory 225872 kb
Host smart-19a444d1-98eb-4dfb-9093-946e5c01c2a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708667551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1708667551
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2741718176
Short name T222
Test name
Test status
Simulation time 617885820 ps
CPU time 8.41 seconds
Started Apr 21 01:31:23 PM PDT 24
Finished Apr 21 01:31:32 PM PDT 24
Peak memory 217920 kb
Host smart-61a3109a-8817-49bf-98c0-c946d910b514
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741718176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2741718176
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.72670850
Short name T681
Test name
Test status
Simulation time 293990114 ps
CPU time 10.79 seconds
Started Apr 21 01:31:22 PM PDT 24
Finished Apr 21 01:31:33 PM PDT 24
Peak memory 217860 kb
Host smart-3ebcbc2b-052b-4047-9796-b526d58b0234
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72670850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.72670850
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1080039755
Short name T455
Test name
Test status
Simulation time 322151899 ps
CPU time 11.11 seconds
Started Apr 21 01:31:25 PM PDT 24
Finished Apr 21 01:31:36 PM PDT 24
Peak memory 217884 kb
Host smart-d5d96fde-244c-48d8-a62d-de8a36e6f5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080039755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1080039755
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2017599883
Short name T471
Test name
Test status
Simulation time 151207761 ps
CPU time 2.76 seconds
Started Apr 21 01:31:19 PM PDT 24
Finished Apr 21 01:31:22 PM PDT 24
Peak memory 214712 kb
Host smart-699fa5f0-3383-4e7d-915d-11903e772776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017599883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2017599883
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2066808348
Short name T540
Test name
Test status
Simulation time 207042846 ps
CPU time 27.18 seconds
Started Apr 21 01:31:21 PM PDT 24
Finished Apr 21 01:31:48 PM PDT 24
Peak memory 248440 kb
Host smart-a513dcf0-3fba-4cde-a5f7-5896d015d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066808348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2066808348
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.600425801
Short name T844
Test name
Test status
Simulation time 79186045 ps
CPU time 7.18 seconds
Started Apr 21 01:31:18 PM PDT 24
Finished Apr 21 01:31:26 PM PDT 24
Peak memory 250860 kb
Host smart-fe1f6868-c170-47e5-a3a9-97b50bc8a47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600425801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.600425801
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1089802353
Short name T527
Test name
Test status
Simulation time 3645365761 ps
CPU time 113.58 seconds
Started Apr 21 01:31:28 PM PDT 24
Finished Apr 21 01:33:22 PM PDT 24
Peak memory 273592 kb
Host smart-f26521c8-19db-4e2b-9ce3-94da3c11cab9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089802353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1089802353
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.16099922
Short name T693
Test name
Test status
Simulation time 44669899 ps
CPU time 0.96 seconds
Started Apr 21 01:31:33 PM PDT 24
Finished Apr 21 01:31:34 PM PDT 24
Peak memory 209388 kb
Host smart-d7158a5c-49b1-4341-b1f0-77ce942ff0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16099922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.16099922
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1242023056
Short name T249
Test name
Test status
Simulation time 383000785 ps
CPU time 13.12 seconds
Started Apr 21 01:31:33 PM PDT 24
Finished Apr 21 01:31:46 PM PDT 24
Peak memory 225916 kb
Host smart-16ba08d8-2901-49f6-8868-04ad7070d2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242023056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1242023056
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.895329183
Short name T495
Test name
Test status
Simulation time 1443881709 ps
CPU time 8.03 seconds
Started Apr 21 01:31:29 PM PDT 24
Finished Apr 21 01:31:37 PM PDT 24
Peak memory 216804 kb
Host smart-d44847a5-8a8b-4b90-a301-bc495cb64687
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895329183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.895329183
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1971725208
Short name T538
Test name
Test status
Simulation time 43741702226 ps
CPU time 31.85 seconds
Started Apr 21 01:31:30 PM PDT 24
Finished Apr 21 01:32:02 PM PDT 24
Peak memory 218396 kb
Host smart-d2030c08-309f-4347-b4b9-3bc92340b334
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971725208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1971725208
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.658560940
Short name T342
Test name
Test status
Simulation time 1337423580 ps
CPU time 11.18 seconds
Started Apr 21 01:31:30 PM PDT 24
Finished Apr 21 01:31:41 PM PDT 24
Peak memory 217776 kb
Host smart-55edc25e-be0a-4bfc-ba27-49c7a3d14ea4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658560940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.658560940
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2468031989
Short name T281
Test name
Test status
Simulation time 189664612 ps
CPU time 2.12 seconds
Started Apr 21 01:31:27 PM PDT 24
Finished Apr 21 01:31:30 PM PDT 24
Peak memory 212836 kb
Host smart-6cc16dc6-4166-4d51-a190-5e5f7899e960
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468031989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2468031989
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3246384227
Short name T810
Test name
Test status
Simulation time 1780521539 ps
CPU time 38.06 seconds
Started Apr 21 01:31:31 PM PDT 24
Finished Apr 21 01:32:09 PM PDT 24
Peak memory 268532 kb
Host smart-a123beac-493b-4324-a5af-5d3395a8e49a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246384227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3246384227
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.479940816
Short name T295
Test name
Test status
Simulation time 8734386469 ps
CPU time 10.86 seconds
Started Apr 21 01:31:28 PM PDT 24
Finished Apr 21 01:31:39 PM PDT 24
Peak memory 245140 kb
Host smart-34eb184b-57d8-4360-8ce6-d16b2fd9a860
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479940816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.479940816
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.954546764
Short name T115
Test name
Test status
Simulation time 203813966 ps
CPU time 2.32 seconds
Started Apr 21 01:31:27 PM PDT 24
Finished Apr 21 01:31:29 PM PDT 24
Peak memory 217812 kb
Host smart-e104a636-bca0-4c92-a588-70bafac70471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954546764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.954546764
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1388313575
Short name T565
Test name
Test status
Simulation time 280139284 ps
CPU time 10.03 seconds
Started Apr 21 01:31:28 PM PDT 24
Finished Apr 21 01:31:38 PM PDT 24
Peak memory 216900 kb
Host smart-0000548a-a535-4a27-9fbc-b69851819f38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388313575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1388313575
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2327400601
Short name T510
Test name
Test status
Simulation time 375965503 ps
CPU time 8.84 seconds
Started Apr 21 01:31:30 PM PDT 24
Finished Apr 21 01:31:39 PM PDT 24
Peak memory 217876 kb
Host smart-ca18b50e-f5c1-49d6-8b8c-6239a5de622a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327400601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2327400601
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1789207090
Short name T243
Test name
Test status
Simulation time 1209681088 ps
CPU time 9.27 seconds
Started Apr 21 01:31:28 PM PDT 24
Finished Apr 21 01:31:37 PM PDT 24
Peak memory 217868 kb
Host smart-bdaa2b82-3f8b-4ae5-af38-75da85027afc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789207090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1789207090
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2011956102
Short name T405
Test name
Test status
Simulation time 1016662068 ps
CPU time 6.72 seconds
Started Apr 21 01:31:27 PM PDT 24
Finished Apr 21 01:31:34 PM PDT 24
Peak memory 225932 kb
Host smart-d582b113-7e8c-4f5a-99f9-c38e74148834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011956102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2011956102
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4104959501
Short name T694
Test name
Test status
Simulation time 144041452 ps
CPU time 1.69 seconds
Started Apr 21 01:31:28 PM PDT 24
Finished Apr 21 01:31:30 PM PDT 24
Peak memory 213284 kb
Host smart-866f4f7c-7ed5-4fb4-b9d4-f622a1396015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104959501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4104959501
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.358183854
Short name T313
Test name
Test status
Simulation time 663325672 ps
CPU time 27.76 seconds
Started Apr 21 01:31:31 PM PDT 24
Finished Apr 21 01:31:59 PM PDT 24
Peak memory 249052 kb
Host smart-cec117d8-b0e2-45b8-a409-f735c3e9ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358183854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.358183854
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2040139686
Short name T359
Test name
Test status
Simulation time 357413419 ps
CPU time 7.71 seconds
Started Apr 21 01:31:32 PM PDT 24
Finished Apr 21 01:31:40 PM PDT 24
Peak memory 250736 kb
Host smart-8894779c-693f-4f9e-be55-0771396a4fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040139686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2040139686
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.329575837
Short name T189
Test name
Test status
Simulation time 16764764237 ps
CPU time 65.67 seconds
Started Apr 21 01:31:29 PM PDT 24
Finished Apr 21 01:32:35 PM PDT 24
Peak memory 218592 kb
Host smart-fba0b2be-cb80-4e10-86f9-424d519f9bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329575837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.329575837
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2899649929
Short name T42
Test name
Test status
Simulation time 22279765 ps
CPU time 0.88 seconds
Started Apr 21 01:31:25 PM PDT 24
Finished Apr 21 01:31:26 PM PDT 24
Peak memory 208656 kb
Host smart-e79dbe8d-1d94-46cb-bc9c-c27ad628c1c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899649929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2899649929
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1887996785
Short name T645
Test name
Test status
Simulation time 16049819 ps
CPU time 0.87 seconds
Started Apr 21 01:31:40 PM PDT 24
Finished Apr 21 01:31:42 PM PDT 24
Peak memory 209444 kb
Host smart-75b28cbe-3b93-4148-8bf9-3b62644466d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887996785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1887996785
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2650927587
Short name T247
Test name
Test status
Simulation time 524417666 ps
CPU time 10.76 seconds
Started Apr 21 01:31:31 PM PDT 24
Finished Apr 21 01:31:42 PM PDT 24
Peak memory 217848 kb
Host smart-cff9da43-2c06-4c1a-a0c7-b2da6f3965b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650927587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2650927587
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2613497116
Short name T508
Test name
Test status
Simulation time 32849731 ps
CPU time 1.53 seconds
Started Apr 21 01:31:40 PM PDT 24
Finished Apr 21 01:31:42 PM PDT 24
Peak memory 216772 kb
Host smart-2e6b5cb4-6ab5-464c-a7ee-20343f4a1f6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613497116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2613497116
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2003733209
Short name T761
Test name
Test status
Simulation time 2762355961 ps
CPU time 23.94 seconds
Started Apr 21 01:31:31 PM PDT 24
Finished Apr 21 01:31:56 PM PDT 24
Peak memory 218012 kb
Host smart-8355eb1b-ca10-4128-99af-de72d6d3c71d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003733209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2003733209
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2733769996
Short name T334
Test name
Test status
Simulation time 147297717 ps
CPU time 5.13 seconds
Started Apr 21 01:31:31 PM PDT 24
Finished Apr 21 01:31:36 PM PDT 24
Peak memory 217872 kb
Host smart-7d9ec324-fb15-49d5-b719-0940b2b067d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733769996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2733769996
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3723348952
Short name T836
Test name
Test status
Simulation time 802035750 ps
CPU time 3.61 seconds
Started Apr 21 01:31:52 PM PDT 24
Finished Apr 21 01:31:56 PM PDT 24
Peak memory 213036 kb
Host smart-7928478d-ca95-44f9-a9ca-d37be20b99d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723348952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3723348952
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2035935982
Short name T177
Test name
Test status
Simulation time 2687037842 ps
CPU time 56.53 seconds
Started Apr 21 01:31:32 PM PDT 24
Finished Apr 21 01:32:28 PM PDT 24
Peak memory 276076 kb
Host smart-6b478409-b72d-4a36-9e37-b94e9bb3b458
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035935982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2035935982
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3543762770
Short name T557
Test name
Test status
Simulation time 1161049125 ps
CPU time 11.62 seconds
Started Apr 21 01:31:31 PM PDT 24
Finished Apr 21 01:31:43 PM PDT 24
Peak memory 250520 kb
Host smart-befe38b0-b925-4052-8b16-1799df8eacee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543762770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3543762770
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2228450242
Short name T710
Test name
Test status
Simulation time 117768906 ps
CPU time 3.88 seconds
Started Apr 21 01:31:32 PM PDT 24
Finished Apr 21 01:31:36 PM PDT 24
Peak memory 217936 kb
Host smart-5042fea7-e9ef-48f5-ac47-f17d88c545cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228450242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2228450242
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.984188792
Short name T180
Test name
Test status
Simulation time 1257113462 ps
CPU time 11.16 seconds
Started Apr 21 01:31:37 PM PDT 24
Finished Apr 21 01:31:48 PM PDT 24
Peak memory 225936 kb
Host smart-738af767-1ce7-45fb-8281-ff11d8246dd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984188792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.984188792
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3490610929
Short name T435
Test name
Test status
Simulation time 1395165616 ps
CPU time 18.27 seconds
Started Apr 21 01:31:38 PM PDT 24
Finished Apr 21 01:31:56 PM PDT 24
Peak memory 217884 kb
Host smart-6a0e8ee1-19db-46dc-bf0c-082a683c589f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490610929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3490610929
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3185620379
Short name T460
Test name
Test status
Simulation time 357714833 ps
CPU time 8.85 seconds
Started Apr 21 01:31:37 PM PDT 24
Finished Apr 21 01:31:46 PM PDT 24
Peak memory 217952 kb
Host smart-30b5521f-4907-4ccc-b363-49b52379c7d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185620379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3185620379
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2798026632
Short name T65
Test name
Test status
Simulation time 347234993 ps
CPU time 12.34 seconds
Started Apr 21 01:31:37 PM PDT 24
Finished Apr 21 01:31:50 PM PDT 24
Peak memory 217948 kb
Host smart-bf0d1dcc-436b-44be-8449-701a3ad2c6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798026632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2798026632
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3185404513
Short name T231
Test name
Test status
Simulation time 60113357 ps
CPU time 3.54 seconds
Started Apr 21 01:31:29 PM PDT 24
Finished Apr 21 01:31:33 PM PDT 24
Peak memory 214424 kb
Host smart-db9cb6f4-000e-4214-b01f-87e74798d447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185404513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3185404513
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2508351126
Short name T491
Test name
Test status
Simulation time 250870350 ps
CPU time 26.31 seconds
Started Apr 21 01:31:32 PM PDT 24
Finished Apr 21 01:31:59 PM PDT 24
Peak memory 250708 kb
Host smart-0c416e6f-4f22-490e-afa1-10237597c70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508351126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2508351126
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.558294257
Short name T329
Test name
Test status
Simulation time 257979202 ps
CPU time 6.74 seconds
Started Apr 21 01:31:32 PM PDT 24
Finished Apr 21 01:31:39 PM PDT 24
Peak memory 250792 kb
Host smart-6d1c517b-5570-462d-abb8-d7c30b87e172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558294257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.558294257
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.474571571
Short name T69
Test name
Test status
Simulation time 253611758 ps
CPU time 8.44 seconds
Started Apr 21 01:31:40 PM PDT 24
Finished Apr 21 01:31:48 PM PDT 24
Peak memory 217412 kb
Host smart-7fde19e5-ce58-4862-9323-a7f771903ad7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474571571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.474571571
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.959710408
Short name T767
Test name
Test status
Simulation time 10912499 ps
CPU time 0.9 seconds
Started Apr 21 01:31:32 PM PDT 24
Finished Apr 21 01:31:33 PM PDT 24
Peak memory 208672 kb
Host smart-15d5a2d3-7eb4-44cb-be3c-e75913da9808
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959710408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.959710408
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3918810628
Short name T412
Test name
Test status
Simulation time 40103574 ps
CPU time 1.16 seconds
Started Apr 21 01:31:44 PM PDT 24
Finished Apr 21 01:31:46 PM PDT 24
Peak memory 209416 kb
Host smart-d4132436-a2d7-4a11-8e3d-4446cf288407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918810628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3918810628
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1647208547
Short name T480
Test name
Test status
Simulation time 3260040358 ps
CPU time 19.59 seconds
Started Apr 21 01:31:41 PM PDT 24
Finished Apr 21 01:32:01 PM PDT 24
Peak memory 217976 kb
Host smart-fbe37f6e-e28d-44ef-b9a0-614543ee854e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647208547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1647208547
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1050207159
Short name T577
Test name
Test status
Simulation time 2737513259 ps
CPU time 40.05 seconds
Started Apr 21 01:31:44 PM PDT 24
Finished Apr 21 01:32:25 PM PDT 24
Peak memory 217908 kb
Host smart-43ae3921-f281-499c-b88b-68a21d4edc63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050207159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1050207159
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3017738415
Short name T84
Test name
Test status
Simulation time 599378333 ps
CPU time 3.43 seconds
Started Apr 21 01:31:40 PM PDT 24
Finished Apr 21 01:31:44 PM PDT 24
Peak memory 212852 kb
Host smart-71a7e396-1d4a-4a3a-bd67-d683b7554b82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017738415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3017738415
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2354908919
Short name T763
Test name
Test status
Simulation time 13168398362 ps
CPU time 42.37 seconds
Started Apr 21 01:31:40 PM PDT 24
Finished Apr 21 01:32:23 PM PDT 24
Peak memory 271564 kb
Host smart-1ea06365-3d48-405d-94bb-22cdd1308192
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354908919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2354908919
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3994211247
Short name T706
Test name
Test status
Simulation time 7233976413 ps
CPU time 28.83 seconds
Started Apr 21 01:31:37 PM PDT 24
Finished Apr 21 01:32:06 PM PDT 24
Peak memory 248176 kb
Host smart-cb655b74-7d60-44c7-b879-7453adbc6215
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994211247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3994211247
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3865236723
Short name T159
Test name
Test status
Simulation time 27248625 ps
CPU time 1.91 seconds
Started Apr 21 01:31:38 PM PDT 24
Finished Apr 21 01:31:40 PM PDT 24
Peak memory 217940 kb
Host smart-c45118e8-a898-4396-a76c-6db9d1991fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865236723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3865236723
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2156495738
Short name T462
Test name
Test status
Simulation time 2388099551 ps
CPU time 22.09 seconds
Started Apr 21 01:31:38 PM PDT 24
Finished Apr 21 01:32:00 PM PDT 24
Peak memory 226044 kb
Host smart-0494b24b-3bc5-4b9b-9980-8941d53cef61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156495738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2156495738
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4063810523
Short name T257
Test name
Test status
Simulation time 766963261 ps
CPU time 19.02 seconds
Started Apr 21 01:31:44 PM PDT 24
Finished Apr 21 01:32:04 PM PDT 24
Peak memory 217860 kb
Host smart-ed1568df-bc96-4890-b31b-535943fc223a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063810523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4063810523
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2804121963
Short name T410
Test name
Test status
Simulation time 324102348 ps
CPU time 8.53 seconds
Started Apr 21 01:31:38 PM PDT 24
Finished Apr 21 01:31:47 PM PDT 24
Peak memory 217892 kb
Host smart-34c28c2d-3874-474c-8111-e68e7e0cf9f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804121963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2804121963
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2499089977
Short name T306
Test name
Test status
Simulation time 1471546850 ps
CPU time 10.35 seconds
Started Apr 21 01:31:37 PM PDT 24
Finished Apr 21 01:31:47 PM PDT 24
Peak memory 217920 kb
Host smart-73606062-ff32-4796-919d-e88d7d1d618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499089977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2499089977
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2122966134
Short name T456
Test name
Test status
Simulation time 208682811 ps
CPU time 3.46 seconds
Started Apr 21 01:31:35 PM PDT 24
Finished Apr 21 01:31:39 PM PDT 24
Peak memory 213592 kb
Host smart-c7e8803e-eb9a-4095-ad22-ca1a328c80c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122966134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2122966134
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.45385986
Short name T407
Test name
Test status
Simulation time 874224703 ps
CPU time 23.13 seconds
Started Apr 21 01:31:38 PM PDT 24
Finished Apr 21 01:32:01 PM PDT 24
Peak memory 250880 kb
Host smart-f14e6515-5944-4059-91e6-b66127cd50f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45385986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.45385986
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1939389497
Short name T561
Test name
Test status
Simulation time 69263989 ps
CPU time 7.2 seconds
Started Apr 21 01:31:36 PM PDT 24
Finished Apr 21 01:31:44 PM PDT 24
Peak memory 246752 kb
Host smart-09221276-bd20-48d9-a7d4-be077028ef6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939389497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1939389497
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3199449562
Short name T591
Test name
Test status
Simulation time 27202755060 ps
CPU time 76.67 seconds
Started Apr 21 01:31:39 PM PDT 24
Finished Apr 21 01:32:56 PM PDT 24
Peak memory 250952 kb
Host smart-82350bec-d20d-426d-b7e9-1899fd8fa8b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199449562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3199449562
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2960473147
Short name T624
Test name
Test status
Simulation time 46285282 ps
CPU time 1.09 seconds
Started Apr 21 01:31:35 PM PDT 24
Finished Apr 21 01:31:37 PM PDT 24
Peak memory 212588 kb
Host smart-58f94315-bc9d-41b9-8903-18fdc1325567
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960473147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2960473147
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.25391732
Short name T260
Test name
Test status
Simulation time 151779429 ps
CPU time 0.99 seconds
Started Apr 21 01:31:49 PM PDT 24
Finished Apr 21 01:31:51 PM PDT 24
Peak memory 209396 kb
Host smart-cd6e6325-d89a-4237-b113-1f87dfb3407c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.25391732
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2600581586
Short name T470
Test name
Test status
Simulation time 605200968 ps
CPU time 8.08 seconds
Started Apr 21 01:31:41 PM PDT 24
Finished Apr 21 01:31:50 PM PDT 24
Peak memory 217848 kb
Host smart-b828fff1-59c6-4ebc-ac44-da355673f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600581586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2600581586
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.746029654
Short name T509
Test name
Test status
Simulation time 669507000 ps
CPU time 4.07 seconds
Started Apr 21 01:31:44 PM PDT 24
Finished Apr 21 01:31:49 PM PDT 24
Peak memory 209436 kb
Host smart-e306dd4c-bd78-4992-acb3-6ee50cb2f517
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746029654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.746029654
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3388783952
Short name T419
Test name
Test status
Simulation time 3604418147 ps
CPU time 40.33 seconds
Started Apr 21 01:31:46 PM PDT 24
Finished Apr 21 01:32:26 PM PDT 24
Peak memory 217928 kb
Host smart-6302ee02-2390-4e50-b823-7a53f889ed4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388783952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3388783952
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1342771201
Short name T803
Test name
Test status
Simulation time 114677092 ps
CPU time 2.58 seconds
Started Apr 21 01:31:44 PM PDT 24
Finished Apr 21 01:31:48 PM PDT 24
Peak memory 217684 kb
Host smart-f96deb41-c30e-4f14-8d52-0fe71f145f20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342771201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1342771201
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1432648232
Short name T791
Test name
Test status
Simulation time 806275618 ps
CPU time 10.96 seconds
Started Apr 21 01:31:46 PM PDT 24
Finished Apr 21 01:31:58 PM PDT 24
Peak memory 213500 kb
Host smart-0eb9da4f-a9c8-425c-b2e1-6fabbbb53595
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432648232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1432648232
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3592112578
Short name T852
Test name
Test status
Simulation time 2142989031 ps
CPU time 35.76 seconds
Started Apr 21 01:31:45 PM PDT 24
Finished Apr 21 01:32:22 PM PDT 24
Peak memory 267600 kb
Host smart-b3cc2ffe-8ff6-44ba-b185-1e6fe0724121
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592112578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3592112578
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3114223234
Short name T850
Test name
Test status
Simulation time 470904571 ps
CPU time 14.83 seconds
Started Apr 21 01:31:46 PM PDT 24
Finished Apr 21 01:32:01 PM PDT 24
Peak memory 217792 kb
Host smart-990b11f7-b744-4d76-81c3-4cea42cc7965
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114223234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3114223234
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1853134184
Short name T367
Test name
Test status
Simulation time 341698379 ps
CPU time 4.16 seconds
Started Apr 21 01:31:43 PM PDT 24
Finished Apr 21 01:31:48 PM PDT 24
Peak memory 217876 kb
Host smart-2813a059-cb96-4ed1-8a9e-433e3f6d75df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853134184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1853134184
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3543340817
Short name T552
Test name
Test status
Simulation time 274929091 ps
CPU time 10.97 seconds
Started Apr 21 01:31:46 PM PDT 24
Finished Apr 21 01:31:57 PM PDT 24
Peak memory 225948 kb
Host smart-8d9a6f09-cac7-4561-bad3-a0d014001eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543340817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3543340817
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2962754688
Short name T240
Test name
Test status
Simulation time 174701103 ps
CPU time 7.93 seconds
Started Apr 21 01:31:50 PM PDT 24
Finished Apr 21 01:31:58 PM PDT 24
Peak memory 217852 kb
Host smart-07ef320b-1bf3-4b59-ad12-b1a694b5cb13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962754688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2962754688
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.902190364
Short name T698
Test name
Test status
Simulation time 1466869612 ps
CPU time 7.82 seconds
Started Apr 21 01:31:48 PM PDT 24
Finished Apr 21 01:31:57 PM PDT 24
Peak memory 217800 kb
Host smart-891308c2-162e-48a9-becc-37617cb85501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902190364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.902190364
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.989867477
Short name T213
Test name
Test status
Simulation time 216535485 ps
CPU time 6.51 seconds
Started Apr 21 01:31:44 PM PDT 24
Finished Apr 21 01:31:51 PM PDT 24
Peak memory 224548 kb
Host smart-f13a9681-ec1a-4561-b22f-9e034e4ae600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989867477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.989867477
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3384640328
Short name T598
Test name
Test status
Simulation time 279664464 ps
CPU time 3.28 seconds
Started Apr 21 01:31:44 PM PDT 24
Finished Apr 21 01:31:47 PM PDT 24
Peak memory 217760 kb
Host smart-c484ead0-933d-433f-a7f6-e57afd515c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384640328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3384640328
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3909058732
Short name T607
Test name
Test status
Simulation time 788480614 ps
CPU time 15.34 seconds
Started Apr 21 01:31:42 PM PDT 24
Finished Apr 21 01:31:58 PM PDT 24
Peak memory 250780 kb
Host smart-4aae456b-d7dc-4e88-afff-7852c27bc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909058732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3909058732
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2684455213
Short name T269
Test name
Test status
Simulation time 69235313 ps
CPU time 7.08 seconds
Started Apr 21 01:31:41 PM PDT 24
Finished Apr 21 01:31:48 PM PDT 24
Peak memory 243356 kb
Host smart-b4ef8fc7-cef4-4197-863c-e1e14b0f7e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684455213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2684455213
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1524525644
Short name T587
Test name
Test status
Simulation time 3452440981 ps
CPU time 96.43 seconds
Started Apr 21 01:31:49 PM PDT 24
Finished Apr 21 01:33:25 PM PDT 24
Peak memory 278152 kb
Host smart-4aa67ac5-286a-449e-94a7-0ba6635e673c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524525644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1524525644
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1113853127
Short name T273
Test name
Test status
Simulation time 47028319 ps
CPU time 0.87 seconds
Started Apr 21 01:31:40 PM PDT 24
Finished Apr 21 01:31:41 PM PDT 24
Peak memory 212448 kb
Host smart-3e270fc5-d44b-4cc9-a3ba-342ef20df13f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113853127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1113853127
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.899769249
Short name T321
Test name
Test status
Simulation time 76003281 ps
CPU time 1.01 seconds
Started Apr 21 01:31:55 PM PDT 24
Finished Apr 21 01:31:57 PM PDT 24
Peak memory 209572 kb
Host smart-7a383185-f705-4963-b289-24b45d827c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899769249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.899769249
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1604922711
Short name T625
Test name
Test status
Simulation time 1029488998 ps
CPU time 15.16 seconds
Started Apr 21 01:31:58 PM PDT 24
Finished Apr 21 01:32:13 PM PDT 24
Peak memory 217932 kb
Host smart-0cc1854a-5cfd-4896-bcd2-4e39924e66bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604922711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1604922711
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.4145149395
Short name T822
Test name
Test status
Simulation time 1750224651 ps
CPU time 11.09 seconds
Started Apr 21 01:31:53 PM PDT 24
Finished Apr 21 01:32:04 PM PDT 24
Peak memory 209440 kb
Host smart-6ef5a182-35bf-445c-a3c9-f83616edb9c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145149395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.4145149395
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1177648480
Short name T797
Test name
Test status
Simulation time 2871896490 ps
CPU time 46.35 seconds
Started Apr 21 01:31:53 PM PDT 24
Finished Apr 21 01:32:40 PM PDT 24
Peak memory 218868 kb
Host smart-cd86afee-4268-4125-8d8d-62e43c35c8b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177648480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1177648480
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.917189582
Short name T529
Test name
Test status
Simulation time 2565730323 ps
CPU time 8.05 seconds
Started Apr 21 01:31:52 PM PDT 24
Finished Apr 21 01:32:00 PM PDT 24
Peak memory 217932 kb
Host smart-d97fbf79-315c-4ffb-a4d8-b1250fec855f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917189582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.917189582
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1978294645
Short name T265
Test name
Test status
Simulation time 1519060074 ps
CPU time 3.65 seconds
Started Apr 21 01:31:52 PM PDT 24
Finished Apr 21 01:31:56 PM PDT 24
Peak memory 212908 kb
Host smart-d5a1fd82-2955-4a56-9445-134ec672d545
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978294645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1978294645
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3450893197
Short name T616
Test name
Test status
Simulation time 3778385007 ps
CPU time 43.24 seconds
Started Apr 21 01:31:53 PM PDT 24
Finished Apr 21 01:32:37 PM PDT 24
Peak memory 250904 kb
Host smart-f3ab2d84-93ea-4efc-aeff-6a2bf7bd80f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450893197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3450893197
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1252781340
Short name T179
Test name
Test status
Simulation time 616663125 ps
CPU time 10.64 seconds
Started Apr 21 01:31:53 PM PDT 24
Finished Apr 21 01:32:04 PM PDT 24
Peak memory 223372 kb
Host smart-6e0e7aee-e6c7-49eb-b230-f05276f473ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252781340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1252781340
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1254434281
Short name T684
Test name
Test status
Simulation time 87711279 ps
CPU time 1.95 seconds
Started Apr 21 01:31:49 PM PDT 24
Finished Apr 21 01:31:51 PM PDT 24
Peak memory 217940 kb
Host smart-0e9bf47d-ac23-47e1-b64f-1b1a103af027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254434281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1254434281
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3468472099
Short name T663
Test name
Test status
Simulation time 257223498 ps
CPU time 9.08 seconds
Started Apr 21 01:31:55 PM PDT 24
Finished Apr 21 01:32:05 PM PDT 24
Peak memory 217844 kb
Host smart-17d15b45-c5ec-48c5-bc70-251ebf888a96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468472099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3468472099
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2996420569
Short name T802
Test name
Test status
Simulation time 1594476188 ps
CPU time 15.33 seconds
Started Apr 21 01:31:56 PM PDT 24
Finished Apr 21 01:32:12 PM PDT 24
Peak memory 217852 kb
Host smart-54423f54-064e-40a0-8c6c-921e92a599f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996420569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2996420569
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1970009297
Short name T58
Test name
Test status
Simulation time 809125954 ps
CPU time 6.72 seconds
Started Apr 21 01:31:55 PM PDT 24
Finished Apr 21 01:32:02 PM PDT 24
Peak memory 217892 kb
Host smart-3ed65d3c-0898-4811-9d19-5604b491d2da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970009297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1970009297
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1982166467
Short name T496
Test name
Test status
Simulation time 193106300 ps
CPU time 8.74 seconds
Started Apr 21 01:31:52 PM PDT 24
Finished Apr 21 01:32:01 PM PDT 24
Peak memory 217888 kb
Host smart-f098344b-21ba-40ea-8d5c-f00bafebcb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982166467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1982166467
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.882955022
Short name T814
Test name
Test status
Simulation time 45044932 ps
CPU time 1.21 seconds
Started Apr 21 01:31:50 PM PDT 24
Finished Apr 21 01:31:51 PM PDT 24
Peak memory 213168 kb
Host smart-78a49230-29f9-425e-acfe-ef4d8560ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882955022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.882955022
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2825812804
Short name T461
Test name
Test status
Simulation time 182061101 ps
CPU time 25.24 seconds
Started Apr 21 01:31:49 PM PDT 24
Finished Apr 21 01:32:15 PM PDT 24
Peak memory 246728 kb
Host smart-09679eb9-184c-4b5a-a9f9-178ff53d3e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825812804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2825812804
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1424003955
Short name T35
Test name
Test status
Simulation time 51669293 ps
CPU time 7.43 seconds
Started Apr 21 01:31:51 PM PDT 24
Finished Apr 21 01:31:59 PM PDT 24
Peak memory 250856 kb
Host smart-e8164454-fd7d-47e2-ab76-7a27d35c7fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424003955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1424003955
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2976702706
Short name T285
Test name
Test status
Simulation time 2080800199 ps
CPU time 62.23 seconds
Started Apr 21 01:31:56 PM PDT 24
Finished Apr 21 01:32:58 PM PDT 24
Peak memory 246768 kb
Host smart-aca1e8e0-668e-4914-9529-66dd7753036c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976702706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2976702706
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3464376672
Short name T392
Test name
Test status
Simulation time 10759556 ps
CPU time 0.77 seconds
Started Apr 21 01:31:49 PM PDT 24
Finished Apr 21 01:31:50 PM PDT 24
Peak memory 208424 kb
Host smart-4f948c8d-9093-4539-863a-499d5c8268b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464376672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3464376672
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1693529170
Short name T589
Test name
Test status
Simulation time 108490636 ps
CPU time 1.03 seconds
Started Apr 21 01:32:02 PM PDT 24
Finished Apr 21 01:32:03 PM PDT 24
Peak memory 209448 kb
Host smart-7158cbfa-382a-406a-b397-4a60372c171d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693529170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1693529170
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1416649429
Short name T376
Test name
Test status
Simulation time 2062431254 ps
CPU time 8.36 seconds
Started Apr 21 01:31:59 PM PDT 24
Finished Apr 21 01:32:08 PM PDT 24
Peak memory 217860 kb
Host smart-87668158-cf6b-4caf-9422-d67458b4fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416649429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1416649429
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3020844223
Short name T532
Test name
Test status
Simulation time 438540314 ps
CPU time 10.95 seconds
Started Apr 21 01:32:03 PM PDT 24
Finished Apr 21 01:32:15 PM PDT 24
Peak memory 208860 kb
Host smart-2583f73f-cb51-423a-ba4c-68da5888baa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020844223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3020844223
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3353071262
Short name T593
Test name
Test status
Simulation time 2587032378 ps
CPU time 65.4 seconds
Started Apr 21 01:32:04 PM PDT 24
Finished Apr 21 01:33:09 PM PDT 24
Peak memory 218004 kb
Host smart-729a140d-42e1-404e-b14a-2048f4fd90f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353071262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3353071262
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1412810806
Short name T825
Test name
Test status
Simulation time 762313719 ps
CPU time 6.95 seconds
Started Apr 21 01:32:06 PM PDT 24
Finished Apr 21 01:32:14 PM PDT 24
Peak memory 217776 kb
Host smart-9be51e1b-5f09-4255-8d7a-a8025a74dcca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412810806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1412810806
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3196275739
Short name T424
Test name
Test status
Simulation time 271107684 ps
CPU time 3.8 seconds
Started Apr 21 01:32:00 PM PDT 24
Finished Apr 21 01:32:04 PM PDT 24
Peak memory 212944 kb
Host smart-3314bc63-f501-4095-b4b9-c9cdb842febc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196275739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3196275739
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2550508906
Short name T610
Test name
Test status
Simulation time 1470103509 ps
CPU time 41.41 seconds
Started Apr 21 01:31:58 PM PDT 24
Finished Apr 21 01:32:40 PM PDT 24
Peak memory 271856 kb
Host smart-0b5d2389-1442-48ac-b1ec-8e723fddae18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550508906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2550508906
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2685290955
Short name T481
Test name
Test status
Simulation time 307993377 ps
CPU time 14.34 seconds
Started Apr 21 01:32:05 PM PDT 24
Finished Apr 21 01:32:19 PM PDT 24
Peak memory 250776 kb
Host smart-c6e80959-fe0c-4697-b625-d0e82aa48630
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685290955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2685290955
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.979056597
Short name T40
Test name
Test status
Simulation time 497039531 ps
CPU time 3.76 seconds
Started Apr 21 01:32:00 PM PDT 24
Finished Apr 21 01:32:04 PM PDT 24
Peak memory 217868 kb
Host smart-cdfa1144-e9ce-42f7-9c50-c7c64533053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979056597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.979056597
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.214647520
Short name T171
Test name
Test status
Simulation time 2966013920 ps
CPU time 15.81 seconds
Started Apr 21 01:32:01 PM PDT 24
Finished Apr 21 01:32:17 PM PDT 24
Peak memory 226084 kb
Host smart-cd96897b-7563-40d7-96b6-cb37ea32c9d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214647520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.214647520
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.873900049
Short name T807
Test name
Test status
Simulation time 2643133600 ps
CPU time 12.4 seconds
Started Apr 21 01:32:02 PM PDT 24
Finished Apr 21 01:32:15 PM PDT 24
Peak memory 217932 kb
Host smart-af13f087-0851-43a1-98fc-7401ef21231d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873900049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.873900049
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3942708025
Short name T402
Test name
Test status
Simulation time 250668850 ps
CPU time 7.06 seconds
Started Apr 21 01:32:03 PM PDT 24
Finished Apr 21 01:32:11 PM PDT 24
Peak memory 217144 kb
Host smart-de36feff-50b6-4b50-8d7d-132b8d236ab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942708025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3942708025
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2460767762
Short name T291
Test name
Test status
Simulation time 336472421 ps
CPU time 8.11 seconds
Started Apr 21 01:32:01 PM PDT 24
Finished Apr 21 01:32:09 PM PDT 24
Peak memory 224384 kb
Host smart-ee4f2796-56e7-43ba-bcaa-d34f277a22ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460767762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2460767762
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2757556424
Short name T622
Test name
Test status
Simulation time 272468178 ps
CPU time 4.82 seconds
Started Apr 21 01:32:01 PM PDT 24
Finished Apr 21 01:32:06 PM PDT 24
Peak memory 214540 kb
Host smart-8361ab26-7abe-4dc0-aa5e-383eeb9e7766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757556424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2757556424
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1197576267
Short name T652
Test name
Test status
Simulation time 400453014 ps
CPU time 20.86 seconds
Started Apr 21 01:31:59 PM PDT 24
Finished Apr 21 01:32:20 PM PDT 24
Peak memory 250448 kb
Host smart-317f42e3-3439-413c-9bc6-a1a2a1cc155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197576267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1197576267
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2617700933
Short name T301
Test name
Test status
Simulation time 222270308 ps
CPU time 3.45 seconds
Started Apr 21 01:32:03 PM PDT 24
Finished Apr 21 01:32:06 PM PDT 24
Peak memory 226208 kb
Host smart-dbaee3d8-059c-4313-9959-98557ceccf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617700933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2617700933
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3639770528
Short name T639
Test name
Test status
Simulation time 19195650785 ps
CPU time 168.86 seconds
Started Apr 21 01:32:03 PM PDT 24
Finished Apr 21 01:34:52 PM PDT 24
Peak memory 329020 kb
Host smart-177f309c-2a40-4359-9ce8-e245611be298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639770528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3639770528
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1361000829
Short name T50
Test name
Test status
Simulation time 17786034 ps
CPU time 0.81 seconds
Started Apr 21 01:31:59 PM PDT 24
Finished Apr 21 01:32:00 PM PDT 24
Peak memory 208636 kb
Host smart-a757a0e2-b2ec-4da4-8bb8-ab72f15f2a77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361000829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1361000829
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.140285807
Short name T651
Test name
Test status
Simulation time 17122952 ps
CPU time 1.11 seconds
Started Apr 21 01:32:16 PM PDT 24
Finished Apr 21 01:32:17 PM PDT 24
Peak memory 209444 kb
Host smart-737ff4cc-7e64-4a6d-ae58-59b4de8e65be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140285807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.140285807
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.4188586054
Short name T530
Test name
Test status
Simulation time 7635880441 ps
CPU time 12.64 seconds
Started Apr 21 01:32:12 PM PDT 24
Finished Apr 21 01:32:25 PM PDT 24
Peak memory 226024 kb
Host smart-5b5e11f9-7daf-40b2-b233-3213805fbb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188586054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4188586054
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2504053191
Short name T665
Test name
Test status
Simulation time 424272587 ps
CPU time 10.79 seconds
Started Apr 21 01:32:08 PM PDT 24
Finished Apr 21 01:32:19 PM PDT 24
Peak memory 209468 kb
Host smart-d2f6507e-9b2d-40a5-9f1a-8c362171519c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504053191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2504053191
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.623947753
Short name T453
Test name
Test status
Simulation time 1418526563 ps
CPU time 23.05 seconds
Started Apr 21 01:32:06 PM PDT 24
Finished Apr 21 01:32:29 PM PDT 24
Peak memory 217728 kb
Host smart-19ef845e-f790-4b65-a28a-7575f7f819e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623947753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.623947753
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3955859397
Short name T22
Test name
Test status
Simulation time 1711908425 ps
CPU time 3.16 seconds
Started Apr 21 01:32:05 PM PDT 24
Finished Apr 21 01:32:09 PM PDT 24
Peak memory 217764 kb
Host smart-8865d342-fa84-43ee-84ff-7c13313450ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955859397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3955859397
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.331386681
Short name T715
Test name
Test status
Simulation time 539392222 ps
CPU time 6.87 seconds
Started Apr 21 01:32:12 PM PDT 24
Finished Apr 21 01:32:19 PM PDT 24
Peak memory 213524 kb
Host smart-ed6797b1-fe74-4b06-a04c-faca4c802771
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331386681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
331386681
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2742973715
Short name T266
Test name
Test status
Simulation time 10773598417 ps
CPU time 51.11 seconds
Started Apr 21 01:32:06 PM PDT 24
Finished Apr 21 01:32:57 PM PDT 24
Peak memory 272680 kb
Host smart-4116d6a7-ac29-494e-b45d-0c20acc92d38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742973715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2742973715
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.780519105
Short name T4
Test name
Test status
Simulation time 912999531 ps
CPU time 10.1 seconds
Started Apr 21 01:32:08 PM PDT 24
Finished Apr 21 01:32:19 PM PDT 24
Peak memory 245568 kb
Host smart-b754d1ae-e5a5-4a9e-ad86-2b5f0fba5ccc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780519105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.780519105
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2059082250
Short name T680
Test name
Test status
Simulation time 58800489 ps
CPU time 2.45 seconds
Started Apr 21 01:32:05 PM PDT 24
Finished Apr 21 01:32:08 PM PDT 24
Peak memory 217848 kb
Host smart-ee45d361-b505-4709-9c3c-b3f970c0f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059082250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2059082250
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3648922663
Short name T697
Test name
Test status
Simulation time 11117296873 ps
CPU time 15.73 seconds
Started Apr 21 01:32:12 PM PDT 24
Finished Apr 21 01:32:28 PM PDT 24
Peak memory 226024 kb
Host smart-370c50a0-3fd0-47b0-a36f-5d189454fa02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648922663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3648922663
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2060561053
Short name T718
Test name
Test status
Simulation time 377482294 ps
CPU time 15.52 seconds
Started Apr 21 01:32:10 PM PDT 24
Finished Apr 21 01:32:26 PM PDT 24
Peak memory 217864 kb
Host smart-1c86c18d-2483-4480-a0a6-05df1b5d409e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060561053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2060561053
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.4105679453
Short name T714
Test name
Test status
Simulation time 2103303500 ps
CPU time 8.24 seconds
Started Apr 21 01:32:10 PM PDT 24
Finished Apr 21 01:32:19 PM PDT 24
Peak memory 217856 kb
Host smart-572bf8ff-15ef-4687-9bac-cf771f70f4ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105679453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
4105679453
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1900801807
Short name T387
Test name
Test status
Simulation time 271587625 ps
CPU time 8 seconds
Started Apr 21 01:32:05 PM PDT 24
Finished Apr 21 01:32:13 PM PDT 24
Peak memory 217908 kb
Host smart-9dbc610b-6e88-4dc5-a5f4-578ed94b2556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900801807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1900801807
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3371089062
Short name T385
Test name
Test status
Simulation time 27610565 ps
CPU time 1.15 seconds
Started Apr 21 01:32:03 PM PDT 24
Finished Apr 21 01:32:05 PM PDT 24
Peak memory 217768 kb
Host smart-2933e7f4-8d38-4707-bfa0-3016667fa092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371089062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3371089062
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1917187400
Short name T254
Test name
Test status
Simulation time 1415889875 ps
CPU time 21.13 seconds
Started Apr 21 01:32:05 PM PDT 24
Finished Apr 21 01:32:27 PM PDT 24
Peak memory 250708 kb
Host smart-cbcf2a04-ddfe-47f0-8454-2584de18a101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917187400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1917187400
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.220993524
Short name T776
Test name
Test status
Simulation time 7613740993 ps
CPU time 156.85 seconds
Started Apr 21 01:32:16 PM PDT 24
Finished Apr 21 01:34:53 PM PDT 24
Peak memory 275552 kb
Host smart-682e2276-6a1a-405a-8c58-022d215610be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220993524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.220993524
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3756736144
Short name T105
Test name
Test status
Simulation time 11117308 ps
CPU time 0.88 seconds
Started Apr 21 01:32:06 PM PDT 24
Finished Apr 21 01:32:07 PM PDT 24
Peak memory 208704 kb
Host smart-b591837d-5c06-42ab-8d5e-bdc22f3d8dd8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756736144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3756736144
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2918780482
Short name T641
Test name
Test status
Simulation time 21763543 ps
CPU time 0.9 seconds
Started Apr 21 01:32:15 PM PDT 24
Finished Apr 21 01:32:16 PM PDT 24
Peak memory 209420 kb
Host smart-1b2fc2a9-0708-470d-9ef6-adbc9474c104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918780482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2918780482
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3513270327
Short name T535
Test name
Test status
Simulation time 1477072488 ps
CPU time 11.65 seconds
Started Apr 21 01:32:15 PM PDT 24
Finished Apr 21 01:32:27 PM PDT 24
Peak memory 217808 kb
Host smart-e6fb1438-611c-47f5-88a8-a86ea0673443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513270327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3513270327
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3856268462
Short name T311
Test name
Test status
Simulation time 335014921 ps
CPU time 2.1 seconds
Started Apr 21 01:32:13 PM PDT 24
Finished Apr 21 01:32:16 PM PDT 24
Peak memory 209436 kb
Host smart-02ba10f5-37a1-40f1-ac1a-a3557e62e578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856268462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3856268462
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1101610954
Short name T773
Test name
Test status
Simulation time 1123139393 ps
CPU time 19.76 seconds
Started Apr 21 01:32:27 PM PDT 24
Finished Apr 21 01:32:47 PM PDT 24
Peak memory 217792 kb
Host smart-cee17401-4c56-4f0b-9cba-928721e07476
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101610954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1101610954
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3949910173
Short name T766
Test name
Test status
Simulation time 2605839536 ps
CPU time 22.48 seconds
Started Apr 21 01:32:15 PM PDT 24
Finished Apr 21 01:32:37 PM PDT 24
Peak memory 217952 kb
Host smart-a956100c-2eea-4860-89ab-76ebf6ba1fdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949910173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3949910173
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.4271561129
Short name T440
Test name
Test status
Simulation time 240987728 ps
CPU time 2.24 seconds
Started Apr 21 01:32:13 PM PDT 24
Finished Apr 21 01:32:15 PM PDT 24
Peak memory 212764 kb
Host smart-0ceb356a-d095-485b-bc52-82710fcfe5ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271561129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.4271561129
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1871941393
Short name T793
Test name
Test status
Simulation time 4841703979 ps
CPU time 49.45 seconds
Started Apr 21 01:32:12 PM PDT 24
Finished Apr 21 01:33:02 PM PDT 24
Peak memory 251080 kb
Host smart-1084d4d0-c937-42e9-be43-187b218f0868
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871941393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1871941393
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4294592440
Short name T789
Test name
Test status
Simulation time 594633867 ps
CPU time 12.15 seconds
Started Apr 21 01:32:12 PM PDT 24
Finished Apr 21 01:32:25 PM PDT 24
Peak memory 247216 kb
Host smart-8424c604-a82a-43dd-997e-726000b9d31c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294592440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.4294592440
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1725683005
Short name T606
Test name
Test status
Simulation time 28245848 ps
CPU time 2.18 seconds
Started Apr 21 01:32:13 PM PDT 24
Finished Apr 21 01:32:16 PM PDT 24
Peak memory 217872 kb
Host smart-891e596c-753e-485a-b18a-0082c147b425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725683005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1725683005
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.4264417438
Short name T437
Test name
Test status
Simulation time 731268210 ps
CPU time 12.21 seconds
Started Apr 21 01:32:17 PM PDT 24
Finished Apr 21 01:32:29 PM PDT 24
Peak memory 225620 kb
Host smart-ed834028-4f4e-402b-9406-76002041f32c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264417438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.4264417438
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1730417126
Short name T544
Test name
Test status
Simulation time 740022323 ps
CPU time 8.37 seconds
Started Apr 21 01:32:17 PM PDT 24
Finished Apr 21 01:32:26 PM PDT 24
Peak memory 217852 kb
Host smart-7c86bd9b-b07f-4b9c-952c-719eb617c2e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730417126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1730417126
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1848749041
Short name T307
Test name
Test status
Simulation time 1173597510 ps
CPU time 8.72 seconds
Started Apr 21 01:32:17 PM PDT 24
Finished Apr 21 01:32:26 PM PDT 24
Peak memory 217860 kb
Host smart-15ec246a-902d-427d-a7b5-da29703cd029
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848749041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1848749041
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1096885863
Short name T759
Test name
Test status
Simulation time 339064709 ps
CPU time 6.15 seconds
Started Apr 21 01:32:14 PM PDT 24
Finished Apr 21 01:32:21 PM PDT 24
Peak memory 217940 kb
Host smart-2ecdf1ae-1abc-44c4-86fe-738b0c57528a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096885863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1096885863
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.981805225
Short name T241
Test name
Test status
Simulation time 27967896 ps
CPU time 1.09 seconds
Started Apr 21 01:32:16 PM PDT 24
Finished Apr 21 01:32:17 PM PDT 24
Peak memory 213096 kb
Host smart-197f2fd2-bc1e-4882-a0b1-a6048f75ad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981805225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.981805225
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3144419306
Short name T215
Test name
Test status
Simulation time 616666035 ps
CPU time 25.66 seconds
Started Apr 21 01:32:12 PM PDT 24
Finished Apr 21 01:32:38 PM PDT 24
Peak memory 250612 kb
Host smart-cc900135-8aab-44fd-84a9-6b423a03afa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144419306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3144419306
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1633075153
Short name T812
Test name
Test status
Simulation time 496558015 ps
CPU time 6.96 seconds
Started Apr 21 01:32:12 PM PDT 24
Finished Apr 21 01:32:20 PM PDT 24
Peak memory 250808 kb
Host smart-22c6606f-c31b-4d6b-8371-ddb8cb186d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633075153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1633075153
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1904613391
Short name T760
Test name
Test status
Simulation time 31601124396 ps
CPU time 49.83 seconds
Started Apr 21 01:32:20 PM PDT 24
Finished Apr 21 01:33:11 PM PDT 24
Peak memory 250972 kb
Host smart-c860acc8-f0ea-42a3-8c28-831f6e73e0c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904613391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1904613391
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2810975029
Short name T298
Test name
Test status
Simulation time 21660684 ps
CPU time 1.05 seconds
Started Apr 21 01:32:15 PM PDT 24
Finished Apr 21 01:32:16 PM PDT 24
Peak memory 211452 kb
Host smart-8aea85d0-707f-427b-baeb-449719b55a53
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810975029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2810975029
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3184570016
Short name T627
Test name
Test status
Simulation time 17614886 ps
CPU time 0.94 seconds
Started Apr 21 01:32:23 PM PDT 24
Finished Apr 21 01:32:24 PM PDT 24
Peak memory 209468 kb
Host smart-b9d5eb5d-53eb-4649-a49e-934c124b0886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184570016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3184570016
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3347240564
Short name T294
Test name
Test status
Simulation time 1094379526 ps
CPU time 17.86 seconds
Started Apr 21 01:32:21 PM PDT 24
Finished Apr 21 01:32:39 PM PDT 24
Peak memory 217856 kb
Host smart-a4963d72-8e0d-450b-a346-1e5e3b08e52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347240564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3347240564
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3666347055
Short name T787
Test name
Test status
Simulation time 9320205107 ps
CPU time 8.5 seconds
Started Apr 21 01:32:22 PM PDT 24
Finished Apr 21 01:32:31 PM PDT 24
Peak memory 209676 kb
Host smart-cbba46a7-f220-40be-9684-d13837a81dea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666347055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3666347055
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1132385286
Short name T92
Test name
Test status
Simulation time 7230402029 ps
CPU time 43.51 seconds
Started Apr 21 01:32:20 PM PDT 24
Finished Apr 21 01:33:04 PM PDT 24
Peak memory 218368 kb
Host smart-6fed8b76-fb2a-42f5-a3a1-074cb7660cf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132385286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1132385286
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2938018274
Short name T573
Test name
Test status
Simulation time 1256926118 ps
CPU time 9.95 seconds
Started Apr 21 01:32:24 PM PDT 24
Finished Apr 21 01:32:34 PM PDT 24
Peak memory 217804 kb
Host smart-f1e7016e-89b3-41f1-bafc-0a977fca0d98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938018274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2938018274
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1734565115
Short name T351
Test name
Test status
Simulation time 504611524 ps
CPU time 4.89 seconds
Started Apr 21 01:32:23 PM PDT 24
Finished Apr 21 01:32:29 PM PDT 24
Peak memory 213660 kb
Host smart-73cb1e04-24cc-4274-a401-04d63aa20f44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734565115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1734565115
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.501493357
Short name T374
Test name
Test status
Simulation time 1166661874 ps
CPU time 30.72 seconds
Started Apr 21 01:32:19 PM PDT 24
Finished Apr 21 01:32:50 PM PDT 24
Peak memory 250784 kb
Host smart-e44ece1e-bd73-44fe-b907-53a5f81fe3ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501493357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.501493357
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2451650726
Short name T21
Test name
Test status
Simulation time 2124857089 ps
CPU time 12.09 seconds
Started Apr 21 01:32:23 PM PDT 24
Finished Apr 21 01:32:36 PM PDT 24
Peak memory 250380 kb
Host smart-783e0b4e-0daf-413e-abaa-76f579688048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451650726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2451650726
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1548889238
Short name T228
Test name
Test status
Simulation time 81396328 ps
CPU time 2.16 seconds
Started Apr 21 01:32:17 PM PDT 24
Finished Apr 21 01:32:19 PM PDT 24
Peak memory 217888 kb
Host smart-302112b1-b18b-4966-a38e-41d21455c146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548889238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1548889238
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2303011522
Short name T724
Test name
Test status
Simulation time 370580895 ps
CPU time 10.5 seconds
Started Apr 21 01:32:22 PM PDT 24
Finished Apr 21 01:32:33 PM PDT 24
Peak memory 218000 kb
Host smart-ad6917ec-eda5-4f73-9635-9a569f8d34d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303011522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2303011522
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3611459605
Short name T1
Test name
Test status
Simulation time 468954566 ps
CPU time 10.6 seconds
Started Apr 21 01:32:20 PM PDT 24
Finished Apr 21 01:32:31 PM PDT 24
Peak memory 217868 kb
Host smart-b2de33d9-fe67-438c-9551-0456caa2110f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611459605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3611459605
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2916459719
Short name T650
Test name
Test status
Simulation time 297662781 ps
CPU time 11.42 seconds
Started Apr 21 01:32:18 PM PDT 24
Finished Apr 21 01:32:30 PM PDT 24
Peak memory 217880 kb
Host smart-1385160c-07da-4111-bf19-44728d5ce133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916459719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2916459719
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2990657149
Short name T361
Test name
Test status
Simulation time 829913230 ps
CPU time 8.65 seconds
Started Apr 21 01:32:24 PM PDT 24
Finished Apr 21 01:32:33 PM PDT 24
Peak memory 217884 kb
Host smart-14af0498-60f3-4a49-96e9-fc322868d612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990657149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2990657149
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2549625993
Short name T119
Test name
Test status
Simulation time 52708903 ps
CPU time 2.69 seconds
Started Apr 21 01:32:17 PM PDT 24
Finished Apr 21 01:32:20 PM PDT 24
Peak memory 213596 kb
Host smart-6ebe0137-6ee7-4a43-9d96-c22b65649dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549625993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2549625993
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3711535178
Short name T343
Test name
Test status
Simulation time 383902990 ps
CPU time 23.54 seconds
Started Apr 21 01:32:16 PM PDT 24
Finished Apr 21 01:32:40 PM PDT 24
Peak memory 250896 kb
Host smart-5f7e8b0c-af92-46e9-8cf6-e3798292bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711535178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3711535178
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4094317614
Short name T730
Test name
Test status
Simulation time 96447517 ps
CPU time 7.4 seconds
Started Apr 21 01:32:18 PM PDT 24
Finished Apr 21 01:32:25 PM PDT 24
Peak memory 246976 kb
Host smart-91d21a3a-0b16-47b8-8cc7-080588a22af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094317614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4094317614
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.248572220
Short name T292
Test name
Test status
Simulation time 2324617511 ps
CPU time 24.88 seconds
Started Apr 21 01:32:19 PM PDT 24
Finished Apr 21 01:32:44 PM PDT 24
Peak memory 246544 kb
Host smart-7089cbb4-95da-4d4d-bc44-dfb249609501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248572220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.248572220
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1596812247
Short name T157
Test name
Test status
Simulation time 5488894956 ps
CPU time 215.68 seconds
Started Apr 21 01:32:18 PM PDT 24
Finished Apr 21 01:35:54 PM PDT 24
Peak memory 332992 kb
Host smart-0988bdf4-75cf-45ae-9c7c-533d5941fc82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1596812247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1596812247
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2498481609
Short name T746
Test name
Test status
Simulation time 58492120 ps
CPU time 0.84 seconds
Started Apr 21 01:32:18 PM PDT 24
Finished Apr 21 01:32:20 PM PDT 24
Peak memory 208452 kb
Host smart-5265d62b-1960-40ff-aebb-4309a48b8adf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498481609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2498481609
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3939196868
Short name T707
Test name
Test status
Simulation time 72659300 ps
CPU time 0.91 seconds
Started Apr 21 01:30:13 PM PDT 24
Finished Apr 21 01:30:14 PM PDT 24
Peak memory 209428 kb
Host smart-781b2b4c-9a86-4927-a2e9-aff03f0ee0ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939196868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3939196868
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.879524011
Short name T210
Test name
Test status
Simulation time 39762712 ps
CPU time 0.9 seconds
Started Apr 21 01:30:09 PM PDT 24
Finished Apr 21 01:30:10 PM PDT 24
Peak memory 209392 kb
Host smart-681131c9-06ec-4abc-897e-a32841a7377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879524011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.879524011
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2863421948
Short name T863
Test name
Test status
Simulation time 1371536925 ps
CPU time 15.83 seconds
Started Apr 21 01:30:07 PM PDT 24
Finished Apr 21 01:30:23 PM PDT 24
Peak memory 217880 kb
Host smart-0ddcba12-dd1f-4ada-ac9f-79410d11fccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863421948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2863421948
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1058206520
Short name T397
Test name
Test status
Simulation time 486651675 ps
CPU time 6.52 seconds
Started Apr 21 01:30:10 PM PDT 24
Finished Apr 21 01:30:17 PM PDT 24
Peak memory 216796 kb
Host smart-2ff307b5-9da7-40a4-bfab-482477dec4d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058206520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1058206520
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1202849830
Short name T319
Test name
Test status
Simulation time 3982644909 ps
CPU time 27.35 seconds
Started Apr 21 01:30:10 PM PDT 24
Finished Apr 21 01:30:37 PM PDT 24
Peak memory 218836 kb
Host smart-2c517fe3-5e3d-4661-a69d-98d33f9b5a6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202849830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1202849830
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2848472445
Short name T618
Test name
Test status
Simulation time 826171896 ps
CPU time 3.18 seconds
Started Apr 21 01:30:08 PM PDT 24
Finished Apr 21 01:30:12 PM PDT 24
Peak memory 217668 kb
Host smart-f2062b75-8985-4f38-b496-e100ae79b926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848472445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
848472445
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1074867133
Short name T790
Test name
Test status
Simulation time 412599446 ps
CPU time 3.53 seconds
Started Apr 21 01:30:11 PM PDT 24
Finished Apr 21 01:30:15 PM PDT 24
Peak memory 217804 kb
Host smart-c9ca45bb-9767-4211-be10-b03763f378f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074867133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1074867133
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3574886359
Short name T737
Test name
Test status
Simulation time 782617057 ps
CPU time 22.41 seconds
Started Apr 21 01:30:13 PM PDT 24
Finished Apr 21 01:30:35 PM PDT 24
Peak memory 213132 kb
Host smart-160ffc0b-c097-4281-8624-61733568c033
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574886359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3574886359
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.667279127
Short name T79
Test name
Test status
Simulation time 962543150 ps
CPU time 7.02 seconds
Started Apr 21 01:30:10 PM PDT 24
Finished Apr 21 01:30:17 PM PDT 24
Peak memory 212888 kb
Host smart-acc84412-1374-43a2-b700-4702221bc10c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667279127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.667279127
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2982902226
Short name T252
Test name
Test status
Simulation time 3313502534 ps
CPU time 61.87 seconds
Started Apr 21 01:30:07 PM PDT 24
Finished Apr 21 01:31:09 PM PDT 24
Peak memory 273536 kb
Host smart-67999b22-87fb-49ce-978a-0b3d92d413d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982902226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2982902226
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.836765878
Short name T620
Test name
Test status
Simulation time 835814648 ps
CPU time 29.39 seconds
Started Apr 21 01:30:08 PM PDT 24
Finished Apr 21 01:30:37 PM PDT 24
Peak memory 250728 kb
Host smart-1c2067e5-5468-4d78-8284-ba9f59d1ffb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836765878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.836765878
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1411797308
Short name T377
Test name
Test status
Simulation time 221614464 ps
CPU time 2.81 seconds
Started Apr 21 01:30:10 PM PDT 24
Finished Apr 21 01:30:13 PM PDT 24
Peak memory 217524 kb
Host smart-530047d4-34de-4802-a331-87b7884d4dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411797308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1411797308
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2231507435
Short name T721
Test name
Test status
Simulation time 1819440066 ps
CPU time 10.83 seconds
Started Apr 21 01:30:08 PM PDT 24
Finished Apr 21 01:30:19 PM PDT 24
Peak memory 214296 kb
Host smart-79ea7e52-9bc4-4a49-86b4-11d5d496bb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231507435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2231507435
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.4119295320
Short name T62
Test name
Test status
Simulation time 217206545 ps
CPU time 37.9 seconds
Started Apr 21 01:30:15 PM PDT 24
Finished Apr 21 01:30:53 PM PDT 24
Peak memory 270044 kb
Host smart-ce97c7f7-05e0-4d48-b91e-9c982df8a64b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119295320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.4119295320
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1059510
Short name T580
Test name
Test status
Simulation time 401111482 ps
CPU time 11.36 seconds
Started Apr 21 01:30:09 PM PDT 24
Finished Apr 21 01:30:21 PM PDT 24
Peak memory 225924 kb
Host smart-9f1443d2-e6c1-4540-9b1a-34419da2f0ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1059510
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3419733690
Short name T352
Test name
Test status
Simulation time 772303378 ps
CPU time 8.42 seconds
Started Apr 21 01:30:08 PM PDT 24
Finished Apr 21 01:30:17 PM PDT 24
Peak memory 217852 kb
Host smart-f005c7a6-c9c8-4e4d-ab35-60d37c7a59af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419733690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3419733690
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.596445588
Short name T234
Test name
Test status
Simulation time 788913197 ps
CPU time 13.23 seconds
Started Apr 21 01:30:09 PM PDT 24
Finished Apr 21 01:30:22 PM PDT 24
Peak memory 217880 kb
Host smart-93d285c8-1998-416f-a616-ccc2e55f61fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596445588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.596445588
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.866227844
Short name T431
Test name
Test status
Simulation time 212726278 ps
CPU time 6.94 seconds
Started Apr 21 01:30:07 PM PDT 24
Finished Apr 21 01:30:14 PM PDT 24
Peak memory 217872 kb
Host smart-4d100e2c-38a1-4a55-bea5-ea4c30782891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866227844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.866227844
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.776640065
Short name T691
Test name
Test status
Simulation time 484377874 ps
CPU time 4.11 seconds
Started Apr 21 01:30:09 PM PDT 24
Finished Apr 21 01:30:13 PM PDT 24
Peak memory 217652 kb
Host smart-0d37c952-ccd9-46a3-898f-6bc61933fbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776640065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.776640065
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.39221192
Short name T523
Test name
Test status
Simulation time 400302711 ps
CPU time 23.05 seconds
Started Apr 21 01:30:10 PM PDT 24
Finished Apr 21 01:30:33 PM PDT 24
Peak memory 250764 kb
Host smart-aea3fc99-10cc-4443-9846-877c06b0a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39221192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.39221192
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3928177757
Short name T107
Test name
Test status
Simulation time 338457541 ps
CPU time 7.16 seconds
Started Apr 21 01:30:06 PM PDT 24
Finished Apr 21 01:30:14 PM PDT 24
Peak memory 246324 kb
Host smart-22e504ed-5b5e-4d2b-ae71-7f36e18946ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928177757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3928177757
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.429640626
Short name T310
Test name
Test status
Simulation time 10339951564 ps
CPU time 66.35 seconds
Started Apr 21 01:30:11 PM PDT 24
Finished Apr 21 01:31:18 PM PDT 24
Peak memory 251204 kb
Host smart-f9c675e8-46a0-4fc3-9b97-980ea5243ff7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429640626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.429640626
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3980335031
Short name T497
Test name
Test status
Simulation time 13155019 ps
CPU time 0.94 seconds
Started Apr 21 01:30:06 PM PDT 24
Finished Apr 21 01:30:07 PM PDT 24
Peak memory 208512 kb
Host smart-ca2f924f-1865-4aac-8538-7a7117d7b891
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980335031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3980335031
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1048973058
Short name T302
Test name
Test status
Simulation time 804714456 ps
CPU time 20.15 seconds
Started Apr 21 01:32:27 PM PDT 24
Finished Apr 21 01:32:47 PM PDT 24
Peak memory 217860 kb
Host smart-99316529-10a1-4b98-9337-445ad613068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048973058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1048973058
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1859744385
Short name T531
Test name
Test status
Simulation time 125129598 ps
CPU time 1.51 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 01:32:34 PM PDT 24
Peak memory 209460 kb
Host smart-9201dbf0-534d-4a78-9b31-cfe3d94ca46c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859744385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1859744385
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2686765579
Short name T855
Test name
Test status
Simulation time 359147946 ps
CPU time 1.97 seconds
Started Apr 21 01:32:24 PM PDT 24
Finished Apr 21 01:32:26 PM PDT 24
Peak memory 217940 kb
Host smart-2da3f05f-a192-4346-8cc6-777b11e4228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686765579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2686765579
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2771617450
Short name T788
Test name
Test status
Simulation time 324653438 ps
CPU time 8.93 seconds
Started Apr 21 01:32:28 PM PDT 24
Finished Apr 21 01:32:37 PM PDT 24
Peak memory 217828 kb
Host smart-70bddca6-d82e-4230-b9d5-3b0f237ea249
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771617450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2771617450
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3614150220
Short name T516
Test name
Test status
Simulation time 1098099540 ps
CPU time 10.93 seconds
Started Apr 21 01:32:29 PM PDT 24
Finished Apr 21 01:32:41 PM PDT 24
Peak memory 217860 kb
Host smart-7e9829a3-b9aa-4efb-aa9c-9af97796c701
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614150220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3614150220
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3356617864
Short name T64
Test name
Test status
Simulation time 1048625318 ps
CPU time 12.87 seconds
Started Apr 21 01:32:28 PM PDT 24
Finished Apr 21 01:32:41 PM PDT 24
Peak memory 217940 kb
Host smart-8cd5f6f2-4c19-49e9-b858-44c8896ae18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356617864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3356617864
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3898831020
Short name T114
Test name
Test status
Simulation time 242165647 ps
CPU time 2.69 seconds
Started Apr 21 01:32:24 PM PDT 24
Finished Apr 21 01:32:27 PM PDT 24
Peak memory 214132 kb
Host smart-06ca7489-1ddb-4666-910f-e8a226d85eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898831020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3898831020
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.537288556
Short name T678
Test name
Test status
Simulation time 461685990 ps
CPU time 20.28 seconds
Started Apr 21 01:32:23 PM PDT 24
Finished Apr 21 01:32:43 PM PDT 24
Peak memory 246952 kb
Host smart-a66fac53-3868-4ee0-beb0-5e0127e61f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537288556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.537288556
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1275034321
Short name T444
Test name
Test status
Simulation time 50832570 ps
CPU time 6.74 seconds
Started Apr 21 01:32:22 PM PDT 24
Finished Apr 21 01:32:29 PM PDT 24
Peak memory 250848 kb
Host smart-b58b58bd-689d-4395-b829-421524040c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275034321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1275034321
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3542809829
Short name T233
Test name
Test status
Simulation time 19778941 ps
CPU time 1.2 seconds
Started Apr 21 01:32:24 PM PDT 24
Finished Apr 21 01:32:25 PM PDT 24
Peak memory 212512 kb
Host smart-44968601-2531-4228-9874-92f3f5ede502
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542809829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3542809829
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2206328031
Short name T418
Test name
Test status
Simulation time 19800254 ps
CPU time 1.18 seconds
Started Apr 21 01:32:30 PM PDT 24
Finished Apr 21 01:32:31 PM PDT 24
Peak memory 209488 kb
Host smart-c11c09a6-d36c-420a-b732-12ab6a233aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206328031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2206328031
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3825690216
Short name T633
Test name
Test status
Simulation time 921554439 ps
CPU time 11.92 seconds
Started Apr 21 01:32:30 PM PDT 24
Finished Apr 21 01:32:42 PM PDT 24
Peak memory 217728 kb
Host smart-a4e35a75-0652-435e-bfb7-ba5f92b5fd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825690216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3825690216
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.688939814
Short name T717
Test name
Test status
Simulation time 501810093 ps
CPU time 4.88 seconds
Started Apr 21 01:32:28 PM PDT 24
Finished Apr 21 01:32:33 PM PDT 24
Peak memory 217164 kb
Host smart-a844336a-448f-4eb7-ab8e-4624a436c024
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688939814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.688939814
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1132290493
Short name T615
Test name
Test status
Simulation time 24450759 ps
CPU time 1.76 seconds
Started Apr 21 01:32:29 PM PDT 24
Finished Apr 21 01:32:31 PM PDT 24
Peak memory 217836 kb
Host smart-30393146-fe13-4f64-a757-c55440c238cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132290493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1132290493
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2543826865
Short name T808
Test name
Test status
Simulation time 630161585 ps
CPU time 10.25 seconds
Started Apr 21 01:32:31 PM PDT 24
Finished Apr 21 01:32:41 PM PDT 24
Peak memory 218804 kb
Host smart-44cad593-19fe-4540-9e28-5d014c36f166
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543826865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2543826865
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4093283033
Short name T182
Test name
Test status
Simulation time 1106620637 ps
CPU time 7.14 seconds
Started Apr 21 01:32:35 PM PDT 24
Finished Apr 21 01:32:42 PM PDT 24
Peak memory 217832 kb
Host smart-bf25f530-6ca8-4f99-8d37-4fe74fbc15d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093283033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4093283033
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2642310065
Short name T858
Test name
Test status
Simulation time 1686724295 ps
CPU time 7.75 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 01:32:40 PM PDT 24
Peak memory 217876 kb
Host smart-576430f5-1b17-4bc3-a122-2fc83d8e942c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642310065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2642310065
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2703697294
Short name T668
Test name
Test status
Simulation time 38606022 ps
CPU time 1.94 seconds
Started Apr 21 01:32:26 PM PDT 24
Finished Apr 21 01:32:28 PM PDT 24
Peak memory 213784 kb
Host smart-ee6d6b62-798c-41f3-906c-25115c6df4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703697294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2703697294
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1967454161
Short name T404
Test name
Test status
Simulation time 509793291 ps
CPU time 27.74 seconds
Started Apr 21 01:32:26 PM PDT 24
Finished Apr 21 01:32:54 PM PDT 24
Peak memory 250436 kb
Host smart-b95d3353-abd7-4e9d-8552-3e0a4a8eae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967454161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1967454161
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2241700853
Short name T111
Test name
Test status
Simulation time 333566725 ps
CPU time 2.96 seconds
Started Apr 21 01:32:28 PM PDT 24
Finished Apr 21 01:32:31 PM PDT 24
Peak memory 226308 kb
Host smart-b64c5360-8ae2-446b-b488-6c48d9fd32d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241700853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2241700853
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3145186693
Short name T831
Test name
Test status
Simulation time 2063207161 ps
CPU time 35.86 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 01:33:08 PM PDT 24
Peak memory 225972 kb
Host smart-fca0cb7e-0581-4e08-aad1-4662fba6a373
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145186693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3145186693
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1256564004
Short name T166
Test name
Test status
Simulation time 102813545977 ps
CPU time 2774.81 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 02:18:47 PM PDT 24
Peak memory 914768 kb
Host smart-abfe22f0-071e-4bbe-bc54-195750c26a78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1256564004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1256564004
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1138390765
Short name T459
Test name
Test status
Simulation time 12713837 ps
CPU time 0.93 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 01:32:33 PM PDT 24
Peak memory 208524 kb
Host smart-3d58e639-3ff9-4dcc-a78a-a8214f9de6d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138390765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1138390765
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1680586650
Short name T320
Test name
Test status
Simulation time 24234485 ps
CPU time 1.27 seconds
Started Apr 21 01:32:37 PM PDT 24
Finished Apr 21 01:32:39 PM PDT 24
Peak memory 209408 kb
Host smart-a8069045-fe77-4d50-80bf-900b3411ed9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680586650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1680586650
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1937805729
Short name T482
Test name
Test status
Simulation time 1150973978 ps
CPU time 14.54 seconds
Started Apr 21 01:32:34 PM PDT 24
Finished Apr 21 01:32:49 PM PDT 24
Peak memory 217844 kb
Host smart-5409b66e-263d-4eed-80cc-c68ed762a3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937805729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1937805729
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1576052925
Short name T315
Test name
Test status
Simulation time 74435248 ps
CPU time 1.64 seconds
Started Apr 21 01:32:34 PM PDT 24
Finished Apr 21 01:32:36 PM PDT 24
Peak memory 216776 kb
Host smart-ec8708f4-640d-4965-a9ef-9c14a4dc46e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576052925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1576052925
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2861939455
Short name T452
Test name
Test status
Simulation time 67439183 ps
CPU time 1.47 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 01:32:34 PM PDT 24
Peak memory 217804 kb
Host smart-a4311f53-338d-4fe6-86ee-dc33baaa9735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861939455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2861939455
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3315187336
Short name T449
Test name
Test status
Simulation time 727061640 ps
CPU time 12.09 seconds
Started Apr 21 01:32:35 PM PDT 24
Finished Apr 21 01:32:47 PM PDT 24
Peak memory 218224 kb
Host smart-04dc740b-b434-45f1-a264-689308cb25bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315187336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3315187336
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1946961834
Short name T331
Test name
Test status
Simulation time 901895349 ps
CPU time 7.89 seconds
Started Apr 21 01:32:34 PM PDT 24
Finished Apr 21 01:32:42 PM PDT 24
Peak memory 217860 kb
Host smart-d351f753-aeec-43e9-85b6-818235f9c1db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946961834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1946961834
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3011052626
Short name T110
Test name
Test status
Simulation time 321886886 ps
CPU time 6.55 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 01:32:39 PM PDT 24
Peak memory 218152 kb
Host smart-49784497-0e29-4e49-9f9e-d565cd8c637f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011052626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3011052626
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1795489807
Short name T485
Test name
Test status
Simulation time 1935368599 ps
CPU time 9.92 seconds
Started Apr 21 01:32:33 PM PDT 24
Finished Apr 21 01:32:43 PM PDT 24
Peak memory 217936 kb
Host smart-e639f9ed-1a15-423a-a028-b9cb5dfcd031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795489807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1795489807
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2939412409
Short name T768
Test name
Test status
Simulation time 80904681 ps
CPU time 1.75 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 01:32:34 PM PDT 24
Peak memory 213740 kb
Host smart-7f7191ad-7c0b-4929-804e-3ec524434705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939412409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2939412409
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2296562384
Short name T317
Test name
Test status
Simulation time 924419094 ps
CPU time 19.56 seconds
Started Apr 21 01:32:34 PM PDT 24
Finished Apr 21 01:32:54 PM PDT 24
Peak memory 250848 kb
Host smart-fa33e57c-8a4a-4e21-8858-13a6b0c76efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296562384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2296562384
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4258743570
Short name T542
Test name
Test status
Simulation time 358783494 ps
CPU time 10.66 seconds
Started Apr 21 01:32:32 PM PDT 24
Finished Apr 21 01:32:43 PM PDT 24
Peak memory 248472 kb
Host smart-b20eff1e-2858-468f-90c3-157ca5e67ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258743570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4258743570
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3970540567
Short name T739
Test name
Test status
Simulation time 5618624203 ps
CPU time 131.83 seconds
Started Apr 21 01:32:36 PM PDT 24
Finished Apr 21 01:34:48 PM PDT 24
Peak memory 267336 kb
Host smart-76c70b48-4133-4e2d-815a-d9c28e28be99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970540567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3970540567
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.513682118
Short name T600
Test name
Test status
Simulation time 71307047 ps
CPU time 0.78 seconds
Started Apr 21 01:32:36 PM PDT 24
Finished Apr 21 01:32:37 PM PDT 24
Peak memory 208344 kb
Host smart-096617d6-9341-4e62-af0b-76b9c4d0e835
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513682118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.513682118
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1942245984
Short name T318
Test name
Test status
Simulation time 264851048 ps
CPU time 0.86 seconds
Started Apr 21 01:32:47 PM PDT 24
Finished Apr 21 01:32:48 PM PDT 24
Peak memory 209444 kb
Host smart-943d42e7-8c04-407a-98e9-724725032c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942245984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1942245984
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.4256901287
Short name T841
Test name
Test status
Simulation time 308932286 ps
CPU time 8.8 seconds
Started Apr 21 01:32:37 PM PDT 24
Finished Apr 21 01:32:46 PM PDT 24
Peak memory 217792 kb
Host smart-68234c60-f18d-42cd-84e4-d745556a0145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256901287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.4256901287
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3993922229
Short name T190
Test name
Test status
Simulation time 278172017 ps
CPU time 4.08 seconds
Started Apr 21 01:32:41 PM PDT 24
Finished Apr 21 01:32:45 PM PDT 24
Peak memory 209432 kb
Host smart-989f4de3-aec3-4ac1-8f8d-dab26e3486ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993922229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3993922229
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3430406485
Short name T251
Test name
Test status
Simulation time 72139725 ps
CPU time 1.64 seconds
Started Apr 21 01:32:38 PM PDT 24
Finished Apr 21 01:32:39 PM PDT 24
Peak memory 217828 kb
Host smart-e319287c-3066-426e-8d39-09413fd2190d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430406485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3430406485
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2250773834
Short name T528
Test name
Test status
Simulation time 587353558 ps
CPU time 14.84 seconds
Started Apr 21 01:32:42 PM PDT 24
Finished Apr 21 01:32:57 PM PDT 24
Peak memory 219016 kb
Host smart-9ae267ed-c1a6-4ba2-bdec-4ce8b336acc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250773834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2250773834
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1565430380
Short name T608
Test name
Test status
Simulation time 1429536807 ps
CPU time 9.85 seconds
Started Apr 21 01:32:41 PM PDT 24
Finished Apr 21 01:32:52 PM PDT 24
Peak memory 217872 kb
Host smart-d03fe3bf-3bd6-4f8d-9f07-3dd9ed8dfbc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565430380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1565430380
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2365623187
Short name T661
Test name
Test status
Simulation time 460338697 ps
CPU time 8.94 seconds
Started Apr 21 01:32:40 PM PDT 24
Finished Apr 21 01:32:49 PM PDT 24
Peak memory 217812 kb
Host smart-651d23d3-450c-4737-af9e-69caeebd5e79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365623187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2365623187
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.619014380
Short name T275
Test name
Test status
Simulation time 622785080 ps
CPU time 8.12 seconds
Started Apr 21 01:32:41 PM PDT 24
Finished Apr 21 01:32:50 PM PDT 24
Peak memory 224724 kb
Host smart-3cc51875-7c77-4d40-a996-92afa814fc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619014380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.619014380
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.812578318
Short name T488
Test name
Test status
Simulation time 89252653 ps
CPU time 3.32 seconds
Started Apr 21 01:32:37 PM PDT 24
Finished Apr 21 01:32:40 PM PDT 24
Peak memory 217644 kb
Host smart-69b6a3b9-4cad-48ea-b59d-5c354c58c7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812578318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.812578318
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3560388857
Short name T617
Test name
Test status
Simulation time 355179158 ps
CPU time 29.06 seconds
Started Apr 21 01:32:36 PM PDT 24
Finished Apr 21 01:33:05 PM PDT 24
Peak memory 250760 kb
Host smart-83a4e3db-ce2f-486e-aba8-aeb8dc78fc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560388857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3560388857
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1485911075
Short name T280
Test name
Test status
Simulation time 387531187 ps
CPU time 7.71 seconds
Started Apr 21 01:32:37 PM PDT 24
Finished Apr 21 01:32:45 PM PDT 24
Peak memory 250720 kb
Host smart-9e12b56d-233e-47d5-a740-a5419c1834d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485911075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1485911075
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2160656621
Short name T348
Test name
Test status
Simulation time 9498483329 ps
CPU time 81.36 seconds
Started Apr 21 01:32:44 PM PDT 24
Finished Apr 21 01:34:06 PM PDT 24
Peak memory 274440 kb
Host smart-410b2afe-a77f-4a9c-996d-73daa50c8622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160656621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2160656621
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.666981614
Short name T775
Test name
Test status
Simulation time 11961493 ps
CPU time 1.12 seconds
Started Apr 21 01:32:38 PM PDT 24
Finished Apr 21 01:32:39 PM PDT 24
Peak memory 211556 kb
Host smart-6861f78f-d37d-47e9-b75b-364d60d89ba1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666981614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.666981614
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3718047673
Short name T239
Test name
Test status
Simulation time 23787818 ps
CPU time 0.99 seconds
Started Apr 21 01:32:48 PM PDT 24
Finished Apr 21 01:32:50 PM PDT 24
Peak memory 209400 kb
Host smart-187f3f11-3e6a-493f-a423-e46a24e992db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718047673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3718047673
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.847993610
Short name T327
Test name
Test status
Simulation time 244935857 ps
CPU time 9.12 seconds
Started Apr 21 01:32:49 PM PDT 24
Finished Apr 21 01:32:58 PM PDT 24
Peak memory 225972 kb
Host smart-116c588b-0071-402b-890a-bb4b90bfbf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847993610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.847993610
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.80234377
Short name T518
Test name
Test status
Simulation time 1047717236 ps
CPU time 4.96 seconds
Started Apr 21 01:32:45 PM PDT 24
Finished Apr 21 01:32:50 PM PDT 24
Peak memory 209404 kb
Host smart-2ddbf1e3-e84c-4be7-8794-7f2c0a607fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80234377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.80234377
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3135988754
Short name T729
Test name
Test status
Simulation time 85621014 ps
CPU time 1.5 seconds
Started Apr 21 01:32:45 PM PDT 24
Finished Apr 21 01:32:47 PM PDT 24
Peak memory 217924 kb
Host smart-0cec03dc-2437-4152-b415-ca955f27a369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135988754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3135988754
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.4105372754
Short name T355
Test name
Test status
Simulation time 4947818822 ps
CPU time 18.24 seconds
Started Apr 21 01:32:48 PM PDT 24
Finished Apr 21 01:33:07 PM PDT 24
Peak memory 219180 kb
Host smart-f1c4bde4-8e6e-41a7-97a6-392d6ee396a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105372754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4105372754
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2430070114
Short name T570
Test name
Test status
Simulation time 631495227 ps
CPU time 12.17 seconds
Started Apr 21 01:32:49 PM PDT 24
Finished Apr 21 01:33:02 PM PDT 24
Peak memory 217816 kb
Host smart-85d74e7f-4ee6-415e-87e5-f3a82cd6c0d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430070114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2430070114
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2247038373
Short name T536
Test name
Test status
Simulation time 1499604163 ps
CPU time 9.19 seconds
Started Apr 21 01:32:49 PM PDT 24
Finished Apr 21 01:32:58 PM PDT 24
Peak memory 217860 kb
Host smart-60727e07-f0b4-4cde-a5a1-6e3da711d62c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247038373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2247038373
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.988844857
Short name T635
Test name
Test status
Simulation time 633412326 ps
CPU time 8.72 seconds
Started Apr 21 01:32:44 PM PDT 24
Finished Apr 21 01:32:53 PM PDT 24
Peak memory 225204 kb
Host smart-96e20a4d-392e-498b-8112-382df893a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988844857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.988844857
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.979340541
Short name T574
Test name
Test status
Simulation time 30840246 ps
CPU time 1.74 seconds
Started Apr 21 01:32:46 PM PDT 24
Finished Apr 21 01:32:48 PM PDT 24
Peak memory 217640 kb
Host smart-4296ab15-6df0-45af-8935-d57a85d26273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979340541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.979340541
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1973670504
Short name T347
Test name
Test status
Simulation time 251300154 ps
CPU time 28.8 seconds
Started Apr 21 01:32:45 PM PDT 24
Finished Apr 21 01:33:14 PM PDT 24
Peak memory 248764 kb
Host smart-9aa92296-083c-4c89-94e0-3cab72cbf927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973670504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1973670504
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2291399850
Short name T572
Test name
Test status
Simulation time 168615897 ps
CPU time 8.43 seconds
Started Apr 21 01:32:47 PM PDT 24
Finished Apr 21 01:32:56 PM PDT 24
Peak memory 248720 kb
Host smart-70245260-5a6a-4044-9d2a-638e2e159038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291399850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2291399850
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3567485523
Short name T716
Test name
Test status
Simulation time 21101916870 ps
CPU time 98.88 seconds
Started Apr 21 01:32:49 PM PDT 24
Finished Apr 21 01:34:28 PM PDT 24
Peak memory 283732 kb
Host smart-70b76dd5-d4b1-481e-a31c-464106b59bbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567485523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3567485523
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1486949291
Short name T287
Test name
Test status
Simulation time 13950295 ps
CPU time 0.95 seconds
Started Apr 21 01:32:45 PM PDT 24
Finished Apr 21 01:32:46 PM PDT 24
Peak memory 211456 kb
Host smart-e1a9139a-689d-4cb5-8433-530ab6774b16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486949291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1486949291
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2831615642
Short name T821
Test name
Test status
Simulation time 63390347 ps
CPU time 0.86 seconds
Started Apr 21 01:32:52 PM PDT 24
Finished Apr 21 01:32:53 PM PDT 24
Peak memory 209444 kb
Host smart-bf02f6c4-c04b-4434-adc3-f563f89560e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831615642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2831615642
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3849923727
Short name T553
Test name
Test status
Simulation time 474978170 ps
CPU time 10.77 seconds
Started Apr 21 01:32:51 PM PDT 24
Finished Apr 21 01:33:02 PM PDT 24
Peak memory 217856 kb
Host smart-619d43ae-39c3-4175-b0a9-97793f12ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849923727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3849923727
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2255255585
Short name T772
Test name
Test status
Simulation time 279567661 ps
CPU time 6.48 seconds
Started Apr 21 01:32:50 PM PDT 24
Finished Apr 21 01:32:57 PM PDT 24
Peak memory 216856 kb
Host smart-046bb536-1ef9-49b2-994e-939ac20ea7e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255255585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2255255585
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1457915856
Short name T687
Test name
Test status
Simulation time 116913442 ps
CPU time 3.51 seconds
Started Apr 21 01:32:52 PM PDT 24
Finished Apr 21 01:32:56 PM PDT 24
Peak memory 217836 kb
Host smart-990e0e03-a16d-49d4-ae75-f44e55b70e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457915856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1457915856
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2477710450
Short name T264
Test name
Test status
Simulation time 630406666 ps
CPU time 15.61 seconds
Started Apr 21 01:32:54 PM PDT 24
Finished Apr 21 01:33:10 PM PDT 24
Peak memory 225912 kb
Host smart-a81ddb5a-a395-4109-8344-8ea6ce63f016
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477710450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2477710450
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.758848118
Short name T216
Test name
Test status
Simulation time 2711749236 ps
CPU time 10.97 seconds
Started Apr 21 01:32:56 PM PDT 24
Finished Apr 21 01:33:07 PM PDT 24
Peak memory 218000 kb
Host smart-cab6755e-9ebe-4a11-a045-e140bcf9de28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758848118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.758848118
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1270104978
Short name T428
Test name
Test status
Simulation time 1042938559 ps
CPU time 8.74 seconds
Started Apr 21 01:32:52 PM PDT 24
Finished Apr 21 01:33:01 PM PDT 24
Peak memory 217804 kb
Host smart-cd21196c-d95b-44a8-9512-a8ab1316c34b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270104978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1270104978
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1555101641
Short name T549
Test name
Test status
Simulation time 711358034 ps
CPU time 8.18 seconds
Started Apr 21 01:32:51 PM PDT 24
Finished Apr 21 01:33:00 PM PDT 24
Peak memory 217892 kb
Host smart-09d6dc7e-f83c-4f1e-8064-3d80d6ec940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555101641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1555101641
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2443286320
Short name T414
Test name
Test status
Simulation time 40268435 ps
CPU time 2.32 seconds
Started Apr 21 01:32:48 PM PDT 24
Finished Apr 21 01:32:51 PM PDT 24
Peak memory 213944 kb
Host smart-3e3c4211-3b90-4a34-87f7-b9aa2963a465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443286320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2443286320
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2625885035
Short name T771
Test name
Test status
Simulation time 1680793532 ps
CPU time 27.4 seconds
Started Apr 21 01:32:50 PM PDT 24
Finished Apr 21 01:33:18 PM PDT 24
Peak memory 248716 kb
Host smart-835d7c23-5974-4c9a-90c4-4adb59c48e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625885035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2625885035
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.946912213
Short name T545
Test name
Test status
Simulation time 53325787 ps
CPU time 2.59 seconds
Started Apr 21 01:32:52 PM PDT 24
Finished Apr 21 01:32:55 PM PDT 24
Peak memory 222176 kb
Host smart-474afa79-4951-49df-b673-c0152f24e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946912213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.946912213
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3534064460
Short name T494
Test name
Test status
Simulation time 15487131324 ps
CPU time 276.12 seconds
Started Apr 21 01:32:51 PM PDT 24
Finished Apr 21 01:37:27 PM PDT 24
Peak memory 251000 kb
Host smart-24819ea8-0da6-4774-81e8-e6df2605c43b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534064460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3534064460
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3646984596
Short name T282
Test name
Test status
Simulation time 41355330 ps
CPU time 0.95 seconds
Started Apr 21 01:32:48 PM PDT 24
Finished Apr 21 01:32:50 PM PDT 24
Peak memory 211424 kb
Host smart-d8bf69c3-47a8-4d68-b661-90681a422b65
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646984596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3646984596
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2454085780
Short name T484
Test name
Test status
Simulation time 27878452 ps
CPU time 1.01 seconds
Started Apr 21 01:32:57 PM PDT 24
Finished Apr 21 01:32:58 PM PDT 24
Peak memory 209448 kb
Host smart-b1b9f9a0-a5c8-49b9-84b2-eaab7be2ffa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454085780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2454085780
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3671623730
Short name T250
Test name
Test status
Simulation time 391193435 ps
CPU time 16.1 seconds
Started Apr 21 01:32:58 PM PDT 24
Finished Apr 21 01:33:14 PM PDT 24
Peak memory 217836 kb
Host smart-d08150d5-0519-481f-86fc-4ad905137f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671623730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3671623730
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.255439193
Short name T753
Test name
Test status
Simulation time 299195731 ps
CPU time 7.88 seconds
Started Apr 21 01:32:53 PM PDT 24
Finished Apr 21 01:33:01 PM PDT 24
Peak memory 209440 kb
Host smart-4584ad7f-5aac-49d9-aa4e-24d61e9eb298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255439193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.255439193
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2809765295
Short name T486
Test name
Test status
Simulation time 136926382 ps
CPU time 2.44 seconds
Started Apr 21 01:32:57 PM PDT 24
Finished Apr 21 01:33:00 PM PDT 24
Peak memory 217828 kb
Host smart-7b7e9d1e-4dda-4b12-a747-c314a99dfcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809765295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2809765295
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3142569824
Short name T596
Test name
Test status
Simulation time 1198804826 ps
CPU time 10.38 seconds
Started Apr 21 01:32:54 PM PDT 24
Finished Apr 21 01:33:05 PM PDT 24
Peak memory 225972 kb
Host smart-7a44609d-7a2a-4c8e-894d-3cf8abaccca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142569824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3142569824
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2413100669
Short name T232
Test name
Test status
Simulation time 581721021 ps
CPU time 8.21 seconds
Started Apr 21 01:32:59 PM PDT 24
Finished Apr 21 01:33:07 PM PDT 24
Peak memory 217808 kb
Host smart-ae4e350d-60ea-424d-b411-05b3719f02ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413100669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2413100669
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3004665496
Short name T290
Test name
Test status
Simulation time 1250536428 ps
CPU time 9.19 seconds
Started Apr 21 01:32:58 PM PDT 24
Finished Apr 21 01:33:08 PM PDT 24
Peak memory 217808 kb
Host smart-468729c8-a896-4821-9179-5927b4828aeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004665496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3004665496
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3685696089
Short name T379
Test name
Test status
Simulation time 832661670 ps
CPU time 9.25 seconds
Started Apr 21 01:32:53 PM PDT 24
Finished Apr 21 01:33:03 PM PDT 24
Peak memory 224620 kb
Host smart-dcdac49c-ca23-4260-b8e0-29eb5ad08862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685696089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3685696089
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.899337518
Short name T308
Test name
Test status
Simulation time 81696958 ps
CPU time 1.56 seconds
Started Apr 21 01:32:53 PM PDT 24
Finished Apr 21 01:32:55 PM PDT 24
Peak memory 213380 kb
Host smart-f1467c1a-c169-4b7a-b424-f5bc8542d23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899337518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.899337518
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2553083784
Short name T709
Test name
Test status
Simulation time 759219141 ps
CPU time 15.48 seconds
Started Apr 21 01:32:55 PM PDT 24
Finished Apr 21 01:33:11 PM PDT 24
Peak memory 250720 kb
Host smart-bae01f18-9daf-47fe-b5f1-ca187429fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553083784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2553083784
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.993665607
Short name T563
Test name
Test status
Simulation time 69221436 ps
CPU time 2.86 seconds
Started Apr 21 01:32:52 PM PDT 24
Finished Apr 21 01:32:56 PM PDT 24
Peak memory 221868 kb
Host smart-03be1376-dc13-4b97-ac87-914ed06a95e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993665607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.993665607
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2591312544
Short name T505
Test name
Test status
Simulation time 15855724283 ps
CPU time 232.1 seconds
Started Apr 21 01:32:58 PM PDT 24
Finished Apr 21 01:36:50 PM PDT 24
Peak memory 266672 kb
Host smart-724133bd-af21-408f-90fe-325c990cdba9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591312544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2591312544
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2114960063
Short name T156
Test name
Test status
Simulation time 20432884654 ps
CPU time 707.12 seconds
Started Apr 21 01:33:02 PM PDT 24
Finished Apr 21 01:44:50 PM PDT 24
Peak memory 283764 kb
Host smart-a1083976-848f-4a12-b6ce-51846741a43b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2114960063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2114960063
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4140159419
Short name T547
Test name
Test status
Simulation time 18659771 ps
CPU time 1.06 seconds
Started Apr 21 01:32:55 PM PDT 24
Finished Apr 21 01:32:56 PM PDT 24
Peak memory 208484 kb
Host smart-824a0fb6-b4c9-4c2e-9562-7b6c88a9e468
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140159419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4140159419
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.190616106
Short name T747
Test name
Test status
Simulation time 16461165 ps
CPU time 0.83 seconds
Started Apr 21 01:33:02 PM PDT 24
Finished Apr 21 01:33:04 PM PDT 24
Peak memory 209440 kb
Host smart-ee5a94a7-5e6d-4395-b7d8-5b39d9299509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190616106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.190616106
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.23557671
Short name T689
Test name
Test status
Simulation time 2333399360 ps
CPU time 24.34 seconds
Started Apr 21 01:33:02 PM PDT 24
Finished Apr 21 01:33:26 PM PDT 24
Peak memory 217988 kb
Host smart-f952f2b5-2ea5-4c57-b5bd-2350f8269f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23557671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.23557671
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1828235013
Short name T630
Test name
Test status
Simulation time 345241024 ps
CPU time 5.11 seconds
Started Apr 21 01:33:02 PM PDT 24
Finished Apr 21 01:33:08 PM PDT 24
Peak memory 209440 kb
Host smart-0d3eb020-89bc-4dcf-98a9-3987196df90c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828235013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1828235013
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.611292743
Short name T174
Test name
Test status
Simulation time 541254440 ps
CPU time 3.15 seconds
Started Apr 21 01:32:58 PM PDT 24
Finished Apr 21 01:33:01 PM PDT 24
Peak memory 217868 kb
Host smart-effa74ee-0634-4c58-9382-5aeaec9c5821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611292743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.611292743
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1128717246
Short name T719
Test name
Test status
Simulation time 5759904714 ps
CPU time 13.78 seconds
Started Apr 21 01:33:02 PM PDT 24
Finished Apr 21 01:33:16 PM PDT 24
Peak memory 219992 kb
Host smart-3d3e1a20-af4b-4fb2-a7db-d018d399a5a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128717246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1128717246
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1274190330
Short name T634
Test name
Test status
Simulation time 273153013 ps
CPU time 10.13 seconds
Started Apr 21 01:33:02 PM PDT 24
Finished Apr 21 01:33:13 PM PDT 24
Peak memory 217828 kb
Host smart-4ac65729-3ba8-4ec4-b857-1fee0e438736
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274190330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1274190330
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.894916748
Short name T840
Test name
Test status
Simulation time 1285539310 ps
CPU time 7.96 seconds
Started Apr 21 01:32:59 PM PDT 24
Finished Apr 21 01:33:07 PM PDT 24
Peak memory 217940 kb
Host smart-00dc406b-6e82-4d7e-8fe5-2700313edab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894916748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.894916748
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3679408
Short name T826
Test name
Test status
Simulation time 58149602 ps
CPU time 3.28 seconds
Started Apr 21 01:32:59 PM PDT 24
Finished Apr 21 01:33:03 PM PDT 24
Peak memory 213984 kb
Host smart-8662b328-8573-4ff0-b76f-f6a1ba0e9b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3679408
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1398880300
Short name T436
Test name
Test status
Simulation time 286160379 ps
CPU time 28.78 seconds
Started Apr 21 01:32:59 PM PDT 24
Finished Apr 21 01:33:28 PM PDT 24
Peak memory 250756 kb
Host smart-993ef0af-6295-4926-a51c-f05e02d05a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398880300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1398880300
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3662370120
Short name T399
Test name
Test status
Simulation time 61870533 ps
CPU time 8.44 seconds
Started Apr 21 01:33:01 PM PDT 24
Finished Apr 21 01:33:10 PM PDT 24
Peak memory 248176 kb
Host smart-0e779511-15d2-43a5-a0e6-bc4e692af4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662370120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3662370120
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.321772150
Short name T217
Test name
Test status
Simulation time 118078596979 ps
CPU time 346.05 seconds
Started Apr 21 01:33:03 PM PDT 24
Finished Apr 21 01:38:49 PM PDT 24
Peak memory 278500 kb
Host smart-803a00f3-9e81-4ba9-b5f0-576059d36663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321772150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.321772150
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.335518743
Short name T588
Test name
Test status
Simulation time 34325740 ps
CPU time 0.81 seconds
Started Apr 21 01:32:59 PM PDT 24
Finished Apr 21 01:33:00 PM PDT 24
Peak memory 208416 kb
Host smart-a088a71d-ff11-4f13-a501-7b66bffbcbbf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335518743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.335518743
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3390681822
Short name T169
Test name
Test status
Simulation time 33277969 ps
CPU time 1 seconds
Started Apr 21 01:33:04 PM PDT 24
Finished Apr 21 01:33:05 PM PDT 24
Peak memory 209428 kb
Host smart-1a09505d-cabc-46a5-8ce9-f77bf9d7d8ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390681822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3390681822
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2764481398
Short name T699
Test name
Test status
Simulation time 1796454596 ps
CPU time 12.05 seconds
Started Apr 21 01:33:04 PM PDT 24
Finished Apr 21 01:33:17 PM PDT 24
Peak memory 217840 kb
Host smart-ac4693aa-f5f9-4596-90fd-86162538725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764481398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2764481398
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2280630703
Short name T621
Test name
Test status
Simulation time 2071147623 ps
CPU time 3.92 seconds
Started Apr 21 01:33:05 PM PDT 24
Finished Apr 21 01:33:09 PM PDT 24
Peak memory 209544 kb
Host smart-3e2abfc3-a6b8-4844-95ba-c35463e3e854
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280630703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2280630703
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3145418169
Short name T786
Test name
Test status
Simulation time 328082225 ps
CPU time 3.31 seconds
Started Apr 21 01:33:03 PM PDT 24
Finished Apr 21 01:33:06 PM PDT 24
Peak memory 217728 kb
Host smart-f28a2035-ae1a-4587-9b63-205b8d742ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145418169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3145418169
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2027859657
Short name T785
Test name
Test status
Simulation time 2005562122 ps
CPU time 10.57 seconds
Started Apr 21 01:33:05 PM PDT 24
Finished Apr 21 01:33:16 PM PDT 24
Peak memory 218484 kb
Host smart-6529ec0b-b022-4996-b277-3a9ac22f5790
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027859657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2027859657
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.944536795
Short name T117
Test name
Test status
Simulation time 434754185 ps
CPU time 14.44 seconds
Started Apr 21 01:33:05 PM PDT 24
Finished Apr 21 01:33:20 PM PDT 24
Peak memory 217864 kb
Host smart-bbb55577-62d1-4068-9b02-843a1bb2b0b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944536795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.944536795
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.476599521
Short name T391
Test name
Test status
Simulation time 1525856664 ps
CPU time 8.98 seconds
Started Apr 21 01:33:05 PM PDT 24
Finished Apr 21 01:33:14 PM PDT 24
Peak memory 217744 kb
Host smart-f39bcdc0-3f55-4c81-822c-1369d057ea7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476599521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.476599521
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2409229752
Short name T859
Test name
Test status
Simulation time 310062319 ps
CPU time 11.66 seconds
Started Apr 21 01:33:04 PM PDT 24
Finished Apr 21 01:33:16 PM PDT 24
Peak memory 217928 kb
Host smart-624e818d-898e-4a57-93e8-3a6d309630a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409229752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2409229752
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3126939455
Short name T828
Test name
Test status
Simulation time 257858655 ps
CPU time 3.08 seconds
Started Apr 21 01:33:02 PM PDT 24
Finished Apr 21 01:33:05 PM PDT 24
Peak memory 214164 kb
Host smart-45df8146-e172-43f7-9c94-c1eb6024bf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126939455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3126939455
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.125508020
Short name T578
Test name
Test status
Simulation time 232033154 ps
CPU time 20.67 seconds
Started Apr 21 01:33:01 PM PDT 24
Finished Apr 21 01:33:22 PM PDT 24
Peak memory 250820 kb
Host smart-6b948faa-a93e-445b-9800-1ee16670a3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125508020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.125508020
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3850143982
Short name T806
Test name
Test status
Simulation time 61744739 ps
CPU time 6.02 seconds
Started Apr 21 01:33:01 PM PDT 24
Finished Apr 21 01:33:07 PM PDT 24
Peak memory 250684 kb
Host smart-f74b1052-800f-496d-9d00-dac7ff740b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850143982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3850143982
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.853211477
Short name T375
Test name
Test status
Simulation time 4264532436 ps
CPU time 87.66 seconds
Started Apr 21 01:33:07 PM PDT 24
Finished Apr 21 01:34:35 PM PDT 24
Peak memory 251000 kb
Host smart-4356a689-2306-4d04-8be9-985c936578da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853211477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.853211477
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.487856504
Short name T106
Test name
Test status
Simulation time 30956032123 ps
CPU time 695.29 seconds
Started Apr 21 01:33:07 PM PDT 24
Finished Apr 21 01:44:42 PM PDT 24
Peak memory 320276 kb
Host smart-2c9be060-27c6-45de-a7a9-530b77e34366
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=487856504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.487856504
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3442673710
Short name T720
Test name
Test status
Simulation time 12795419 ps
CPU time 0.94 seconds
Started Apr 21 01:33:01 PM PDT 24
Finished Apr 21 01:33:02 PM PDT 24
Peak memory 208500 kb
Host smart-d3909bb5-cfd0-4626-b73f-95be1eaabb96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442673710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3442673710
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2103205687
Short name T74
Test name
Test status
Simulation time 28478892 ps
CPU time 1.09 seconds
Started Apr 21 01:33:16 PM PDT 24
Finished Apr 21 01:33:17 PM PDT 24
Peak memory 209384 kb
Host smart-d834602e-2501-4ea0-8067-755010cd925f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103205687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2103205687
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2631697709
Short name T44
Test name
Test status
Simulation time 347768041 ps
CPU time 13.78 seconds
Started Apr 21 01:33:12 PM PDT 24
Finished Apr 21 01:33:26 PM PDT 24
Peak memory 217884 kb
Host smart-8d6b3673-a69e-4c08-a3c8-7f4917da6785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631697709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2631697709
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3594860755
Short name T10
Test name
Test status
Simulation time 997895321 ps
CPU time 5.4 seconds
Started Apr 21 01:33:13 PM PDT 24
Finished Apr 21 01:33:18 PM PDT 24
Peak memory 217084 kb
Host smart-bae68619-b500-4b26-b807-89a63bf68c7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594860755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3594860755
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2698747512
Short name T792
Test name
Test status
Simulation time 45545881 ps
CPU time 2.61 seconds
Started Apr 21 01:33:13 PM PDT 24
Finished Apr 21 01:33:16 PM PDT 24
Peak memory 217908 kb
Host smart-a0ec7155-c39b-46e4-a924-321e828e7cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698747512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2698747512
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1885378407
Short name T27
Test name
Test status
Simulation time 1038025062 ps
CPU time 10.79 seconds
Started Apr 21 01:33:11 PM PDT 24
Finished Apr 21 01:33:22 PM PDT 24
Peak memory 217860 kb
Host smart-5caf6b41-ca0a-43fa-8ab9-98cf4c9f95f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885378407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1885378407
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1093842249
Short name T438
Test name
Test status
Simulation time 1028660114 ps
CPU time 10.17 seconds
Started Apr 21 01:33:12 PM PDT 24
Finished Apr 21 01:33:22 PM PDT 24
Peak memory 217928 kb
Host smart-c0fa7c52-aa1d-4488-94ea-467f018dac0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093842249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1093842249
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2689998947
Short name T316
Test name
Test status
Simulation time 2080748485 ps
CPU time 12.11 seconds
Started Apr 21 01:33:06 PM PDT 24
Finished Apr 21 01:33:19 PM PDT 24
Peak memory 217912 kb
Host smart-7ddb0c67-fb47-40e2-b71d-b94c1aef4264
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689998947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2689998947
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1722931157
Short name T686
Test name
Test status
Simulation time 2492157091 ps
CPU time 12.48 seconds
Started Apr 21 01:33:11 PM PDT 24
Finished Apr 21 01:33:23 PM PDT 24
Peak memory 218076 kb
Host smart-349eb5f2-b565-478c-bd01-2d4d01a624dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722931157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1722931157
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1284010687
Short name T582
Test name
Test status
Simulation time 187125796 ps
CPU time 2.19 seconds
Started Apr 21 01:33:06 PM PDT 24
Finished Apr 21 01:33:09 PM PDT 24
Peak memory 214224 kb
Host smart-e128e64d-9af5-4ef5-8eb2-2321a4959d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284010687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1284010687
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3885628991
Short name T401
Test name
Test status
Simulation time 258469382 ps
CPU time 29.82 seconds
Started Apr 21 01:33:08 PM PDT 24
Finished Apr 21 01:33:38 PM PDT 24
Peak memory 247184 kb
Host smart-7a0fa5ed-e225-4b66-9c3c-025fed7457a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885628991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3885628991
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1118962294
Short name T293
Test name
Test status
Simulation time 81574511 ps
CPU time 6.28 seconds
Started Apr 21 01:33:06 PM PDT 24
Finished Apr 21 01:33:12 PM PDT 24
Peak memory 246396 kb
Host smart-a4cb7a2f-8bd8-42eb-9e13-f5fa62bc92df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118962294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1118962294
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2813119821
Short name T609
Test name
Test status
Simulation time 41772023127 ps
CPU time 104.22 seconds
Started Apr 21 01:33:08 PM PDT 24
Finished Apr 21 01:34:52 PM PDT 24
Peak memory 250628 kb
Host smart-df6447a1-4b89-40e6-9b38-a1fc21f9c2aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813119821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2813119821
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.384542236
Short name T824
Test name
Test status
Simulation time 16804160 ps
CPU time 1.21 seconds
Started Apr 21 01:33:04 PM PDT 24
Finished Apr 21 01:33:06 PM PDT 24
Peak memory 212560 kb
Host smart-8f6bc5b3-351f-483e-b9aa-315c1b153f58
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384542236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.384542236
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.761260265
Short name T648
Test name
Test status
Simulation time 74717306 ps
CPU time 0.91 seconds
Started Apr 21 01:30:22 PM PDT 24
Finished Apr 21 01:30:23 PM PDT 24
Peak memory 209444 kb
Host smart-42ed06a6-9ea5-491d-a44b-58d753ce431f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761260265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.761260265
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3730876538
Short name T170
Test name
Test status
Simulation time 1399389950 ps
CPU time 15.09 seconds
Started Apr 21 01:30:13 PM PDT 24
Finished Apr 21 01:30:28 PM PDT 24
Peak memory 217728 kb
Host smart-64fd4770-1ccd-43c5-900a-8b140676b4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730876538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3730876538
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1002409598
Short name T5
Test name
Test status
Simulation time 126752064 ps
CPU time 1.05 seconds
Started Apr 21 01:30:20 PM PDT 24
Finished Apr 21 01:30:22 PM PDT 24
Peak memory 209460 kb
Host smart-859a52a8-3095-4b5b-b0c4-5f0fffdfce0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002409598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1002409598
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.340238694
Short name T267
Test name
Test status
Simulation time 7690513793 ps
CPU time 61.27 seconds
Started Apr 21 01:30:21 PM PDT 24
Finished Apr 21 01:31:23 PM PDT 24
Peak memory 218852 kb
Host smart-3ee02ef2-6117-43d0-b4a3-73a3934c41e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340238694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.340238694
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2177308496
Short name T519
Test name
Test status
Simulation time 175212139 ps
CPU time 2.54 seconds
Started Apr 21 01:30:18 PM PDT 24
Finished Apr 21 01:30:21 PM PDT 24
Peak memory 216996 kb
Host smart-2651d953-e7c0-4d17-8aaf-75cb40a46010
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177308496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
177308496
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2733964576
Short name T20
Test name
Test status
Simulation time 3310560631 ps
CPU time 6.25 seconds
Started Apr 21 01:30:16 PM PDT 24
Finished Apr 21 01:30:22 PM PDT 24
Peak memory 217972 kb
Host smart-45daf77b-69eb-4b75-96e9-20ddd7b2c727
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733964576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2733964576
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.839197397
Short name T72
Test name
Test status
Simulation time 3243536356 ps
CPU time 11.51 seconds
Started Apr 21 01:30:20 PM PDT 24
Finished Apr 21 01:30:32 PM PDT 24
Peak memory 213412 kb
Host smart-dd34e1ad-5126-4c2b-b551-9cba46fe1fd6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839197397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.839197397
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3457576196
Short name T457
Test name
Test status
Simulation time 4399115564 ps
CPU time 8.21 seconds
Started Apr 21 01:30:15 PM PDT 24
Finished Apr 21 01:30:24 PM PDT 24
Peak memory 213700 kb
Host smart-7f4fceda-7f9a-4688-9f70-cd098706a427
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457576196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3457576196
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3850174422
Short name T314
Test name
Test status
Simulation time 16876035464 ps
CPU time 41.1 seconds
Started Apr 21 01:30:17 PM PDT 24
Finished Apr 21 01:30:58 PM PDT 24
Peak memory 276932 kb
Host smart-95b8c8f5-78f3-4f88-b93a-188a19134d5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850174422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3850174422
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4063574197
Short name T303
Test name
Test status
Simulation time 1618584056 ps
CPU time 13.16 seconds
Started Apr 21 01:30:15 PM PDT 24
Finished Apr 21 01:30:29 PM PDT 24
Peak memory 244076 kb
Host smart-86a8c112-cec5-4404-833a-7de6b296ffcf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063574197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4063574197
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1906382574
Short name T743
Test name
Test status
Simulation time 45972027 ps
CPU time 1.58 seconds
Started Apr 21 01:30:14 PM PDT 24
Finished Apr 21 01:30:16 PM PDT 24
Peak memory 217824 kb
Host smart-06b87d6f-0eac-42e4-b429-6cf2d0068981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906382574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1906382574
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3461928059
Short name T744
Test name
Test status
Simulation time 783454170 ps
CPU time 7.91 seconds
Started Apr 21 01:30:15 PM PDT 24
Finished Apr 21 01:30:23 PM PDT 24
Peak memory 214104 kb
Host smart-11e9359b-60d1-4c24-b11b-4aedf6942f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461928059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3461928059
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1247884851
Short name T93
Test name
Test status
Simulation time 1257644348 ps
CPU time 35.12 seconds
Started Apr 21 01:30:21 PM PDT 24
Finished Apr 21 01:30:57 PM PDT 24
Peak memory 284488 kb
Host smart-452aae3f-8f08-4416-b299-4d0b133a171e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247884851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1247884851
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.395795332
Short name T236
Test name
Test status
Simulation time 1501618508 ps
CPU time 14.81 seconds
Started Apr 21 01:30:17 PM PDT 24
Finished Apr 21 01:30:33 PM PDT 24
Peak memory 218064 kb
Host smart-5b96702b-26a7-4b06-a4e1-58d06aeeb121
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395795332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.395795332
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2359181702
Short name T333
Test name
Test status
Simulation time 754867866 ps
CPU time 15.25 seconds
Started Apr 21 01:30:22 PM PDT 24
Finished Apr 21 01:30:38 PM PDT 24
Peak memory 217892 kb
Host smart-34055496-3985-4d90-8c50-8834665a5e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359181702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2359181702
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3994357045
Short name T338
Test name
Test status
Simulation time 328262602 ps
CPU time 10.89 seconds
Started Apr 21 01:30:22 PM PDT 24
Finished Apr 21 01:30:33 PM PDT 24
Peak memory 217860 kb
Host smart-f1ab9728-0f63-4c1a-9979-9d836c842b99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994357045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
994357045
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4286140924
Short name T626
Test name
Test status
Simulation time 1368743046 ps
CPU time 8.41 seconds
Started Apr 21 01:30:14 PM PDT 24
Finished Apr 21 01:30:23 PM PDT 24
Peak memory 217868 kb
Host smart-c72556c7-3cfc-4de0-9061-2af712206cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286140924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4286140924
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3827250045
Short name T432
Test name
Test status
Simulation time 15538854 ps
CPU time 1.4 seconds
Started Apr 21 01:30:13 PM PDT 24
Finished Apr 21 01:30:15 PM PDT 24
Peak memory 213256 kb
Host smart-1bda65b2-6de3-45a3-b692-aaa75d6f60bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827250045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3827250045
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.373735216
Short name T365
Test name
Test status
Simulation time 305074475 ps
CPU time 25.57 seconds
Started Apr 21 01:30:15 PM PDT 24
Finished Apr 21 01:30:41 PM PDT 24
Peak memory 250840 kb
Host smart-1ccc4eb8-c53b-4e8a-b3ae-343a632e1e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373735216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.373735216
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.372320933
Short name T734
Test name
Test status
Simulation time 46775062 ps
CPU time 2.99 seconds
Started Apr 21 01:30:12 PM PDT 24
Finished Apr 21 01:30:16 PM PDT 24
Peak memory 222144 kb
Host smart-a9fa4c38-1cbd-485a-8a7a-22cfe61a6ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372320933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.372320933
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2802899760
Short name T83
Test name
Test status
Simulation time 59362856593 ps
CPU time 473.11 seconds
Started Apr 21 01:30:22 PM PDT 24
Finished Apr 21 01:38:16 PM PDT 24
Peak memory 273660 kb
Host smart-375582c3-73d6-46f5-bfb8-c867c64571e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802899760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2802899760
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1365592245
Short name T178
Test name
Test status
Simulation time 226624173723 ps
CPU time 371.16 seconds
Started Apr 21 01:30:23 PM PDT 24
Finished Apr 21 01:36:34 PM PDT 24
Peak memory 274356 kb
Host smart-a8d6619b-dc36-4159-ad44-bbb8aa498542
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1365592245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.1365592245
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2336159772
Short name T664
Test name
Test status
Simulation time 18128022 ps
CPU time 0.79 seconds
Started Apr 21 01:30:15 PM PDT 24
Finished Apr 21 01:30:16 PM PDT 24
Peak memory 208576 kb
Host smart-0f07ffc3-d7d2-47fa-ab32-279340df873a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336159772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2336159772
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2120309557
Short name T423
Test name
Test status
Simulation time 38198550 ps
CPU time 0.9 seconds
Started Apr 21 01:33:13 PM PDT 24
Finished Apr 21 01:33:14 PM PDT 24
Peak memory 209444 kb
Host smart-43da27d9-0f26-486c-af80-3cb22bab8c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120309557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2120309557
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2340421230
Short name T512
Test name
Test status
Simulation time 1402453288 ps
CPU time 11.1 seconds
Started Apr 21 01:33:16 PM PDT 24
Finished Apr 21 01:33:27 PM PDT 24
Peak memory 225928 kb
Host smart-93105cdd-d64e-4ca3-b3d9-83d6efab6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340421230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2340421230
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1998996922
Short name T32
Test name
Test status
Simulation time 121857103 ps
CPU time 2.11 seconds
Started Apr 21 01:33:12 PM PDT 24
Finished Apr 21 01:33:14 PM PDT 24
Peak memory 216796 kb
Host smart-d11665d7-cd23-4692-9462-bac2fbb61f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998996922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1998996922
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.170549860
Short name T26
Test name
Test status
Simulation time 198167659 ps
CPU time 2.95 seconds
Started Apr 21 01:33:12 PM PDT 24
Finished Apr 21 01:33:15 PM PDT 24
Peak memory 217812 kb
Host smart-26a208a4-e4d4-48e9-bb6c-b404bdc383af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170549860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.170549860
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.901392044
Short name T534
Test name
Test status
Simulation time 636269907 ps
CPU time 7.83 seconds
Started Apr 21 01:33:11 PM PDT 24
Finished Apr 21 01:33:19 PM PDT 24
Peak memory 217860 kb
Host smart-446d5ce1-0e5f-4b4d-9adb-628e233d3b89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901392044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.901392044
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3437667076
Short name T619
Test name
Test status
Simulation time 1274341882 ps
CPU time 12.85 seconds
Started Apr 21 01:33:13 PM PDT 24
Finished Apr 21 01:33:26 PM PDT 24
Peak memory 217864 kb
Host smart-5669916e-fbf5-41c4-9834-97329296937f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437667076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3437667076
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.4203755966
Short name T244
Test name
Test status
Simulation time 2036771316 ps
CPU time 12.62 seconds
Started Apr 21 01:33:17 PM PDT 24
Finished Apr 21 01:33:30 PM PDT 24
Peak memory 217836 kb
Host smart-3b7be288-ef83-4ea7-a0c1-7fcd43dfaea2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203755966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
4203755966
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.219003563
Short name T732
Test name
Test status
Simulation time 1475401110 ps
CPU time 9.35 seconds
Started Apr 21 01:33:16 PM PDT 24
Finished Apr 21 01:33:25 PM PDT 24
Peak memory 224964 kb
Host smart-6fbed881-8f1b-4c30-a5e8-fef435221433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219003563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.219003563
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.117790598
Short name T447
Test name
Test status
Simulation time 234636628 ps
CPU time 2.58 seconds
Started Apr 21 01:33:15 PM PDT 24
Finished Apr 21 01:33:18 PM PDT 24
Peak memory 214236 kb
Host smart-62ed8cc6-9e72-424b-9a36-01de47a43b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117790598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.117790598
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1161655842
Short name T846
Test name
Test status
Simulation time 486543312 ps
CPU time 29.99 seconds
Started Apr 21 01:33:15 PM PDT 24
Finished Apr 21 01:33:45 PM PDT 24
Peak memory 250832 kb
Host smart-d8f36042-904b-4caf-8a57-82b5b8755434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161655842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1161655842
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.939202723
Short name T731
Test name
Test status
Simulation time 267801891 ps
CPU time 4.02 seconds
Started Apr 21 01:33:17 PM PDT 24
Finished Apr 21 01:33:21 PM PDT 24
Peak memory 226252 kb
Host smart-609142fc-6c19-4779-b325-0d40f3b7e07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939202723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.939202723
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1708820432
Short name T187
Test name
Test status
Simulation time 4593692960 ps
CPU time 153.78 seconds
Started Apr 21 01:33:15 PM PDT 24
Finished Apr 21 01:35:49 PM PDT 24
Peak memory 274656 kb
Host smart-88e72a93-13d8-41d7-9b20-2d0f61f4f0d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708820432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1708820432
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.807184293
Short name T605
Test name
Test status
Simulation time 14564808 ps
CPU time 0.97 seconds
Started Apr 21 01:33:11 PM PDT 24
Finished Apr 21 01:33:12 PM PDT 24
Peak memory 208568 kb
Host smart-1ab28816-4fd8-43e1-8d20-de5a4eb843e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807184293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.807184293
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.584118081
Short name T631
Test name
Test status
Simulation time 13024880 ps
CPU time 0.83 seconds
Started Apr 21 01:33:27 PM PDT 24
Finished Apr 21 01:33:28 PM PDT 24
Peak memory 209384 kb
Host smart-9fe7a3c8-ef83-42f2-9128-6743a4a5a7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584118081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.584118081
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.863133667
Short name T851
Test name
Test status
Simulation time 1205500312 ps
CPU time 11.19 seconds
Started Apr 21 01:33:15 PM PDT 24
Finished Apr 21 01:33:27 PM PDT 24
Peak memory 225948 kb
Host smart-b4a044e8-f844-40da-81c8-9ff445799a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863133667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.863133667
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2820160498
Short name T465
Test name
Test status
Simulation time 1096616530 ps
CPU time 8.68 seconds
Started Apr 21 01:33:16 PM PDT 24
Finished Apr 21 01:33:25 PM PDT 24
Peak memory 209528 kb
Host smart-c8d3e4df-f38f-4d8d-b36d-9dbc9f074117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820160498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2820160498
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.806028692
Short name T723
Test name
Test status
Simulation time 41195644 ps
CPU time 2.71 seconds
Started Apr 21 01:33:16 PM PDT 24
Finished Apr 21 01:33:19 PM PDT 24
Peak memory 217856 kb
Host smart-244a676e-d74d-47a7-b257-daed87593abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806028692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.806028692
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4161950210
Short name T226
Test name
Test status
Simulation time 338581422 ps
CPU time 15.96 seconds
Started Apr 21 01:33:27 PM PDT 24
Finished Apr 21 01:33:43 PM PDT 24
Peak memory 218760 kb
Host smart-e088a01f-4536-4194-b528-b7cc96ca600f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161950210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4161950210
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1039684136
Short name T38
Test name
Test status
Simulation time 1120548947 ps
CPU time 11.49 seconds
Started Apr 21 01:33:28 PM PDT 24
Finished Apr 21 01:33:40 PM PDT 24
Peak memory 217884 kb
Host smart-954b2856-827b-413b-9e32-0cf89faac251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039684136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1039684136
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1160801657
Short name T242
Test name
Test status
Simulation time 2851267664 ps
CPU time 7.28 seconds
Started Apr 21 01:33:21 PM PDT 24
Finished Apr 21 01:33:28 PM PDT 24
Peak memory 217932 kb
Host smart-1588b96f-4536-4660-88b0-95daf226ab75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160801657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1160801657
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2999358573
Short name T796
Test name
Test status
Simulation time 1100610107 ps
CPU time 7.86 seconds
Started Apr 21 01:33:16 PM PDT 24
Finished Apr 21 01:33:24 PM PDT 24
Peak memory 217956 kb
Host smart-d4a9c608-0978-4ef0-9dd0-f5006dfaded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999358573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2999358573
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.136662248
Short name T172
Test name
Test status
Simulation time 19912722 ps
CPU time 1.63 seconds
Started Apr 21 01:33:16 PM PDT 24
Finished Apr 21 01:33:18 PM PDT 24
Peak memory 213384 kb
Host smart-fcd215da-0395-4f7b-a9a0-d0fd32333193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136662248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.136662248
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1078834366
Short name T398
Test name
Test status
Simulation time 565322790 ps
CPU time 29.15 seconds
Started Apr 21 01:33:14 PM PDT 24
Finished Apr 21 01:33:44 PM PDT 24
Peak memory 250792 kb
Host smart-64b1bc9e-4b3d-4480-9b8a-60b4e417ac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078834366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1078834366
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3621209312
Short name T696
Test name
Test status
Simulation time 79849123 ps
CPU time 7.87 seconds
Started Apr 21 01:33:15 PM PDT 24
Finished Apr 21 01:33:23 PM PDT 24
Peak memory 245716 kb
Host smart-ad347fc8-2e22-407e-ae05-1f2fa1fef7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621209312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3621209312
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3963300303
Short name T575
Test name
Test status
Simulation time 3061507365 ps
CPU time 16.16 seconds
Started Apr 21 01:33:21 PM PDT 24
Finished Apr 21 01:33:37 PM PDT 24
Peak memory 226040 kb
Host smart-254226ca-1884-437d-965a-219e4aa4c7e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963300303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3963300303
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3630250147
Short name T161
Test name
Test status
Simulation time 40404940264 ps
CPU time 1349.85 seconds
Started Apr 21 01:33:20 PM PDT 24
Finished Apr 21 01:55:50 PM PDT 24
Peak memory 438452 kb
Host smart-eadc34fa-be71-419b-867e-fa9b61452245
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3630250147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.3630250147
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1262529973
Short name T289
Test name
Test status
Simulation time 28338173 ps
CPU time 0.87 seconds
Started Apr 21 01:33:16 PM PDT 24
Finished Apr 21 01:33:18 PM PDT 24
Peak memory 208668 kb
Host smart-24a978a1-cee1-4749-be10-4851cd7c9ca3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262529973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1262529973
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1744049783
Short name T364
Test name
Test status
Simulation time 34559275 ps
CPU time 0.9 seconds
Started Apr 21 01:33:30 PM PDT 24
Finished Apr 21 01:33:31 PM PDT 24
Peak memory 209404 kb
Host smart-1b3e1a9c-94f8-4966-bad5-3e2d269277c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744049783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1744049783
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3821416003
Short name T54
Test name
Test status
Simulation time 647803981 ps
CPU time 10.5 seconds
Started Apr 21 01:33:28 PM PDT 24
Finished Apr 21 01:33:38 PM PDT 24
Peak memory 225960 kb
Host smart-00763533-811c-41c6-a66b-5ed9d227ae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821416003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3821416003
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2876931155
Short name T816
Test name
Test status
Simulation time 2333889539 ps
CPU time 6.36 seconds
Started Apr 21 01:33:25 PM PDT 24
Finished Apr 21 01:33:32 PM PDT 24
Peak memory 216896 kb
Host smart-a6d4f28f-deb4-49d6-bcae-e74cb87a3783
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876931155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2876931155
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.755368071
Short name T567
Test name
Test status
Simulation time 71277037 ps
CPU time 2.83 seconds
Started Apr 21 01:33:23 PM PDT 24
Finished Apr 21 01:33:26 PM PDT 24
Peak memory 217876 kb
Host smart-4c77c049-83ce-449a-bc96-e3b79e24ff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755368071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.755368071
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3850419059
Short name T701
Test name
Test status
Simulation time 1195736541 ps
CPU time 13.49 seconds
Started Apr 21 01:33:22 PM PDT 24
Finished Apr 21 01:33:36 PM PDT 24
Peak memory 218040 kb
Host smart-6bcf7438-6f62-44a6-bc9d-3dcf9053a604
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850419059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3850419059
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2719922264
Short name T448
Test name
Test status
Simulation time 1190953395 ps
CPU time 13.9 seconds
Started Apr 21 01:33:30 PM PDT 24
Finished Apr 21 01:33:44 PM PDT 24
Peak memory 217864 kb
Host smart-c9337942-3ed9-44bf-8998-b30ff8cb02ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719922264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2719922264
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1069405683
Short name T695
Test name
Test status
Simulation time 1432816420 ps
CPU time 13.46 seconds
Started Apr 21 01:33:28 PM PDT 24
Finished Apr 21 01:33:42 PM PDT 24
Peak memory 217732 kb
Host smart-642e439c-95a4-4d4c-86d2-e5a15dd1d591
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069405683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1069405683
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.112167568
Short name T59
Test name
Test status
Simulation time 1117447023 ps
CPU time 9.55 seconds
Started Apr 21 01:33:27 PM PDT 24
Finished Apr 21 01:33:37 PM PDT 24
Peak memory 217920 kb
Host smart-af680f2d-9ca6-496d-a71b-beabb66df692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112167568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.112167568
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3648800171
Short name T566
Test name
Test status
Simulation time 226776064 ps
CPU time 3.92 seconds
Started Apr 21 01:33:28 PM PDT 24
Finished Apr 21 01:33:33 PM PDT 24
Peak memory 217652 kb
Host smart-7f0bc3aa-a382-4f75-9b2f-aa4099782d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648800171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3648800171
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2388367136
Short name T109
Test name
Test status
Simulation time 264929487 ps
CPU time 23.43 seconds
Started Apr 21 01:33:27 PM PDT 24
Finished Apr 21 01:33:50 PM PDT 24
Peak memory 250836 kb
Host smart-03c5c720-8e1c-4dff-9540-8b1a73b6532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388367136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2388367136
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1563516885
Short name T326
Test name
Test status
Simulation time 83636618 ps
CPU time 7.63 seconds
Started Apr 21 01:33:28 PM PDT 24
Finished Apr 21 01:33:36 PM PDT 24
Peak memory 249896 kb
Host smart-552e7e34-4acd-46a6-acaf-dab298ae70c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563516885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1563516885
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3382743831
Short name T108
Test name
Test status
Simulation time 242709050502 ps
CPU time 277.98 seconds
Started Apr 21 01:33:26 PM PDT 24
Finished Apr 21 01:38:04 PM PDT 24
Peak memory 250960 kb
Host smart-4c27195b-8e26-4339-b36b-b008f8695713
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382743831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3382743831
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1879465023
Short name T390
Test name
Test status
Simulation time 133902782 ps
CPU time 0.88 seconds
Started Apr 21 01:33:22 PM PDT 24
Finished Apr 21 01:33:23 PM PDT 24
Peak memory 208464 kb
Host smart-1e988c46-ea64-48e7-99d1-941ff35641be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879465023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1879465023
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.478545406
Short name T594
Test name
Test status
Simulation time 119091104 ps
CPU time 1.38 seconds
Started Apr 21 01:33:31 PM PDT 24
Finished Apr 21 01:33:33 PM PDT 24
Peak memory 209444 kb
Host smart-5656e2f7-5042-44ac-891f-f18f4ec6b9c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478545406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.478545406
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2474508233
Short name T514
Test name
Test status
Simulation time 945889297 ps
CPU time 8.9 seconds
Started Apr 21 01:33:28 PM PDT 24
Finished Apr 21 01:33:37 PM PDT 24
Peak memory 225844 kb
Host smart-b9d36ada-637f-4f36-b5cb-6c0aa3fe000f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474508233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2474508233
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1146915255
Short name T764
Test name
Test status
Simulation time 4743089426 ps
CPU time 20.15 seconds
Started Apr 21 01:33:29 PM PDT 24
Finished Apr 21 01:33:49 PM PDT 24
Peak memory 217764 kb
Host smart-e66f0118-f1a9-48ec-b701-474cec077bb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146915255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1146915255
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3335309926
Short name T745
Test name
Test status
Simulation time 391217957 ps
CPU time 3.03 seconds
Started Apr 21 01:33:32 PM PDT 24
Finished Apr 21 01:33:35 PM PDT 24
Peak memory 217876 kb
Host smart-b38c2665-30fa-4e35-8e97-c95bac6b4922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335309926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3335309926
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.4280635421
Short name T780
Test name
Test status
Simulation time 305163253 ps
CPU time 12.18 seconds
Started Apr 21 01:33:30 PM PDT 24
Finished Apr 21 01:33:42 PM PDT 24
Peak memory 217824 kb
Host smart-56674f2e-1002-4e1c-a172-65993a080b67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280635421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.4280635421
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2196684386
Short name T487
Test name
Test status
Simulation time 955999930 ps
CPU time 7.85 seconds
Started Apr 21 01:33:28 PM PDT 24
Finished Apr 21 01:33:36 PM PDT 24
Peak memory 217884 kb
Host smart-2b152b1c-21e7-43e9-ac58-de2b573cfb65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196684386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2196684386
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.789683364
Short name T642
Test name
Test status
Simulation time 541705271 ps
CPU time 7.23 seconds
Started Apr 21 01:33:27 PM PDT 24
Finished Apr 21 01:33:34 PM PDT 24
Peak memory 217856 kb
Host smart-49c1bbe5-5ec4-48b4-8786-56361b1c5f71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789683364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.789683364
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3387033911
Short name T176
Test name
Test status
Simulation time 42692453 ps
CPU time 1.29 seconds
Started Apr 21 01:33:25 PM PDT 24
Finished Apr 21 01:33:27 PM PDT 24
Peak memory 213404 kb
Host smart-99b97a66-68b3-42ee-ae9c-822970895b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387033911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3387033911
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3997216111
Short name T754
Test name
Test status
Simulation time 5172035702 ps
CPU time 26.38 seconds
Started Apr 21 01:33:32 PM PDT 24
Finished Apr 21 01:33:59 PM PDT 24
Peak memory 250948 kb
Host smart-6c3f5fc6-c7a5-42d6-9175-6b82a25c0003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997216111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3997216111
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2171547470
Short name T13
Test name
Test status
Simulation time 107168305 ps
CPU time 8.53 seconds
Started Apr 21 01:33:30 PM PDT 24
Finished Apr 21 01:33:39 PM PDT 24
Peak memory 248512 kb
Host smart-81a196a4-1c7d-4711-9961-14f9383b4e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171547470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2171547470
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4066382272
Short name T579
Test name
Test status
Simulation time 5675464827 ps
CPU time 48.88 seconds
Started Apr 21 01:33:29 PM PDT 24
Finished Apr 21 01:34:18 PM PDT 24
Peak memory 219968 kb
Host smart-604328e8-188f-4dff-9c43-9ac2c7811d7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066382272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4066382272
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1957050140
Short name T765
Test name
Test status
Simulation time 15547137 ps
CPU time 1.08 seconds
Started Apr 21 01:33:27 PM PDT 24
Finished Apr 21 01:33:28 PM PDT 24
Peak memory 211612 kb
Host smart-ab96c245-67ef-4420-90fe-df6a1a4602e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957050140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1957050140
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.4006313434
Short name T640
Test name
Test status
Simulation time 67780503 ps
CPU time 0.89 seconds
Started Apr 21 01:33:33 PM PDT 24
Finished Apr 21 01:33:34 PM PDT 24
Peak memory 209432 kb
Host smart-d44f9292-8f8b-458c-8344-5a4a6ac47bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006313434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.4006313434
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2109835582
Short name T380
Test name
Test status
Simulation time 1158921640 ps
CPU time 16.24 seconds
Started Apr 21 01:33:35 PM PDT 24
Finished Apr 21 01:33:52 PM PDT 24
Peak memory 225968 kb
Host smart-63dc0cb6-e5fe-46eb-9c32-468d4d429311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109835582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2109835582
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1472379316
Short name T34
Test name
Test status
Simulation time 1375748076 ps
CPU time 2.76 seconds
Started Apr 21 01:33:32 PM PDT 24
Finished Apr 21 01:33:35 PM PDT 24
Peak memory 209412 kb
Host smart-a31edf2d-0e62-4029-8a27-f30b16370a0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472379316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1472379316
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2085597011
Short name T628
Test name
Test status
Simulation time 123867560 ps
CPU time 3.27 seconds
Started Apr 21 01:33:33 PM PDT 24
Finished Apr 21 01:33:36 PM PDT 24
Peak memory 217872 kb
Host smart-ee405883-efde-4345-9e67-0e0a476fc54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085597011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2085597011
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.56108839
Short name T218
Test name
Test status
Simulation time 367657429 ps
CPU time 13.15 seconds
Started Apr 21 01:33:35 PM PDT 24
Finished Apr 21 01:33:49 PM PDT 24
Peak memory 225972 kb
Host smart-702c1d1d-e7d9-43df-9865-eba6c2e35f11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56108839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.56108839
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1929506605
Short name T623
Test name
Test status
Simulation time 1760839335 ps
CPU time 14.57 seconds
Started Apr 21 01:33:33 PM PDT 24
Finished Apr 21 01:33:47 PM PDT 24
Peak memory 217892 kb
Host smart-12fcf36c-e234-446d-ae3c-9988f5272f63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929506605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1929506605
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.557866240
Short name T70
Test name
Test status
Simulation time 1366744210 ps
CPU time 9.72 seconds
Started Apr 21 01:33:33 PM PDT 24
Finished Apr 21 01:33:43 PM PDT 24
Peak memory 217904 kb
Host smart-bac5b00f-3a97-4d76-b9d4-86c8a522d1a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557866240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.557866240
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3310539615
Short name T658
Test name
Test status
Simulation time 985794534 ps
CPU time 9.48 seconds
Started Apr 21 01:33:32 PM PDT 24
Finished Apr 21 01:33:42 PM PDT 24
Peak memory 224276 kb
Host smart-0fb10d9f-f7ed-4b9f-80ee-5d35753985b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310539615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3310539615
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.690206540
Short name T46
Test name
Test status
Simulation time 45578147 ps
CPU time 3.19 seconds
Started Apr 21 01:33:29 PM PDT 24
Finished Apr 21 01:33:32 PM PDT 24
Peak memory 214404 kb
Host smart-294d79bb-823a-458e-9b1f-517ee96966f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690206540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.690206540
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3560359522
Short name T726
Test name
Test status
Simulation time 931258545 ps
CPU time 17.9 seconds
Started Apr 21 01:33:32 PM PDT 24
Finished Apr 21 01:33:50 PM PDT 24
Peak memory 250844 kb
Host smart-43eabc3d-60ea-459a-bb27-755a8705bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560359522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3560359522
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2798016383
Short name T18
Test name
Test status
Simulation time 218077380 ps
CPU time 8.91 seconds
Started Apr 21 01:33:29 PM PDT 24
Finished Apr 21 01:33:38 PM PDT 24
Peak memory 250568 kb
Host smart-de86dfcb-0f58-4182-ade9-3c1872443d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798016383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2798016383
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1715580423
Short name T350
Test name
Test status
Simulation time 14678548299 ps
CPU time 103.13 seconds
Started Apr 21 01:33:31 PM PDT 24
Finished Apr 21 01:35:15 PM PDT 24
Peak memory 227916 kb
Host smart-2c333eef-1c15-4e2b-aec6-cd9ea832c63b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715580423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1715580423
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.4071116423
Short name T158
Test name
Test status
Simulation time 11849737890 ps
CPU time 230.98 seconds
Started Apr 21 01:33:33 PM PDT 24
Finished Apr 21 01:37:24 PM PDT 24
Peak memory 316456 kb
Host smart-840519c9-2b38-4704-aff7-f6ac0ed218b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4071116423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.4071116423
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.257449959
Short name T272
Test name
Test status
Simulation time 39146480 ps
CPU time 0.89 seconds
Started Apr 21 01:33:40 PM PDT 24
Finished Apr 21 01:33:41 PM PDT 24
Peak memory 209468 kb
Host smart-f549e1d0-50bd-4c20-a633-3300683bab4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257449959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.257449959
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.661377462
Short name T756
Test name
Test status
Simulation time 2619459498 ps
CPU time 7.89 seconds
Started Apr 21 01:33:37 PM PDT 24
Finished Apr 21 01:33:45 PM PDT 24
Peak memory 217996 kb
Host smart-e83c1ef3-f19d-4fb3-bb9e-87e3cb28b2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661377462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.661377462
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.883266756
Short name T740
Test name
Test status
Simulation time 1928124246 ps
CPU time 11.67 seconds
Started Apr 21 01:33:36 PM PDT 24
Finished Apr 21 01:33:48 PM PDT 24
Peak memory 209476 kb
Host smart-06556c6c-1be6-4830-b0bb-b30e6184179e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883266756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.883266756
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1345909434
Short name T476
Test name
Test status
Simulation time 53536172 ps
CPU time 2.41 seconds
Started Apr 21 01:33:36 PM PDT 24
Finished Apr 21 01:33:39 PM PDT 24
Peak memory 217940 kb
Host smart-71a8d6f8-afad-4fe2-8828-d11abf2b793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345909434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1345909434
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4204947122
Short name T116
Test name
Test status
Simulation time 513382845 ps
CPU time 12.97 seconds
Started Apr 21 01:33:36 PM PDT 24
Finished Apr 21 01:33:49 PM PDT 24
Peak memory 217888 kb
Host smart-bb008a4a-b80a-4ff1-b48a-39427d8ed207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204947122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4204947122
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.910043048
Short name T395
Test name
Test status
Simulation time 199633598 ps
CPU time 5.91 seconds
Started Apr 21 01:33:35 PM PDT 24
Finished Apr 21 01:33:41 PM PDT 24
Peak memory 217812 kb
Host smart-4cbe0887-c94e-4cde-bc1f-ca5182d909b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910043048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.910043048
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3602221424
Short name T120
Test name
Test status
Simulation time 381447506 ps
CPU time 9.09 seconds
Started Apr 21 01:33:35 PM PDT 24
Finished Apr 21 01:33:45 PM PDT 24
Peak memory 224808 kb
Host smart-73c7694d-b4e1-4ff0-84ae-1cf3bb4a79cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602221424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3602221424
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1740249465
Short name T19
Test name
Test status
Simulation time 106366650 ps
CPU time 1.39 seconds
Started Apr 21 01:33:31 PM PDT 24
Finished Apr 21 01:33:32 PM PDT 24
Peak memory 213232 kb
Host smart-cc2c6f5f-e40f-4245-a2f8-726c3bbff60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740249465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1740249465
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2524806224
Short name T422
Test name
Test status
Simulation time 244591701 ps
CPU time 21.2 seconds
Started Apr 21 01:33:36 PM PDT 24
Finished Apr 21 01:33:57 PM PDT 24
Peak memory 250844 kb
Host smart-0b1c1c99-5554-4f3a-8774-da159893d46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524806224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2524806224
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.308283554
Short name T356
Test name
Test status
Simulation time 76359486 ps
CPU time 2.93 seconds
Started Apr 21 01:33:36 PM PDT 24
Finished Apr 21 01:33:40 PM PDT 24
Peak memory 223656 kb
Host smart-20aa2ffc-3e55-4ed5-a12b-ed6a77b08ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308283554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.308283554
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.43773198
Short name T283
Test name
Test status
Simulation time 96837324471 ps
CPU time 198.21 seconds
Started Apr 21 01:33:34 PM PDT 24
Finished Apr 21 01:36:53 PM PDT 24
Peak memory 267748 kb
Host smart-5b9a0859-a22a-446f-93c5-b70341e904ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43773198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.lc_ctrl_stress_all.43773198
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.533949989
Short name T843
Test name
Test status
Simulation time 138659082821 ps
CPU time 1698.99 seconds
Started Apr 21 01:33:38 PM PDT 24
Finished Apr 21 02:01:58 PM PDT 24
Peak memory 961520 kb
Host smart-dc2fe9b3-0473-440a-8118-69e6c825f80f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=533949989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.533949989
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.5210397
Short name T677
Test name
Test status
Simulation time 66856422 ps
CPU time 1.03 seconds
Started Apr 21 01:33:30 PM PDT 24
Finished Apr 21 01:33:31 PM PDT 24
Peak memory 211448 kb
Host smart-55166911-9632-4d13-9ab2-a57900defa02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5210397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola
tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl
_volatile_unlock_smoke.5210397
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1281448663
Short name T95
Test name
Test status
Simulation time 30291867 ps
CPU time 1.1 seconds
Started Apr 21 01:33:40 PM PDT 24
Finished Apr 21 01:33:41 PM PDT 24
Peak memory 209424 kb
Host smart-fd45e237-4411-45e2-b8e8-6d94f14c734f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281448663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1281448663
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1664617382
Short name T733
Test name
Test status
Simulation time 236226119 ps
CPU time 12.41 seconds
Started Apr 21 01:33:39 PM PDT 24
Finished Apr 21 01:33:51 PM PDT 24
Peak memory 217840 kb
Host smart-3b32840e-6b01-4cd3-b041-367a32611e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664617382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1664617382
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.791379092
Short name T475
Test name
Test status
Simulation time 5372264477 ps
CPU time 7.44 seconds
Started Apr 21 01:33:38 PM PDT 24
Finished Apr 21 01:33:45 PM PDT 24
Peak memory 209564 kb
Host smart-a54907d8-f005-436f-9da5-ffff22b14184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791379092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.791379092
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3154144670
Short name T614
Test name
Test status
Simulation time 44098964 ps
CPU time 2.08 seconds
Started Apr 21 01:33:39 PM PDT 24
Finished Apr 21 01:33:42 PM PDT 24
Peak memory 217828 kb
Host smart-f2fd3f47-a9d4-41d3-bc93-ca6a7053f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154144670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3154144670
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3134041689
Short name T550
Test name
Test status
Simulation time 1321606280 ps
CPU time 14.74 seconds
Started Apr 21 01:33:40 PM PDT 24
Finished Apr 21 01:33:55 PM PDT 24
Peak memory 225892 kb
Host smart-cc4c7c3d-4ee1-4a5f-b4e0-22eb36294d37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134041689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3134041689
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2294593858
Short name T339
Test name
Test status
Simulation time 805846991 ps
CPU time 8.92 seconds
Started Apr 21 01:33:41 PM PDT 24
Finished Apr 21 01:33:50 PM PDT 24
Peak memory 217808 kb
Host smart-22ff738f-62d2-4c87-8875-fb0337ff4218
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294593858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2294593858
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3535583807
Short name T679
Test name
Test status
Simulation time 261760834 ps
CPU time 9.69 seconds
Started Apr 21 01:33:41 PM PDT 24
Finished Apr 21 01:33:51 PM PDT 24
Peak memory 217884 kb
Host smart-61272939-9abe-44ee-90eb-1b2ce7844fa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535583807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3535583807
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3898086868
Short name T690
Test name
Test status
Simulation time 2713428496 ps
CPU time 8.75 seconds
Started Apr 21 01:33:38 PM PDT 24
Finished Apr 21 01:33:47 PM PDT 24
Peak memory 218052 kb
Host smart-e9065e5f-5490-4e38-acaf-eb9b4b41b4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898086868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3898086868
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.660236512
Short name T473
Test name
Test status
Simulation time 95520457 ps
CPU time 1.88 seconds
Started Apr 21 01:33:40 PM PDT 24
Finished Apr 21 01:33:42 PM PDT 24
Peak memory 213872 kb
Host smart-5ec8539a-f95f-46f9-acf1-a5d1f17456ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660236512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.660236512
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.491686781
Short name T220
Test name
Test status
Simulation time 1552256228 ps
CPU time 34.17 seconds
Started Apr 21 01:33:39 PM PDT 24
Finished Apr 21 01:34:13 PM PDT 24
Peak memory 250600 kb
Host smart-4c44732e-a80d-4a1e-9bd5-2c10925ac07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491686781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.491686781
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2969047772
Short name T515
Test name
Test status
Simulation time 185052935 ps
CPU time 8.75 seconds
Started Apr 21 01:33:40 PM PDT 24
Finished Apr 21 01:33:48 PM PDT 24
Peak memory 245980 kb
Host smart-24311394-9149-4506-8139-96dc7dd7231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969047772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2969047772
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3967475263
Short name T520
Test name
Test status
Simulation time 2394648848 ps
CPU time 98.42 seconds
Started Apr 21 01:33:43 PM PDT 24
Finished Apr 21 01:35:22 PM PDT 24
Peak memory 250952 kb
Host smart-c94f951f-d227-475c-8682-7861d124c82f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967475263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3967475263
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1702533304
Short name T521
Test name
Test status
Simulation time 30912979 ps
CPU time 1.14 seconds
Started Apr 21 01:33:39 PM PDT 24
Finished Apr 21 01:33:40 PM PDT 24
Peak memory 212504 kb
Host smart-d305e22d-e9b9-4bd9-8f05-1f4d1898e1c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702533304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1702533304
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2150914
Short name T647
Test name
Test status
Simulation time 38047889 ps
CPU time 0.95 seconds
Started Apr 21 01:33:50 PM PDT 24
Finished Apr 21 01:33:52 PM PDT 24
Peak memory 209396 kb
Host smart-5be825bc-2b62-4e46-84e3-1ec9ddda6e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2150914
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.4043514956
Short name T246
Test name
Test status
Simulation time 399019269 ps
CPU time 11.7 seconds
Started Apr 21 01:33:46 PM PDT 24
Finished Apr 21 01:33:58 PM PDT 24
Peak memory 217848 kb
Host smart-4d06bc7a-e32a-4889-a53a-f11110cf7001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043514956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.4043514956
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2942410173
Short name T533
Test name
Test status
Simulation time 353798560 ps
CPU time 9.01 seconds
Started Apr 21 01:33:45 PM PDT 24
Finished Apr 21 01:33:55 PM PDT 24
Peak memory 209416 kb
Host smart-9d288908-6c23-4551-a3c0-8b8ea74e0f46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942410173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2942410173
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1911806755
Short name T468
Test name
Test status
Simulation time 79491877 ps
CPU time 3.09 seconds
Started Apr 21 01:33:45 PM PDT 24
Finished Apr 21 01:33:48 PM PDT 24
Peak memory 217808 kb
Host smart-aebad5f9-e342-4ef7-99e4-d3929967aa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911806755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1911806755
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1571685882
Short name T330
Test name
Test status
Simulation time 2159174373 ps
CPU time 12.55 seconds
Started Apr 21 01:33:43 PM PDT 24
Finished Apr 21 01:33:56 PM PDT 24
Peak memory 226052 kb
Host smart-fbb0b7f8-d55a-4c21-9184-befe44e455b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571685882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1571685882
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.139817441
Short name T541
Test name
Test status
Simulation time 741521492 ps
CPU time 13.53 seconds
Started Apr 21 01:33:49 PM PDT 24
Finished Apr 21 01:34:03 PM PDT 24
Peak memory 217884 kb
Host smart-cda1f9d1-d33f-4f1c-943d-8e3a844ffc25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139817441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.139817441
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3685470487
Short name T328
Test name
Test status
Simulation time 295326360 ps
CPU time 10.61 seconds
Started Apr 21 01:33:51 PM PDT 24
Finished Apr 21 01:34:02 PM PDT 24
Peak memory 217884 kb
Host smart-2d44d637-88b8-4a23-80e0-285b7df5e1aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685470487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3685470487
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3166077221
Short name T499
Test name
Test status
Simulation time 1155578044 ps
CPU time 7.5 seconds
Started Apr 21 01:33:45 PM PDT 24
Finished Apr 21 01:33:53 PM PDT 24
Peak memory 217928 kb
Host smart-ba68db73-1950-47ff-a457-f02142b519d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166077221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3166077221
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1134025891
Short name T711
Test name
Test status
Simulation time 12294457 ps
CPU time 1.13 seconds
Started Apr 21 01:33:43 PM PDT 24
Finished Apr 21 01:33:44 PM PDT 24
Peak memory 211812 kb
Host smart-6ee07f06-7b68-436a-8878-bafd81d5cc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134025891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1134025891
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1711143762
Short name T101
Test name
Test status
Simulation time 236263990 ps
CPU time 28.22 seconds
Started Apr 21 01:33:42 PM PDT 24
Finished Apr 21 01:34:11 PM PDT 24
Peak memory 246188 kb
Host smart-45dbe0af-f407-4d16-9237-7084d1f74a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711143762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1711143762
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.521944122
Short name T384
Test name
Test status
Simulation time 612384187 ps
CPU time 10 seconds
Started Apr 21 01:33:49 PM PDT 24
Finished Apr 21 01:33:59 PM PDT 24
Peak memory 250868 kb
Host smart-1fffe416-639e-44ec-8f00-1159ba969082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521944122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.521944122
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.863868799
Short name T167
Test name
Test status
Simulation time 39380120676 ps
CPU time 206.78 seconds
Started Apr 21 01:33:47 PM PDT 24
Finished Apr 21 01:37:14 PM PDT 24
Peak memory 226040 kb
Host smart-7c52a487-0ca6-4c48-96bc-aae239d35ebd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863868799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.863868799
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.143231980
Short name T160
Test name
Test status
Simulation time 41994445893 ps
CPU time 361.29 seconds
Started Apr 21 01:33:48 PM PDT 24
Finished Apr 21 01:39:49 PM PDT 24
Peak memory 283804 kb
Host smart-cdf68991-5166-4414-a3cd-d721199cc912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=143231980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.143231980
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.99431272
Short name T646
Test name
Test status
Simulation time 221926348 ps
CPU time 1 seconds
Started Apr 21 01:33:41 PM PDT 24
Finished Apr 21 01:33:42 PM PDT 24
Peak memory 212516 kb
Host smart-887ccb3c-194f-4ddc-a23b-d1fbde7dcf08
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99431272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctr
l_volatile_unlock_smoke.99431272
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.989179186
Short name T632
Test name
Test status
Simulation time 44533936 ps
CPU time 0.83 seconds
Started Apr 21 01:33:56 PM PDT 24
Finished Apr 21 01:33:57 PM PDT 24
Peak memory 209348 kb
Host smart-a67ce310-e2cf-4799-ac69-c94c871121de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989179186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.989179186
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1212849175
Short name T758
Test name
Test status
Simulation time 855601502 ps
CPU time 13.26 seconds
Started Apr 21 01:33:48 PM PDT 24
Finished Apr 21 01:34:02 PM PDT 24
Peak memory 217852 kb
Host smart-438b3a94-6450-4019-b7bb-9bc6558d3547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212849175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1212849175
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.256279095
Short name T795
Test name
Test status
Simulation time 2663179728 ps
CPU time 13.52 seconds
Started Apr 21 01:33:49 PM PDT 24
Finished Apr 21 01:34:03 PM PDT 24
Peak memory 209508 kb
Host smart-c1a32d86-2ba2-41a5-aeec-d15a21010530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256279095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.256279095
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.55830540
Short name T504
Test name
Test status
Simulation time 21484379 ps
CPU time 1.64 seconds
Started Apr 21 01:33:49 PM PDT 24
Finished Apr 21 01:33:51 PM PDT 24
Peak memory 217844 kb
Host smart-4de5b096-9f39-4061-a50a-3ac7d780610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55830540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.55830540
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3242717064
Short name T483
Test name
Test status
Simulation time 347471278 ps
CPU time 13.88 seconds
Started Apr 21 01:33:48 PM PDT 24
Finished Apr 21 01:34:02 PM PDT 24
Peak memory 217848 kb
Host smart-c5aacd67-ed22-4eeb-8a10-94aad7dad9d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242717064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3242717064
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1484395061
Short name T346
Test name
Test status
Simulation time 982704244 ps
CPU time 8.13 seconds
Started Apr 21 01:33:50 PM PDT 24
Finished Apr 21 01:33:58 PM PDT 24
Peak memory 217860 kb
Host smart-7e06c665-edaa-4175-b77c-3b67cd115b8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484395061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1484395061
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2230604427
Short name T800
Test name
Test status
Simulation time 618037230 ps
CPU time 11.18 seconds
Started Apr 21 01:33:51 PM PDT 24
Finished Apr 21 01:34:02 PM PDT 24
Peak memory 217844 kb
Host smart-b8aabf64-21af-4601-b119-fb404343db72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230604427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2230604427
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2459655700
Short name T164
Test name
Test status
Simulation time 3446841876 ps
CPU time 7.85 seconds
Started Apr 21 01:33:51 PM PDT 24
Finished Apr 21 01:33:59 PM PDT 24
Peak memory 218072 kb
Host smart-fe5c8399-4182-4f4e-b6de-bf114db60a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459655700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2459655700
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2187193164
Short name T383
Test name
Test status
Simulation time 17630663 ps
CPU time 1.4 seconds
Started Apr 21 01:33:48 PM PDT 24
Finished Apr 21 01:33:50 PM PDT 24
Peak memory 213152 kb
Host smart-57319270-d391-4a16-bd47-ca92dbbb9b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187193164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2187193164
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1004232982
Short name T748
Test name
Test status
Simulation time 2661389445 ps
CPU time 28.85 seconds
Started Apr 21 01:33:50 PM PDT 24
Finished Apr 21 01:34:19 PM PDT 24
Peak memory 246896 kb
Host smart-be7ff31a-7cf0-448a-adc8-d63679271900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004232982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1004232982
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1167703433
Short name T378
Test name
Test status
Simulation time 116367375 ps
CPU time 8.58 seconds
Started Apr 21 01:33:50 PM PDT 24
Finished Apr 21 01:33:59 PM PDT 24
Peak memory 250588 kb
Host smart-e1836bc6-f4de-4667-9701-0f53e798fc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167703433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1167703433
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.4222402251
Short name T207
Test name
Test status
Simulation time 9017772441 ps
CPU time 188.44 seconds
Started Apr 21 01:33:49 PM PDT 24
Finished Apr 21 01:36:58 PM PDT 24
Peak memory 251412 kb
Host smart-20e8e3c0-95fc-4f4f-b70d-5185c8399cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222402251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.4222402251
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1626176320
Short name T669
Test name
Test status
Simulation time 40468563 ps
CPU time 0.89 seconds
Started Apr 21 01:33:51 PM PDT 24
Finished Apr 21 01:33:52 PM PDT 24
Peak memory 211420 kb
Host smart-9096e77e-c4f6-4371-a14a-b162598c3599
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626176320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1626176320
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1691199498
Short name T597
Test name
Test status
Simulation time 60842761 ps
CPU time 1.04 seconds
Started Apr 21 01:33:58 PM PDT 24
Finished Apr 21 01:33:59 PM PDT 24
Peak memory 209404 kb
Host smart-5e4f2ddf-1d4d-4e11-83f9-e9fee0b734b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691199498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1691199498
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3290528049
Short name T442
Test name
Test status
Simulation time 1136067697 ps
CPU time 10.85 seconds
Started Apr 21 01:33:54 PM PDT 24
Finished Apr 21 01:34:05 PM PDT 24
Peak memory 217852 kb
Host smart-51e8d8d1-f3e7-4fb6-bb5a-8c05b4a8cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290528049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3290528049
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2928375863
Short name T373
Test name
Test status
Simulation time 262322225 ps
CPU time 3.95 seconds
Started Apr 21 01:33:57 PM PDT 24
Finished Apr 21 01:34:01 PM PDT 24
Peak memory 209392 kb
Host smart-08707396-0930-4a0e-8db7-b3a1e240fe7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928375863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2928375863
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1998816074
Short name T490
Test name
Test status
Simulation time 80205683 ps
CPU time 3.81 seconds
Started Apr 21 01:33:51 PM PDT 24
Finished Apr 21 01:33:55 PM PDT 24
Peak memory 217848 kb
Host smart-05d46ae8-31b4-4ea4-911e-a8cacf7b264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998816074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1998816074
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.691171072
Short name T276
Test name
Test status
Simulation time 217613755 ps
CPU time 8.21 seconds
Started Apr 21 01:33:54 PM PDT 24
Finished Apr 21 01:34:03 PM PDT 24
Peak memory 225408 kb
Host smart-f6fb4f6e-98f3-49b5-83df-3c977bd20c2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691171072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.691171072
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2055559740
Short name T670
Test name
Test status
Simulation time 805267159 ps
CPU time 6.43 seconds
Started Apr 21 01:33:52 PM PDT 24
Finished Apr 21 01:33:59 PM PDT 24
Peak memory 217876 kb
Host smart-de34d0e5-1bce-44e8-9bcd-a8308b13ea7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055559740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2055559740
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3664926478
Short name T224
Test name
Test status
Simulation time 855592929 ps
CPU time 8.78 seconds
Started Apr 21 01:34:02 PM PDT 24
Finished Apr 21 01:34:12 PM PDT 24
Peak memory 217860 kb
Host smart-66734a71-73aa-4987-aa92-4c1892fa3568
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664926478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3664926478
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.635140665
Short name T595
Test name
Test status
Simulation time 2564585382 ps
CPU time 7.7 seconds
Started Apr 21 01:33:54 PM PDT 24
Finished Apr 21 01:34:02 PM PDT 24
Peak memory 224868 kb
Host smart-dfe872d5-74aa-444b-a208-285c9730fba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635140665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.635140665
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.53851456
Short name T76
Test name
Test status
Simulation time 152772048 ps
CPU time 1.99 seconds
Started Apr 21 01:33:52 PM PDT 24
Finished Apr 21 01:33:54 PM PDT 24
Peak memory 217652 kb
Host smart-7e83bdc5-458f-4686-b1ef-46222d7f67c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53851456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.53851456
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.401730691
Short name T121
Test name
Test status
Simulation time 4063760286 ps
CPU time 19.02 seconds
Started Apr 21 01:33:51 PM PDT 24
Finished Apr 21 01:34:10 PM PDT 24
Peak memory 250896 kb
Host smart-6003e17f-d0ed-4402-9de0-5faf5a6eaaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401730691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.401730691
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1894074326
Short name T415
Test name
Test status
Simulation time 71807025 ps
CPU time 8.5 seconds
Started Apr 21 01:33:51 PM PDT 24
Finished Apr 21 01:33:59 PM PDT 24
Peak memory 250852 kb
Host smart-28ebd18f-0d5e-47ba-85d3-0d68ba9dab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894074326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1894074326
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.296411460
Short name T682
Test name
Test status
Simulation time 2130140987 ps
CPU time 44.51 seconds
Started Apr 21 01:33:53 PM PDT 24
Finished Apr 21 01:34:38 PM PDT 24
Peak memory 225948 kb
Host smart-2896e6da-7fb5-451f-8df9-d5ac27ffaf7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296411460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.296411460
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1205913996
Short name T492
Test name
Test status
Simulation time 14199992 ps
CPU time 1.12 seconds
Started Apr 21 01:33:52 PM PDT 24
Finished Apr 21 01:33:53 PM PDT 24
Peak memory 211464 kb
Host smart-bf253231-ebde-46e9-8507-ec6a07a82ca0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205913996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1205913996
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1836720648
Short name T372
Test name
Test status
Simulation time 16761712 ps
CPU time 0.97 seconds
Started Apr 21 01:30:37 PM PDT 24
Finished Apr 21 01:30:38 PM PDT 24
Peak memory 209412 kb
Host smart-8497c777-edc2-42f2-b4e1-4c0711f89432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836720648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1836720648
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.509641257
Short name T358
Test name
Test status
Simulation time 12569221 ps
CPU time 0.97 seconds
Started Apr 21 01:30:30 PM PDT 24
Finished Apr 21 01:30:31 PM PDT 24
Peak memory 209440 kb
Host smart-aaabf9ba-7fbf-431d-a186-270fbff3e621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509641257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.509641257
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.715076084
Short name T604
Test name
Test status
Simulation time 1773808633 ps
CPU time 9.45 seconds
Started Apr 21 01:30:28 PM PDT 24
Finished Apr 21 01:30:38 PM PDT 24
Peak memory 217844 kb
Host smart-67113336-c02b-4ea5-a901-0ed3d7d45675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715076084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.715076084
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1194845864
Short name T33
Test name
Test status
Simulation time 113529084 ps
CPU time 2.02 seconds
Started Apr 21 01:30:31 PM PDT 24
Finished Apr 21 01:30:33 PM PDT 24
Peak memory 209436 kb
Host smart-4e53a916-40db-407f-a9bc-ef9b37b57994
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194845864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1194845864
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3276513673
Short name T433
Test name
Test status
Simulation time 3225369390 ps
CPU time 86.61 seconds
Started Apr 21 01:30:28 PM PDT 24
Finished Apr 21 01:31:55 PM PDT 24
Peak memory 218872 kb
Host smart-1f338428-f28d-4ee5-a944-80caa1fbb87e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276513673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3276513673
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1684770589
Short name T184
Test name
Test status
Simulation time 78558751 ps
CPU time 2.84 seconds
Started Apr 21 01:30:29 PM PDT 24
Finished Apr 21 01:30:32 PM PDT 24
Peak memory 217628 kb
Host smart-39f17bf0-20a0-4149-ae32-da9eace0b70b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684770589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
684770589
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.426229522
Short name T705
Test name
Test status
Simulation time 776649796 ps
CPU time 6.52 seconds
Started Apr 21 01:30:30 PM PDT 24
Finished Apr 21 01:30:37 PM PDT 24
Peak memory 217800 kb
Host smart-d032773c-db49-4e03-afb8-bc20f5c8bd8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426229522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.426229522
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2706835251
Short name T834
Test name
Test status
Simulation time 3256907013 ps
CPU time 35.57 seconds
Started Apr 21 01:30:32 PM PDT 24
Finished Apr 21 01:31:07 PM PDT 24
Peak memory 213976 kb
Host smart-3f8d7f63-3f97-4498-b0e9-788bb32a72ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706835251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2706835251
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3215402587
Short name T688
Test name
Test status
Simulation time 608001771 ps
CPU time 3.34 seconds
Started Apr 21 01:30:31 PM PDT 24
Finished Apr 21 01:30:34 PM PDT 24
Peak memory 213360 kb
Host smart-bbe1d0f8-b030-4309-b9e5-9477d32874b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215402587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3215402587
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1530597559
Short name T750
Test name
Test status
Simulation time 2570109113 ps
CPU time 33.25 seconds
Started Apr 21 01:30:30 PM PDT 24
Finished Apr 21 01:31:03 PM PDT 24
Peak memory 270884 kb
Host smart-be70cec5-78d3-4377-8db2-8f9fdb650101
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530597559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1530597559
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3398426566
Short name T381
Test name
Test status
Simulation time 401829676 ps
CPU time 9.97 seconds
Started Apr 21 01:30:29 PM PDT 24
Finished Apr 21 01:30:39 PM PDT 24
Peak memory 249508 kb
Host smart-bf13e4aa-9134-4c05-bdf4-aab5f4c165bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398426566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3398426566
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.498369543
Short name T408
Test name
Test status
Simulation time 95057068 ps
CPU time 2.24 seconds
Started Apr 21 01:30:30 PM PDT 24
Finished Apr 21 01:30:32 PM PDT 24
Peak memory 217940 kb
Host smart-03402000-b94b-4af7-991f-8ef8eb7becc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498369543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.498369543
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2738697717
Short name T173
Test name
Test status
Simulation time 1293216209 ps
CPU time 10.88 seconds
Started Apr 21 01:30:30 PM PDT 24
Finished Apr 21 01:30:41 PM PDT 24
Peak memory 217772 kb
Host smart-6b6adfd9-72a7-4ece-8424-e2f76d5e9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738697717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2738697717
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3449010141
Short name T73
Test name
Test status
Simulation time 1526553084 ps
CPU time 23.16 seconds
Started Apr 21 01:30:35 PM PDT 24
Finished Apr 21 01:30:58 PM PDT 24
Peak memory 267832 kb
Host smart-d2d98441-cdf6-4ea0-98de-6f68b9bfed72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449010141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3449010141
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3743777576
Short name T543
Test name
Test status
Simulation time 1136783958 ps
CPU time 13.26 seconds
Started Apr 21 01:30:31 PM PDT 24
Finished Apr 21 01:30:44 PM PDT 24
Peak memory 218188 kb
Host smart-50d80ab1-21bc-4c04-b2f4-d96cee7d3681
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743777576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3743777576
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.730298505
Short name T839
Test name
Test status
Simulation time 500600648 ps
CPU time 11.37 seconds
Started Apr 21 01:30:38 PM PDT 24
Finished Apr 21 01:30:50 PM PDT 24
Peak memory 217824 kb
Host smart-2a0e76e9-2653-4812-adc7-8115e111968b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730298505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.730298505
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2183314723
Short name T637
Test name
Test status
Simulation time 745149108 ps
CPU time 9.28 seconds
Started Apr 21 01:30:32 PM PDT 24
Finished Apr 21 01:30:42 PM PDT 24
Peak memory 217920 kb
Host smart-7d211c26-df66-4a7d-88a5-ec57cfe702bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183314723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
183314723
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4173835677
Short name T165
Test name
Test status
Simulation time 1316683505 ps
CPU time 9.3 seconds
Started Apr 21 01:30:29 PM PDT 24
Finished Apr 21 01:30:39 PM PDT 24
Peak memory 225936 kb
Host smart-879f8a77-5f67-46aa-9eda-878f40bc307d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173835677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4173835677
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1182270421
Short name T832
Test name
Test status
Simulation time 82080667 ps
CPU time 1.9 seconds
Started Apr 21 01:30:22 PM PDT 24
Finished Apr 21 01:30:24 PM PDT 24
Peak memory 213688 kb
Host smart-9a19893b-f225-4341-a5d2-c9c0da063710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182270421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1182270421
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.929376208
Short name T507
Test name
Test status
Simulation time 135111271 ps
CPU time 8.12 seconds
Started Apr 21 01:30:25 PM PDT 24
Finished Apr 21 01:30:33 PM PDT 24
Peak memory 250852 kb
Host smart-9495c426-e5a8-419c-a845-90fc3f5ad23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929376208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.929376208
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.427603854
Short name T450
Test name
Test status
Simulation time 41457066856 ps
CPU time 305.05 seconds
Started Apr 21 01:30:38 PM PDT 24
Finished Apr 21 01:35:43 PM PDT 24
Peak memory 300156 kb
Host smart-918a3754-c1c2-456e-98cb-7b6457299174
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427603854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.427603854
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.698444205
Short name T833
Test name
Test status
Simulation time 16727448813 ps
CPU time 364.33 seconds
Started Apr 21 01:30:36 PM PDT 24
Finished Apr 21 01:36:41 PM PDT 24
Peak memory 389272 kb
Host smart-9fa20fe1-edc4-43b3-a961-e5d221fa555c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=698444205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.698444205
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.91077159
Short name T779
Test name
Test status
Simulation time 14542707 ps
CPU time 0.91 seconds
Started Apr 21 01:30:26 PM PDT 24
Finished Apr 21 01:30:27 PM PDT 24
Peak memory 211464 kb
Host smart-f226c642-3c9e-45c1-84b6-a925749d26f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91077159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_volatile_unlock_smoke.91077159
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1223933473
Short name T274
Test name
Test status
Simulation time 38014467 ps
CPU time 1.11 seconds
Started Apr 21 01:34:04 PM PDT 24
Finished Apr 21 01:34:05 PM PDT 24
Peak memory 209412 kb
Host smart-d98896ff-8412-41e8-86b9-4a9a7b9efb63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223933473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1223933473
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2114732377
Short name T262
Test name
Test status
Simulation time 537049553 ps
CPU time 21.58 seconds
Started Apr 21 01:34:00 PM PDT 24
Finished Apr 21 01:34:21 PM PDT 24
Peak memory 217856 kb
Host smart-e5efc3f7-f7e2-4d0a-ba22-9f59399e213c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114732377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2114732377
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2044799854
Short name T29
Test name
Test status
Simulation time 2669007453 ps
CPU time 15.9 seconds
Started Apr 21 01:34:04 PM PDT 24
Finished Apr 21 01:34:20 PM PDT 24
Peak memory 209544 kb
Host smart-d1cdc138-eda3-422f-a7ea-5dceb5c5c10d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044799854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2044799854
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.438393924
Short name T248
Test name
Test status
Simulation time 196828374 ps
CPU time 4.41 seconds
Started Apr 21 01:33:58 PM PDT 24
Finished Apr 21 01:34:03 PM PDT 24
Peak memory 217824 kb
Host smart-26b8a06e-98ac-4085-9717-7c5bece6da78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438393924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.438393924
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.733586534
Short name T45
Test name
Test status
Simulation time 824666250 ps
CPU time 13.18 seconds
Started Apr 21 01:34:00 PM PDT 24
Finished Apr 21 01:34:14 PM PDT 24
Peak memory 225900 kb
Host smart-34dd32ec-8eb6-4c6d-9eb4-391c4e1c438e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733586534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.733586534
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2803081688
Short name T830
Test name
Test status
Simulation time 211946293 ps
CPU time 6.72 seconds
Started Apr 21 01:34:00 PM PDT 24
Finished Apr 21 01:34:07 PM PDT 24
Peak memory 218044 kb
Host smart-bb76cd04-64dc-45ca-b982-44e81a748c24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803081688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2803081688
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3868178109
Short name T477
Test name
Test status
Simulation time 2095031742 ps
CPU time 16.67 seconds
Started Apr 21 01:34:00 PM PDT 24
Finished Apr 21 01:34:17 PM PDT 24
Peak memory 217832 kb
Host smart-5234578d-9ca3-468e-a405-0c277f310783
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868178109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3868178109
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3346940724
Short name T548
Test name
Test status
Simulation time 2705318469 ps
CPU time 9.79 seconds
Started Apr 21 01:34:00 PM PDT 24
Finished Apr 21 01:34:10 PM PDT 24
Peak memory 218004 kb
Host smart-532cff99-0ad7-4fc3-98ed-c3b61ceb00f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346940724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3346940724
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4043242190
Short name T344
Test name
Test status
Simulation time 79471980 ps
CPU time 1.65 seconds
Started Apr 21 01:33:58 PM PDT 24
Finished Apr 21 01:34:00 PM PDT 24
Peak memory 213556 kb
Host smart-f7ddf355-161b-4dc7-a480-64a6ad58d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043242190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4043242190
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1776114958
Short name T229
Test name
Test status
Simulation time 1281079972 ps
CPU time 24.84 seconds
Started Apr 21 01:34:03 PM PDT 24
Finished Apr 21 01:34:28 PM PDT 24
Peak memory 245444 kb
Host smart-be058ba6-f912-496b-8058-99aaca95a3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776114958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1776114958
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3820070631
Short name T667
Test name
Test status
Simulation time 78667758 ps
CPU time 6.4 seconds
Started Apr 21 01:34:44 PM PDT 24
Finished Apr 21 01:34:51 PM PDT 24
Peak memory 247472 kb
Host smart-b50c6d9d-ddda-471f-b84a-89e759c73b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820070631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3820070631
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2495018070
Short name T513
Test name
Test status
Simulation time 5026860001 ps
CPU time 80.86 seconds
Started Apr 21 01:34:00 PM PDT 24
Finished Apr 21 01:35:21 PM PDT 24
Peak memory 271008 kb
Host smart-290a79e1-ffbd-49d8-8285-a3a43c01c5d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495018070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2495018070
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.812860671
Short name T263
Test name
Test status
Simulation time 174427671 ps
CPU time 0.93 seconds
Started Apr 21 01:33:55 PM PDT 24
Finished Apr 21 01:33:57 PM PDT 24
Peak memory 211552 kb
Host smart-c0f948b3-9fa5-4ceb-9633-e242c9d2ddd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812860671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.812860671
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3053355140
Short name T175
Test name
Test status
Simulation time 15933907 ps
CPU time 1.03 seconds
Started Apr 21 01:34:06 PM PDT 24
Finished Apr 21 01:34:08 PM PDT 24
Peak memory 209452 kb
Host smart-f7e4929d-1315-4db4-a739-dda286489d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053355140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3053355140
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3818627675
Short name T784
Test name
Test status
Simulation time 794797112 ps
CPU time 12.72 seconds
Started Apr 21 01:34:04 PM PDT 24
Finished Apr 21 01:34:17 PM PDT 24
Peak memory 225988 kb
Host smart-788040a4-5141-48fe-b016-17e8ce319f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818627675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3818627675
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3587521951
Short name T369
Test name
Test status
Simulation time 485043003 ps
CPU time 4.21 seconds
Started Apr 21 01:34:05 PM PDT 24
Finished Apr 21 01:34:09 PM PDT 24
Peak memory 209392 kb
Host smart-30647d2c-ea23-4a84-91eb-d4d20c731dad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587521951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3587521951
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3465008275
Short name T820
Test name
Test status
Simulation time 27860577 ps
CPU time 1.96 seconds
Started Apr 21 01:34:03 PM PDT 24
Finished Apr 21 01:34:05 PM PDT 24
Peak memory 218000 kb
Host smart-99478352-9157-4856-afa5-64dfddaf7198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465008275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3465008275
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.232667950
Short name T854
Test name
Test status
Simulation time 1502493854 ps
CPU time 14.15 seconds
Started Apr 21 01:34:06 PM PDT 24
Finished Apr 21 01:34:20 PM PDT 24
Peak memory 218828 kb
Host smart-6b336122-a0a8-45b8-8cd4-ff560640123c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232667950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.232667950
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1379770850
Short name T467
Test name
Test status
Simulation time 200792632 ps
CPU time 8.96 seconds
Started Apr 21 01:34:09 PM PDT 24
Finished Apr 21 01:34:18 PM PDT 24
Peak memory 217848 kb
Host smart-8b07c7c4-8095-4cfa-b73b-50ffb8c249a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379770850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1379770850
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.810876201
Short name T501
Test name
Test status
Simulation time 1121166753 ps
CPU time 11.65 seconds
Started Apr 21 01:34:07 PM PDT 24
Finished Apr 21 01:34:19 PM PDT 24
Peak memory 217828 kb
Host smart-d4004a96-fed2-4a5d-928c-a6f88e88e0cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810876201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.810876201
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1991846829
Short name T68
Test name
Test status
Simulation time 63352558 ps
CPU time 2.25 seconds
Started Apr 21 01:34:02 PM PDT 24
Finished Apr 21 01:34:05 PM PDT 24
Peak memory 217860 kb
Host smart-eaab7ef1-cb1a-40e8-91d5-b835677cce5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991846829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1991846829
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2201064790
Short name T98
Test name
Test status
Simulation time 661835532 ps
CPU time 25.91 seconds
Started Apr 21 01:34:11 PM PDT 24
Finished Apr 21 01:34:37 PM PDT 24
Peak memory 250720 kb
Host smart-8570d0c0-94c4-4e98-a063-e3cd1e1d289e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201064790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2201064790
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3655644691
Short name T336
Test name
Test status
Simulation time 518183551 ps
CPU time 5.69 seconds
Started Apr 21 01:34:04 PM PDT 24
Finished Apr 21 01:34:10 PM PDT 24
Peak memory 250832 kb
Host smart-3d506891-d2d6-4c59-a247-a3ca3e448a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655644691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3655644691
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3158613812
Short name T91
Test name
Test status
Simulation time 195117539356 ps
CPU time 860.15 seconds
Started Apr 21 01:34:07 PM PDT 24
Finished Apr 21 01:48:27 PM PDT 24
Peak memory 273500 kb
Host smart-3bbbe07f-7977-4406-aa54-8ffb8ee33035
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158613812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3158613812
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3839388945
Short name T168
Test name
Test status
Simulation time 279037400060 ps
CPU time 663.49 seconds
Started Apr 21 01:34:08 PM PDT 24
Finished Apr 21 01:45:12 PM PDT 24
Peak memory 283824 kb
Host smart-75a7c4fd-51c8-4c6b-ad66-b9b85099ca98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3839388945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3839388945
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1645255136
Short name T87
Test name
Test status
Simulation time 14807221 ps
CPU time 0.97 seconds
Started Apr 21 01:34:01 PM PDT 24
Finished Apr 21 01:34:02 PM PDT 24
Peak memory 211432 kb
Host smart-bdeca333-bd1d-43b0-91b9-82f0462b96a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645255136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1645255136
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.491318215
Short name T656
Test name
Test status
Simulation time 33413138 ps
CPU time 1.1 seconds
Started Apr 21 01:34:15 PM PDT 24
Finished Apr 21 01:34:16 PM PDT 24
Peak memory 209428 kb
Host smart-c04248a5-cd48-47e3-94dd-ab991b59537d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491318215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.491318215
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3083439290
Short name T430
Test name
Test status
Simulation time 552177907 ps
CPU time 8.32 seconds
Started Apr 21 01:34:06 PM PDT 24
Finished Apr 21 01:34:14 PM PDT 24
Peak memory 217732 kb
Host smart-ddb36851-ed58-461c-898e-c2876287bf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083439290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3083439290
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.545870433
Short name T393
Test name
Test status
Simulation time 988901793 ps
CPU time 6.34 seconds
Started Apr 21 01:34:10 PM PDT 24
Finished Apr 21 01:34:17 PM PDT 24
Peak memory 216860 kb
Host smart-5603ce5b-48ea-46f1-a1a1-2fd2491480a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545870433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.545870433
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1864182407
Short name T811
Test name
Test status
Simulation time 134588536 ps
CPU time 3.96 seconds
Started Apr 21 01:34:10 PM PDT 24
Finished Apr 21 01:34:14 PM PDT 24
Peak memory 217924 kb
Host smart-87960cec-a00e-4780-a0d7-76b73d6651de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864182407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1864182407
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3976921564
Short name T429
Test name
Test status
Simulation time 558355165 ps
CPU time 13.96 seconds
Started Apr 21 01:34:20 PM PDT 24
Finished Apr 21 01:34:34 PM PDT 24
Peak memory 217836 kb
Host smart-06acd824-c10e-4616-8dcc-d047431c2c21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976921564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3976921564
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1558026163
Short name T556
Test name
Test status
Simulation time 165455842 ps
CPU time 8.4 seconds
Started Apr 21 01:34:10 PM PDT 24
Finished Apr 21 01:34:19 PM PDT 24
Peak memory 217840 kb
Host smart-51dffb37-1cf0-45cd-b65a-d6a4b0d977c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558026163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1558026163
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4284974603
Short name T770
Test name
Test status
Simulation time 434701382 ps
CPU time 8.88 seconds
Started Apr 21 01:34:10 PM PDT 24
Finished Apr 21 01:34:20 PM PDT 24
Peak memory 217784 kb
Host smart-0e12f41f-0493-44e6-ba4c-87a5e3da1528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284974603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
4284974603
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.550673839
Short name T525
Test name
Test status
Simulation time 649812858 ps
CPU time 7.46 seconds
Started Apr 21 01:34:10 PM PDT 24
Finished Apr 21 01:34:18 PM PDT 24
Peak memory 217920 kb
Host smart-a8abe2b4-dbb8-4453-8a3e-85d962beb026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550673839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.550673839
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3859579969
Short name T271
Test name
Test status
Simulation time 87216202 ps
CPU time 1.63 seconds
Started Apr 21 01:34:08 PM PDT 24
Finished Apr 21 01:34:10 PM PDT 24
Peak memory 213380 kb
Host smart-3261cbad-035a-4c81-b47d-b44b1e23c6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859579969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3859579969
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1790065010
Short name T592
Test name
Test status
Simulation time 260005447 ps
CPU time 25.55 seconds
Started Apr 21 01:34:10 PM PDT 24
Finished Apr 21 01:34:36 PM PDT 24
Peak memory 245804 kb
Host smart-3d903c8e-8007-4433-8cfd-908ce0dafe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790065010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1790065010
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2601098948
Short name T357
Test name
Test status
Simulation time 302252007 ps
CPU time 3.65 seconds
Started Apr 21 01:34:10 PM PDT 24
Finished Apr 21 01:34:14 PM PDT 24
Peak memory 226256 kb
Host smart-aa112dae-3336-4a0d-9b9e-8b92c9ab9410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601098948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2601098948
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2128860137
Short name T188
Test name
Test status
Simulation time 27457494410 ps
CPU time 192.51 seconds
Started Apr 21 01:34:08 PM PDT 24
Finished Apr 21 01:37:20 PM PDT 24
Peak memory 262632 kb
Host smart-80023fbe-a003-4fa4-b125-0a6775e5a214
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128860137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2128860137
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1638595252
Short name T223
Test name
Test status
Simulation time 32393582 ps
CPU time 0.69 seconds
Started Apr 21 01:34:06 PM PDT 24
Finished Apr 21 01:34:07 PM PDT 24
Peak memory 206780 kb
Host smart-fa5c567f-a6d1-4b55-a9d4-69fbdfe603b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638595252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1638595252
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3832326992
Short name T445
Test name
Test status
Simulation time 51485213 ps
CPU time 0.88 seconds
Started Apr 21 01:34:14 PM PDT 24
Finished Apr 21 01:34:15 PM PDT 24
Peak memory 209412 kb
Host smart-58850246-05aa-4400-bad4-af3da96d4c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832326992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3832326992
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.322130608
Short name T394
Test name
Test status
Simulation time 1153234720 ps
CPU time 12.41 seconds
Started Apr 21 01:34:15 PM PDT 24
Finished Apr 21 01:34:28 PM PDT 24
Peak memory 225948 kb
Host smart-34daf830-0d71-4b05-8c49-db07b807a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322130608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.322130608
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3696332234
Short name T28
Test name
Test status
Simulation time 1148638796 ps
CPU time 8.33 seconds
Started Apr 21 01:34:12 PM PDT 24
Finished Apr 21 01:34:21 PM PDT 24
Peak memory 209448 kb
Host smart-10d38b41-ec49-4213-b9ff-d1444c8bc130
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696332234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3696332234
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2382923691
Short name T700
Test name
Test status
Simulation time 274497456 ps
CPU time 4.19 seconds
Started Apr 21 01:34:19 PM PDT 24
Finished Apr 21 01:34:23 PM PDT 24
Peak memory 217832 kb
Host smart-c2c45111-56c5-4381-8a40-add1c481a93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382923691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2382923691
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3691396884
Short name T427
Test name
Test status
Simulation time 512274654 ps
CPU time 15.68 seconds
Started Apr 21 01:34:12 PM PDT 24
Finished Apr 21 01:34:28 PM PDT 24
Peak memory 218812 kb
Host smart-4be3cf2c-c0a4-4b48-a1c8-ec53a21dda42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691396884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3691396884
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.8836523
Short name T225
Test name
Test status
Simulation time 933179074 ps
CPU time 13.39 seconds
Started Apr 21 01:34:19 PM PDT 24
Finished Apr 21 01:34:33 PM PDT 24
Peak memory 217852 kb
Host smart-1dc3b907-5875-4806-aa9f-c9f6e96a7c94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8836523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_dige
st.8836523
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1234975188
Short name T675
Test name
Test status
Simulation time 523416642 ps
CPU time 10.69 seconds
Started Apr 21 01:34:15 PM PDT 24
Finished Apr 21 01:34:26 PM PDT 24
Peak memory 217884 kb
Host smart-1c74b7ac-832d-401b-9965-8919827b2856
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234975188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1234975188
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3226620382
Short name T63
Test name
Test status
Simulation time 989825468 ps
CPU time 10.75 seconds
Started Apr 21 01:34:11 PM PDT 24
Finished Apr 21 01:34:22 PM PDT 24
Peak memory 217908 kb
Host smart-66faf653-8f40-459a-b3bc-9cc814c46aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226620382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3226620382
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.4128526904
Short name T602
Test name
Test status
Simulation time 83723088 ps
CPU time 3.95 seconds
Started Apr 21 01:34:11 PM PDT 24
Finished Apr 21 01:34:15 PM PDT 24
Peak memory 214092 kb
Host smart-906b3587-4b76-4c39-8c3d-4702ba5d12e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128526904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.4128526904
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.667532629
Short name T413
Test name
Test status
Simulation time 316057146 ps
CPU time 32.51 seconds
Started Apr 21 01:34:08 PM PDT 24
Finished Apr 21 01:34:41 PM PDT 24
Peak memory 250776 kb
Host smart-e0d401f7-5da3-4769-87f5-bc3e3f73abe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667532629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.667532629
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1729808413
Short name T848
Test name
Test status
Simulation time 1453810728 ps
CPU time 11.5 seconds
Started Apr 21 01:34:19 PM PDT 24
Finished Apr 21 01:34:31 PM PDT 24
Peak memory 250832 kb
Host smart-5f04a319-7e15-4379-8edb-3c6226cbd9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729808413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1729808413
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.992644269
Short name T742
Test name
Test status
Simulation time 8240482466 ps
CPU time 127.16 seconds
Started Apr 21 01:34:12 PM PDT 24
Finished Apr 21 01:36:20 PM PDT 24
Peak memory 277156 kb
Host smart-c2247f7f-6eba-4ca7-8a8d-9873e569c736
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992644269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.992644269
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3146651591
Short name T323
Test name
Test status
Simulation time 33133171 ps
CPU time 0.83 seconds
Started Apr 21 01:34:11 PM PDT 24
Finished Apr 21 01:34:12 PM PDT 24
Peak memory 208476 kb
Host smart-54c51cdf-7802-4f50-a3a5-9d2c28819185
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146651591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3146651591
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4001915522
Short name T560
Test name
Test status
Simulation time 14544511 ps
CPU time 0.82 seconds
Started Apr 21 01:34:17 PM PDT 24
Finished Apr 21 01:34:18 PM PDT 24
Peak memory 209460 kb
Host smart-7c47decb-eb44-4942-8eb9-0f858b87372b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001915522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4001915522
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.223028355
Short name T783
Test name
Test status
Simulation time 372237011 ps
CPU time 12.76 seconds
Started Apr 21 01:34:15 PM PDT 24
Finished Apr 21 01:34:28 PM PDT 24
Peak memory 217728 kb
Host smart-bd5b0c4b-8628-481a-9f99-ebdea01589fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223028355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.223028355
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2304984538
Short name T562
Test name
Test status
Simulation time 216611743 ps
CPU time 3.19 seconds
Started Apr 21 01:34:18 PM PDT 24
Finished Apr 21 01:34:22 PM PDT 24
Peak memory 216992 kb
Host smart-eaf6715f-4521-4cf6-81ff-779fef0da05f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304984538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2304984538
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.4160020925
Short name T569
Test name
Test status
Simulation time 68768905 ps
CPU time 2.5 seconds
Started Apr 21 01:34:16 PM PDT 24
Finished Apr 21 01:34:19 PM PDT 24
Peak memory 217864 kb
Host smart-dab41f18-93aa-4374-9289-9488b3608fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160020925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4160020925
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3597870274
Short name T335
Test name
Test status
Simulation time 1024871032 ps
CPU time 9.44 seconds
Started Apr 21 01:34:17 PM PDT 24
Finished Apr 21 01:34:27 PM PDT 24
Peak memory 218016 kb
Host smart-0ab8e3b8-7e1b-4879-83f3-3d91b60520c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597870274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3597870274
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1489490330
Short name T683
Test name
Test status
Simulation time 1224863989 ps
CPU time 28.76 seconds
Started Apr 21 01:34:20 PM PDT 24
Finished Apr 21 01:34:49 PM PDT 24
Peak memory 217888 kb
Host smart-f7b197fc-1b1e-447d-a65e-64ad563d54f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489490330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1489490330
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2741175456
Short name T660
Test name
Test status
Simulation time 3763589977 ps
CPU time 9.95 seconds
Started Apr 21 01:34:19 PM PDT 24
Finished Apr 21 01:34:30 PM PDT 24
Peak memory 218020 kb
Host smart-f26f2b62-00db-43c6-b935-6307ad0920ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741175456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2741175456
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.59438440
Short name T60
Test name
Test status
Simulation time 1022443364 ps
CPU time 16.2 seconds
Started Apr 21 01:34:13 PM PDT 24
Finished Apr 21 01:34:30 PM PDT 24
Peak memory 225952 kb
Host smart-e324820b-ba55-4f69-843a-2f64191e97b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59438440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.59438440
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3665915280
Short name T551
Test name
Test status
Simulation time 55207726 ps
CPU time 2.31 seconds
Started Apr 21 01:34:17 PM PDT 24
Finished Apr 21 01:34:19 PM PDT 24
Peak memory 213896 kb
Host smart-522bdea3-1d9d-4645-8362-d12e5af95821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665915280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3665915280
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.919002515
Short name T97
Test name
Test status
Simulation time 232411797 ps
CPU time 23.28 seconds
Started Apr 21 01:34:17 PM PDT 24
Finished Apr 21 01:34:40 PM PDT 24
Peak memory 249316 kb
Host smart-1a18eedc-8a59-4def-bb88-bda4a8d017ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919002515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.919002515
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.4081695281
Short name T856
Test name
Test status
Simulation time 768033692 ps
CPU time 7.3 seconds
Started Apr 21 01:34:18 PM PDT 24
Finished Apr 21 01:34:26 PM PDT 24
Peak memory 250708 kb
Host smart-5cba4e07-b857-438e-b25f-d4c8e4b8d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081695281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4081695281
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.28026295
Short name T757
Test name
Test status
Simulation time 13001507905 ps
CPU time 192.68 seconds
Started Apr 21 01:34:18 PM PDT 24
Finished Apr 21 01:37:31 PM PDT 24
Peak memory 313272 kb
Host smart-1814a938-2f41-4e03-a1c8-6af52524f041
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28026295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.lc_ctrl_stress_all.28026295
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1167588297
Short name T425
Test name
Test status
Simulation time 48053362 ps
CPU time 1.04 seconds
Started Apr 21 01:34:16 PM PDT 24
Finished Apr 21 01:34:17 PM PDT 24
Peak memory 211548 kb
Host smart-5526486a-9b36-480b-a004-d4b030092464
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167588297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1167588297
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.848858202
Short name T692
Test name
Test status
Simulation time 32919923 ps
CPU time 0.9 seconds
Started Apr 21 01:34:25 PM PDT 24
Finished Apr 21 01:34:26 PM PDT 24
Peak memory 209396 kb
Host smart-ce6c40c8-d94f-4c4a-bf44-dbf2a3cdea15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848858202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.848858202
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3368963777
Short name T100
Test name
Test status
Simulation time 302369485 ps
CPU time 14.82 seconds
Started Apr 21 01:34:22 PM PDT 24
Finished Apr 21 01:34:37 PM PDT 24
Peak memory 217856 kb
Host smart-8442c6c9-f630-4b70-8504-32b464ce9752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368963777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3368963777
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3173382963
Short name T474
Test name
Test status
Simulation time 469228046 ps
CPU time 5.14 seconds
Started Apr 21 01:34:21 PM PDT 24
Finished Apr 21 01:34:26 PM PDT 24
Peak memory 209456 kb
Host smart-79ada622-662d-4636-bee8-af887e5d4c6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173382963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3173382963
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.33940529
Short name T735
Test name
Test status
Simulation time 118510675 ps
CPU time 2.19 seconds
Started Apr 21 01:34:23 PM PDT 24
Finished Apr 21 01:34:25 PM PDT 24
Peak memory 217800 kb
Host smart-11e2a11c-183c-471d-b76f-69a5f7568459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33940529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.33940529
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.977673133
Short name T386
Test name
Test status
Simulation time 472964400 ps
CPU time 10.49 seconds
Started Apr 21 01:34:21 PM PDT 24
Finished Apr 21 01:34:32 PM PDT 24
Peak memory 226028 kb
Host smart-aa5f50b8-b29a-462b-ae37-cf5ec619089d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977673133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.977673133
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3291186167
Short name T458
Test name
Test status
Simulation time 778302305 ps
CPU time 13.54 seconds
Started Apr 21 01:34:22 PM PDT 24
Finished Apr 21 01:34:36 PM PDT 24
Peak memory 217820 kb
Host smart-9985d68a-d3e9-4e9f-9a0d-411469612f2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291186167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3291186167
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.707575816
Short name T349
Test name
Test status
Simulation time 248535783 ps
CPU time 8.48 seconds
Started Apr 21 01:34:24 PM PDT 24
Finished Apr 21 01:34:33 PM PDT 24
Peak memory 217816 kb
Host smart-41585814-7e85-4894-bbbf-09078ab9267b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707575816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.707575816
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1652390227
Short name T382
Test name
Test status
Simulation time 848817976 ps
CPU time 9.88 seconds
Started Apr 21 01:34:21 PM PDT 24
Finished Apr 21 01:34:31 PM PDT 24
Peak memory 218048 kb
Host smart-3040b381-de1a-45a6-aa2e-eb78fd18312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652390227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1652390227
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3968645823
Short name T655
Test name
Test status
Simulation time 15615408 ps
CPU time 1.47 seconds
Started Apr 21 01:34:18 PM PDT 24
Finished Apr 21 01:34:20 PM PDT 24
Peak memory 213376 kb
Host smart-6295722b-bf65-4e7e-a466-a02cb7ea94c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968645823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3968645823
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2141403447
Short name T235
Test name
Test status
Simulation time 258568865 ps
CPU time 26.33 seconds
Started Apr 21 01:34:22 PM PDT 24
Finished Apr 21 01:34:48 PM PDT 24
Peak memory 250916 kb
Host smart-52701d6e-a2e1-4b9c-9354-7d0f7dd12390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141403447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2141403447
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2841488527
Short name T829
Test name
Test status
Simulation time 130849921 ps
CPU time 2.98 seconds
Started Apr 21 01:34:24 PM PDT 24
Finished Apr 21 01:34:27 PM PDT 24
Peak memory 221916 kb
Host smart-5ac35d9a-54c3-438e-9491-4fa8460e6805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841488527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2841488527
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3642905750
Short name T362
Test name
Test status
Simulation time 4422401649 ps
CPU time 88.12 seconds
Started Apr 21 01:34:23 PM PDT 24
Finished Apr 21 01:35:52 PM PDT 24
Peak memory 276276 kb
Host smart-4e09778a-26df-4737-90d6-160a3c09609f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642905750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3642905750
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2923199218
Short name T827
Test name
Test status
Simulation time 31621957880 ps
CPU time 2182.14 seconds
Started Apr 21 01:34:26 PM PDT 24
Finished Apr 21 02:10:49 PM PDT 24
Peak memory 967296 kb
Host smart-2e25d9aa-c00a-4c36-b62e-db395d309c88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2923199218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2923199218
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.975746247
Short name T322
Test name
Test status
Simulation time 24581253 ps
CPU time 1.14 seconds
Started Apr 21 01:34:20 PM PDT 24
Finished Apr 21 01:34:22 PM PDT 24
Peak memory 212672 kb
Host smart-7dcba49a-c2e2-4246-a58f-f851fb435fb3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975746247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.975746247
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3017442465
Short name T75
Test name
Test status
Simulation time 61456132 ps
CPU time 0.82 seconds
Started Apr 21 01:34:32 PM PDT 24
Finished Apr 21 01:34:33 PM PDT 24
Peak memory 209416 kb
Host smart-99c8d0d3-acf0-4d67-adb1-56c24fb1cf59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017442465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3017442465
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.493590338
Short name T673
Test name
Test status
Simulation time 192361275 ps
CPU time 7.64 seconds
Started Apr 21 01:34:27 PM PDT 24
Finished Apr 21 01:34:35 PM PDT 24
Peak memory 225976 kb
Host smart-1f4dfa3f-c57a-498a-a964-21ad4b4a86dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493590338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.493590338
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1198454759
Short name T672
Test name
Test status
Simulation time 942334416 ps
CPU time 12.63 seconds
Started Apr 21 01:34:30 PM PDT 24
Finished Apr 21 01:34:43 PM PDT 24
Peak memory 209416 kb
Host smart-d4d198e7-9f8e-47ab-a937-71091f45ec30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198454759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1198454759
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3663510476
Short name T749
Test name
Test status
Simulation time 62179167 ps
CPU time 2.05 seconds
Started Apr 21 01:34:27 PM PDT 24
Finished Apr 21 01:34:29 PM PDT 24
Peak memory 217948 kb
Host smart-7f7623ec-45f6-4616-8c65-9a942e32a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663510476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3663510476
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2188478763
Short name T842
Test name
Test status
Simulation time 266450030 ps
CPU time 13.65 seconds
Started Apr 21 01:34:28 PM PDT 24
Finished Apr 21 01:34:42 PM PDT 24
Peak memory 225944 kb
Host smart-b641b929-8ca0-4cc7-acaa-62cf92521ec1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188478763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2188478763
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3115906121
Short name T564
Test name
Test status
Simulation time 1098912693 ps
CPU time 12.24 seconds
Started Apr 21 01:34:27 PM PDT 24
Finished Apr 21 01:34:39 PM PDT 24
Peak memory 217832 kb
Host smart-bda285bd-af6b-421f-877e-411a540d7c48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115906121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3115906121
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2670149840
Short name T259
Test name
Test status
Simulation time 328223727 ps
CPU time 11.22 seconds
Started Apr 21 01:34:31 PM PDT 24
Finished Apr 21 01:34:42 PM PDT 24
Peak memory 217836 kb
Host smart-3d3b5f42-cd52-4563-b12f-ceb38d79861c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670149840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2670149840
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1773044453
Short name T214
Test name
Test status
Simulation time 2229218119 ps
CPU time 11.51 seconds
Started Apr 21 01:34:29 PM PDT 24
Finished Apr 21 01:34:41 PM PDT 24
Peak memory 218004 kb
Host smart-10ff8418-d91c-4499-b845-9e5652e0def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773044453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1773044453
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3248614530
Short name T366
Test name
Test status
Simulation time 532544086 ps
CPU time 2.7 seconds
Started Apr 21 01:34:24 PM PDT 24
Finished Apr 21 01:34:27 PM PDT 24
Peak memory 217772 kb
Host smart-86044668-a1d7-426b-a476-5918b9a948cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248614530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3248614530
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2667863598
Short name T817
Test name
Test status
Simulation time 319845157 ps
CPU time 31.22 seconds
Started Apr 21 01:34:25 PM PDT 24
Finished Apr 21 01:34:57 PM PDT 24
Peak memory 248520 kb
Host smart-64090117-3e6f-4e27-ab48-474074be604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667863598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2667863598
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1304481449
Short name T738
Test name
Test status
Simulation time 300299727 ps
CPU time 7.29 seconds
Started Apr 21 01:34:29 PM PDT 24
Finished Apr 21 01:34:37 PM PDT 24
Peak memory 246408 kb
Host smart-dfa5f6f7-6dc9-4597-a8f3-72b7a5dd1831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304481449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1304481449
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3263593535
Short name T568
Test name
Test status
Simulation time 27095888163 ps
CPU time 49.44 seconds
Started Apr 21 01:34:31 PM PDT 24
Finished Apr 21 01:35:21 PM PDT 24
Peak memory 226052 kb
Host smart-c75b889c-c4f4-4b06-a562-c9a7ef1db2ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263593535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3263593535
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1518070548
Short name T583
Test name
Test status
Simulation time 48860611 ps
CPU time 0.82 seconds
Started Apr 21 01:34:23 PM PDT 24
Finished Apr 21 01:34:24 PM PDT 24
Peak memory 208572 kb
Host smart-da62fa44-eac5-4295-beb1-26b5cb3ff444
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518070548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1518070548
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2325158243
Short name T585
Test name
Test status
Simulation time 14027114 ps
CPU time 0.82 seconds
Started Apr 21 01:34:36 PM PDT 24
Finished Apr 21 01:34:37 PM PDT 24
Peak memory 209340 kb
Host smart-cf661c27-169e-44e6-b099-458a12295f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325158243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2325158243
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1592173823
Short name T838
Test name
Test status
Simulation time 636633341 ps
CPU time 16.72 seconds
Started Apr 21 01:34:30 PM PDT 24
Finished Apr 21 01:34:47 PM PDT 24
Peak memory 217824 kb
Host smart-cb097751-da0d-4376-9c7e-de61ad6eba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592173823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1592173823
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.4256789524
Short name T798
Test name
Test status
Simulation time 1383625748 ps
CPU time 4.99 seconds
Started Apr 21 01:34:35 PM PDT 24
Finished Apr 21 01:34:41 PM PDT 24
Peak memory 217128 kb
Host smart-f009695b-92f1-4101-b67c-b5e4131cb29c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256789524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.4256789524
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2301037490
Short name T613
Test name
Test status
Simulation time 20505364 ps
CPU time 1.54 seconds
Started Apr 21 01:34:32 PM PDT 24
Finished Apr 21 01:34:34 PM PDT 24
Peak memory 217824 kb
Host smart-b43d8f32-c787-4311-81c5-b9250b9e6e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301037490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2301037490
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1019939792
Short name T354
Test name
Test status
Simulation time 284665525 ps
CPU time 12.71 seconds
Started Apr 21 01:34:32 PM PDT 24
Finished Apr 21 01:34:45 PM PDT 24
Peak memory 218796 kb
Host smart-93439725-a5c6-4a54-9ace-e12b03d6d490
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019939792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1019939792
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.97273590
Short name T643
Test name
Test status
Simulation time 1379325647 ps
CPU time 12.26 seconds
Started Apr 21 01:34:35 PM PDT 24
Finished Apr 21 01:34:48 PM PDT 24
Peak memory 217968 kb
Host smart-66d9739f-1293-4a41-9723-dcec7f693d9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97273590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_dig
est.97273590
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3806464756
Short name T774
Test name
Test status
Simulation time 865819680 ps
CPU time 9.42 seconds
Started Apr 21 01:34:33 PM PDT 24
Finished Apr 21 01:34:43 PM PDT 24
Peak memory 217860 kb
Host smart-fb45a357-8101-419e-b454-3dd685b39058
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806464756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3806464756
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.661231605
Short name T653
Test name
Test status
Simulation time 1739030612 ps
CPU time 12.36 seconds
Started Apr 21 01:34:30 PM PDT 24
Finished Apr 21 01:34:43 PM PDT 24
Peak memory 224556 kb
Host smart-4e6356c9-619e-4142-8340-3223dfaf529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661231605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.661231605
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2291821771
Short name T277
Test name
Test status
Simulation time 31957626 ps
CPU time 1.6 seconds
Started Apr 21 01:34:34 PM PDT 24
Finished Apr 21 01:34:36 PM PDT 24
Peak memory 213480 kb
Host smart-22abeff0-cbce-4f15-a0d2-12dc2faf2037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291821771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2291821771
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2308422651
Short name T296
Test name
Test status
Simulation time 982904159 ps
CPU time 24.2 seconds
Started Apr 21 01:34:31 PM PDT 24
Finished Apr 21 01:34:56 PM PDT 24
Peak memory 250816 kb
Host smart-94f6fe4f-62b3-4f16-b6fe-43423f12ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308422651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2308422651
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.449774267
Short name T736
Test name
Test status
Simulation time 228992486 ps
CPU time 5.77 seconds
Started Apr 21 01:34:32 PM PDT 24
Finished Apr 21 01:34:38 PM PDT 24
Peak memory 245508 kb
Host smart-eddff851-344f-4af9-b589-b5682fc2ba83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449774267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.449774267
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.792801885
Short name T82
Test name
Test status
Simulation time 1398057069 ps
CPU time 54.82 seconds
Started Apr 21 01:34:37 PM PDT 24
Finished Apr 21 01:35:32 PM PDT 24
Peak memory 252304 kb
Host smart-f3e8f93d-4451-425b-91db-44b0b70456b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792801885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.792801885
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3780899329
Short name T751
Test name
Test status
Simulation time 2980538914 ps
CPU time 72.92 seconds
Started Apr 21 01:34:33 PM PDT 24
Finished Apr 21 01:35:46 PM PDT 24
Peak memory 269252 kb
Host smart-41a5f2ab-28b6-47b9-b8a7-5e35e37a766b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3780899329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.3780899329
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2809451508
Short name T441
Test name
Test status
Simulation time 36954008 ps
CPU time 0.9 seconds
Started Apr 21 01:34:31 PM PDT 24
Finished Apr 21 01:34:33 PM PDT 24
Peak memory 211504 kb
Host smart-8896714f-0ef2-43af-8b47-716db80ab72e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809451508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2809451508
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4126302213
Short name T823
Test name
Test status
Simulation time 24975794 ps
CPU time 0.83 seconds
Started Apr 21 01:34:39 PM PDT 24
Finished Apr 21 01:34:40 PM PDT 24
Peak memory 209324 kb
Host smart-78590033-f042-438c-b5b1-0cc243ea2ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126302213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4126302213
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1887051498
Short name T258
Test name
Test status
Simulation time 888913477 ps
CPU time 9.91 seconds
Started Apr 21 01:34:35 PM PDT 24
Finished Apr 21 01:34:45 PM PDT 24
Peak memory 217888 kb
Host smart-c6802d2f-c805-4234-8fc0-c97466d30567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887051498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1887051498
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2678116359
Short name T500
Test name
Test status
Simulation time 1507620494 ps
CPU time 12.08 seconds
Started Apr 21 01:34:39 PM PDT 24
Finished Apr 21 01:34:51 PM PDT 24
Peak memory 209380 kb
Host smart-e9ee0476-24d5-43b4-a944-c364d60a32d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678116359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2678116359
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2965796364
Short name T16
Test name
Test status
Simulation time 891796677 ps
CPU time 2.87 seconds
Started Apr 21 01:34:35 PM PDT 24
Finished Apr 21 01:34:39 PM PDT 24
Peak memory 217848 kb
Host smart-f9427def-5dd0-4fd3-8f48-d6f007bafd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965796364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2965796364
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2625925505
Short name T268
Test name
Test status
Simulation time 502763641 ps
CPU time 14.96 seconds
Started Apr 21 01:34:36 PM PDT 24
Finished Apr 21 01:34:52 PM PDT 24
Peak memory 219044 kb
Host smart-c3749722-9f74-42c7-a05f-cbc4c24181cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625925505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2625925505
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.299373021
Short name T371
Test name
Test status
Simulation time 550858338 ps
CPU time 8.93 seconds
Started Apr 21 01:34:39 PM PDT 24
Finished Apr 21 01:34:48 PM PDT 24
Peak memory 217812 kb
Host smart-0e0cbb45-751d-454a-827a-85cafbcaa0b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299373021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.299373021
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2842332340
Short name T517
Test name
Test status
Simulation time 2590650342 ps
CPU time 11.94 seconds
Started Apr 21 01:34:36 PM PDT 24
Finished Apr 21 01:34:48 PM PDT 24
Peak memory 218024 kb
Host smart-df18b88c-5421-4c38-967d-0d69811c5bea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842332340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2842332340
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3546748610
Short name T503
Test name
Test status
Simulation time 720015539 ps
CPU time 9.2 seconds
Started Apr 21 01:34:39 PM PDT 24
Finished Apr 21 01:34:49 PM PDT 24
Peak memory 217928 kb
Host smart-53ad061f-bf81-4b54-854d-85bee7fd66c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546748610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3546748610
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.596661975
Short name T67
Test name
Test status
Simulation time 83619126 ps
CPU time 2.96 seconds
Started Apr 21 01:34:36 PM PDT 24
Finished Apr 21 01:34:39 PM PDT 24
Peak memory 217800 kb
Host smart-8576ec1a-5381-42fd-a6a0-383e2c86c190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596661975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.596661975
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1824078904
Short name T511
Test name
Test status
Simulation time 2472581669 ps
CPU time 22.98 seconds
Started Apr 21 01:34:33 PM PDT 24
Finished Apr 21 01:34:56 PM PDT 24
Peak memory 246040 kb
Host smart-df8d82a0-21fd-435a-8fc9-aac32bf869a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824078904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1824078904
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.128015771
Short name T835
Test name
Test status
Simulation time 414784836 ps
CPU time 6.13 seconds
Started Apr 21 01:34:37 PM PDT 24
Finished Apr 21 01:34:43 PM PDT 24
Peak memory 250832 kb
Host smart-a5f935fe-58bf-408f-aedc-ce1a1042b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128015771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.128015771
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1295541629
Short name T56
Test name
Test status
Simulation time 15434751313 ps
CPU time 125.48 seconds
Started Apr 21 01:34:40 PM PDT 24
Finished Apr 21 01:36:45 PM PDT 24
Peak memory 280948 kb
Host smart-90ae9bed-b912-4e8d-a281-9384f6461297
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295541629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1295541629
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.47637098
Short name T324
Test name
Test status
Simulation time 13205254 ps
CPU time 0.97 seconds
Started Apr 21 01:34:39 PM PDT 24
Finished Apr 21 01:34:40 PM PDT 24
Peak memory 208536 kb
Host smart-1229bcf0-f75e-4807-adf2-a4ddc6afaa71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47637098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctr
l_volatile_unlock_smoke.47637098
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.24466141
Short name T94
Test name
Test status
Simulation time 50112054 ps
CPU time 0.92 seconds
Started Apr 21 01:34:51 PM PDT 24
Finished Apr 21 01:34:52 PM PDT 24
Peak memory 209380 kb
Host smart-b0c9d03b-ec36-4715-acf0-0d1ab4793089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24466141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.24466141
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2333669298
Short name T809
Test name
Test status
Simulation time 697403729 ps
CPU time 15.15 seconds
Started Apr 21 01:34:41 PM PDT 24
Finished Apr 21 01:34:57 PM PDT 24
Peak memory 217852 kb
Host smart-e4090ec1-7ea4-48d7-92b3-6db82fc56454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333669298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2333669298
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2717422239
Short name T777
Test name
Test status
Simulation time 2971993061 ps
CPU time 7.02 seconds
Started Apr 21 01:34:43 PM PDT 24
Finished Apr 21 01:34:50 PM PDT 24
Peak memory 209576 kb
Host smart-93de792c-e1db-4226-b91b-06281eca15a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717422239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2717422239
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3032579343
Short name T539
Test name
Test status
Simulation time 119872506 ps
CPU time 1.8 seconds
Started Apr 21 01:34:40 PM PDT 24
Finished Apr 21 01:34:42 PM PDT 24
Peak memory 217876 kb
Host smart-9cd62a14-c365-4287-ab95-e947d26e92d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032579343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3032579343
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3802237789
Short name T238
Test name
Test status
Simulation time 2336837055 ps
CPU time 14.41 seconds
Started Apr 21 01:34:45 PM PDT 24
Finished Apr 21 01:35:00 PM PDT 24
Peak memory 218120 kb
Host smart-3091f79f-ac2e-4561-bbce-02054ed149dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802237789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3802237789
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3863423926
Short name T66
Test name
Test status
Simulation time 4365325438 ps
CPU time 10.41 seconds
Started Apr 21 01:34:48 PM PDT 24
Finished Apr 21 01:34:59 PM PDT 24
Peak memory 218080 kb
Host smart-88873e76-eee8-460d-bad4-17574e6de56e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863423926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3863423926
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1971106793
Short name T805
Test name
Test status
Simulation time 487056740 ps
CPU time 10.31 seconds
Started Apr 21 01:34:45 PM PDT 24
Finished Apr 21 01:34:56 PM PDT 24
Peak memory 217828 kb
Host smart-b6ccdeb6-013e-49da-92d4-e2e3408501f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971106793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1971106793
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2784273194
Short name T559
Test name
Test status
Simulation time 283891689 ps
CPU time 10.08 seconds
Started Apr 21 01:34:45 PM PDT 24
Finished Apr 21 01:34:56 PM PDT 24
Peak memory 217912 kb
Host smart-cce9b903-474b-4c63-a9ed-fe0a17f30b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784273194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2784273194
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3357723924
Short name T80
Test name
Test status
Simulation time 71587697 ps
CPU time 2.68 seconds
Started Apr 21 01:34:41 PM PDT 24
Finished Apr 21 01:34:44 PM PDT 24
Peak memory 217720 kb
Host smart-38ce562c-e442-4f9b-b929-64f113401890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357723924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3357723924
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2476904942
Short name T861
Test name
Test status
Simulation time 555793002 ps
CPU time 24.38 seconds
Started Apr 21 01:34:43 PM PDT 24
Finished Apr 21 01:35:08 PM PDT 24
Peak memory 250024 kb
Host smart-a8811a4b-345d-49d9-9b45-209bceff3d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476904942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2476904942
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1570245457
Short name T794
Test name
Test status
Simulation time 317120087 ps
CPU time 7.9 seconds
Started Apr 21 01:34:42 PM PDT 24
Finished Apr 21 01:34:50 PM PDT 24
Peak memory 242640 kb
Host smart-08cda357-f6f3-47c8-87d4-4184718232d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570245457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1570245457
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1313205238
Short name T406
Test name
Test status
Simulation time 1781295394 ps
CPU time 50.95 seconds
Started Apr 21 01:34:48 PM PDT 24
Finished Apr 21 01:35:39 PM PDT 24
Peak memory 225688 kb
Host smart-b57bc330-a70b-475a-b549-52db4e6d8b1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313205238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1313205238
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.4075333489
Short name T584
Test name
Test status
Simulation time 12951429158 ps
CPU time 438.55 seconds
Started Apr 21 01:35:01 PM PDT 24
Finished Apr 21 01:42:20 PM PDT 24
Peak memory 281936 kb
Host smart-b441c971-cbb8-4664-a0c1-31a3f52cad4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4075333489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.4075333489
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3316218279
Short name T181
Test name
Test status
Simulation time 12290049 ps
CPU time 0.78 seconds
Started Apr 21 01:34:41 PM PDT 24
Finished Apr 21 01:34:42 PM PDT 24
Peak memory 208436 kb
Host smart-fcf13225-747c-490b-954a-edd8fdde9671
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316218279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3316218279
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3370886198
Short name T77
Test name
Test status
Simulation time 38375167 ps
CPU time 1.03 seconds
Started Apr 21 01:30:43 PM PDT 24
Finished Apr 21 01:30:44 PM PDT 24
Peak memory 209448 kb
Host smart-4542ffcc-4bf7-4ee0-87af-7a9129e8998f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370886198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3370886198
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2419361949
Short name T703
Test name
Test status
Simulation time 14055840 ps
CPU time 0.81 seconds
Started Apr 21 01:30:47 PM PDT 24
Finished Apr 21 01:30:48 PM PDT 24
Peak memory 209328 kb
Host smart-9828ce2f-4caf-4248-9664-7b1d4c5b5dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419361949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2419361949
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.165259340
Short name T537
Test name
Test status
Simulation time 410540003 ps
CPU time 13.87 seconds
Started Apr 21 01:30:39 PM PDT 24
Finished Apr 21 01:30:53 PM PDT 24
Peak memory 217868 kb
Host smart-5e99559e-f2f2-4bf5-866e-c57fdfdb57c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165259340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.165259340
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1894763502
Short name T31
Test name
Test status
Simulation time 196633052 ps
CPU time 5.52 seconds
Started Apr 21 01:30:40 PM PDT 24
Finished Apr 21 01:30:46 PM PDT 24
Peak memory 216888 kb
Host smart-b0396769-59fc-4b0a-b307-b7576136970e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894763502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1894763502
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.209012049
Short name T300
Test name
Test status
Simulation time 1122502318 ps
CPU time 17.09 seconds
Started Apr 21 01:30:40 PM PDT 24
Finished Apr 21 01:30:57 PM PDT 24
Peak memory 217780 kb
Host smart-776b0ee7-b453-4579-b281-0f5b4af1c0d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209012049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.209012049
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.4126430707
Short name T71
Test name
Test status
Simulation time 3982721732 ps
CPU time 14.07 seconds
Started Apr 21 01:30:43 PM PDT 24
Finished Apr 21 01:30:57 PM PDT 24
Peak memory 217740 kb
Host smart-891ef960-0d9b-4133-bec7-46b906e43e16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126430707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.4
126430707
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2055689174
Short name T586
Test name
Test status
Simulation time 1033566324 ps
CPU time 5.49 seconds
Started Apr 21 01:30:46 PM PDT 24
Finished Apr 21 01:30:52 PM PDT 24
Peak memory 217836 kb
Host smart-b77e317d-1c38-4ee7-892d-0f783121d206
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055689174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2055689174
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1088507150
Short name T601
Test name
Test status
Simulation time 2436955481 ps
CPU time 8.81 seconds
Started Apr 21 01:30:45 PM PDT 24
Finished Apr 21 01:30:54 PM PDT 24
Peak memory 213060 kb
Host smart-f6ed131f-ad0c-4fc6-8f67-ca3fa2b16d8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088507150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1088507150
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4174002439
Short name T337
Test name
Test status
Simulation time 919651508 ps
CPU time 3.9 seconds
Started Apr 21 01:30:40 PM PDT 24
Finished Apr 21 01:30:44 PM PDT 24
Peak memory 213180 kb
Host smart-98e3c329-ba77-43c8-83b1-9f60ddf13a99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174002439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
4174002439
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1472505371
Short name T297
Test name
Test status
Simulation time 1565463244 ps
CPU time 37.49 seconds
Started Apr 21 01:30:46 PM PDT 24
Finished Apr 21 01:31:24 PM PDT 24
Peak memory 250756 kb
Host smart-4f7c4102-ad64-4093-b84b-69ac06112911
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472505371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1472505371
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2131883839
Short name T261
Test name
Test status
Simulation time 2245919467 ps
CPU time 13.87 seconds
Started Apr 21 01:30:48 PM PDT 24
Finished Apr 21 01:31:02 PM PDT 24
Peak memory 222660 kb
Host smart-07952ec7-35fc-4dff-84fa-0cd714b9c88c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131883839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2131883839
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.576765749
Short name T37
Test name
Test status
Simulation time 28766970 ps
CPU time 1.68 seconds
Started Apr 21 01:30:38 PM PDT 24
Finished Apr 21 01:30:40 PM PDT 24
Peak memory 217816 kb
Host smart-33bf4ab7-ab08-413d-9efc-c0ae89f9834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576765749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.576765749
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2244720275
Short name T464
Test name
Test status
Simulation time 210893009 ps
CPU time 5.16 seconds
Started Apr 21 01:30:40 PM PDT 24
Finished Apr 21 01:30:45 PM PDT 24
Peak memory 217608 kb
Host smart-7ce10e6e-a40c-4f92-889d-6e198c742b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244720275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2244720275
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1552256880
Short name T837
Test name
Test status
Simulation time 456627287 ps
CPU time 18.67 seconds
Started Apr 21 01:30:43 PM PDT 24
Finished Apr 21 01:31:02 PM PDT 24
Peak memory 225948 kb
Host smart-336b0f5f-1a45-491b-9764-22953241bb66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552256880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1552256880
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.283289002
Short name T434
Test name
Test status
Simulation time 1599341544 ps
CPU time 14.73 seconds
Started Apr 21 01:30:43 PM PDT 24
Finished Apr 21 01:30:58 PM PDT 24
Peak memory 217880 kb
Host smart-c3539eb4-f2a5-44a3-ae79-dc0bb6201474
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283289002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.283289002
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3876041342
Short name T666
Test name
Test status
Simulation time 1679781900 ps
CPU time 11.4 seconds
Started Apr 21 01:30:45 PM PDT 24
Finished Apr 21 01:30:56 PM PDT 24
Peak memory 217872 kb
Host smart-9d0ca981-608c-473b-99c0-1f585679099a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876041342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
876041342
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4113964278
Short name T312
Test name
Test status
Simulation time 264922378 ps
CPU time 8.61 seconds
Started Apr 21 01:30:38 PM PDT 24
Finished Apr 21 01:30:47 PM PDT 24
Peak memory 217936 kb
Host smart-da20e77e-43c2-4750-9315-f357ad43fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113964278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4113964278
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1998205397
Short name T728
Test name
Test status
Simulation time 159530927 ps
CPU time 4.6 seconds
Started Apr 21 01:30:46 PM PDT 24
Finished Apr 21 01:30:51 PM PDT 24
Peak memory 217836 kb
Host smart-a22136ef-6b09-445a-9f32-d33bacf56180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998205397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1998205397
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.4197793541
Short name T421
Test name
Test status
Simulation time 237882526 ps
CPU time 16.37 seconds
Started Apr 21 01:30:45 PM PDT 24
Finished Apr 21 01:31:02 PM PDT 24
Peak memory 248432 kb
Host smart-56fc0718-8873-409b-b7b6-4c5b5ff662db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197793541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4197793541
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1682175437
Short name T221
Test name
Test status
Simulation time 286300924 ps
CPU time 7.51 seconds
Started Apr 21 01:30:46 PM PDT 24
Finished Apr 21 01:30:53 PM PDT 24
Peak memory 250388 kb
Host smart-49454a81-a2d7-4e73-b217-8f3282bb5fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682175437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1682175437
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2110111618
Short name T278
Test name
Test status
Simulation time 6113736757 ps
CPU time 122.55 seconds
Started Apr 21 01:30:43 PM PDT 24
Finished Apr 21 01:32:45 PM PDT 24
Peak memory 265860 kb
Host smart-89a31d41-6a61-4889-bc7d-3f5ee22726db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110111618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2110111618
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3617907613
Short name T17
Test name
Test status
Simulation time 73599668 ps
CPU time 1.19 seconds
Started Apr 21 01:30:46 PM PDT 24
Finished Apr 21 01:30:47 PM PDT 24
Peak memory 212504 kb
Host smart-51d2eb5e-490a-4df3-a722-6c724359676c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617907613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3617907613
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2488879476
Short name T396
Test name
Test status
Simulation time 236457180 ps
CPU time 0.91 seconds
Started Apr 21 01:30:51 PM PDT 24
Finished Apr 21 01:30:52 PM PDT 24
Peak memory 209432 kb
Host smart-1417038c-085b-4b23-8919-e40b7d212013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488879476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2488879476
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.979744947
Short name T463
Test name
Test status
Simulation time 9915001 ps
CPU time 0.8 seconds
Started Apr 21 01:30:45 PM PDT 24
Finished Apr 21 01:30:46 PM PDT 24
Peak memory 209364 kb
Host smart-e0d464b7-b2a4-4556-9e8e-c72944143306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979744947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.979744947
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3850591573
Short name T813
Test name
Test status
Simulation time 947277355 ps
CPU time 10.34 seconds
Started Apr 21 01:30:49 PM PDT 24
Finished Apr 21 01:31:00 PM PDT 24
Peak memory 217856 kb
Host smart-7c8e95c1-df17-4932-9543-47b6733ac50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850591573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3850591573
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1203360899
Short name T409
Test name
Test status
Simulation time 373109548 ps
CPU time 4.84 seconds
Started Apr 21 01:30:48 PM PDT 24
Finished Apr 21 01:30:53 PM PDT 24
Peak memory 209484 kb
Host smart-8abd2d08-5eae-4b97-865a-c0e30aefd591
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203360899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1203360899
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.11228005
Short name T479
Test name
Test status
Simulation time 6098610721 ps
CPU time 46.59 seconds
Started Apr 21 01:30:47 PM PDT 24
Finished Apr 21 01:31:34 PM PDT 24
Peak memory 219472 kb
Host smart-c58e95f7-170c-42c9-80f2-889b62f21363
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11228005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_erro
rs.11228005
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.962953088
Short name T778
Test name
Test status
Simulation time 1294876176 ps
CPU time 4.57 seconds
Started Apr 21 01:30:47 PM PDT 24
Finished Apr 21 01:30:52 PM PDT 24
Peak memory 217672 kb
Host smart-bb5ba52a-5dd3-4ba4-9b4c-38f785ba34e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962953088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.962953088
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4052895078
Short name T478
Test name
Test status
Simulation time 15336570856 ps
CPU time 25.94 seconds
Started Apr 21 01:30:47 PM PDT 24
Finished Apr 21 01:31:14 PM PDT 24
Peak memory 218828 kb
Host smart-e1b71d67-865f-49ba-b383-3491e8c00a52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052895078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.4052895078
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.71997786
Short name T86
Test name
Test status
Simulation time 2821163363 ps
CPU time 19.91 seconds
Started Apr 21 01:30:47 PM PDT 24
Finished Apr 21 01:31:07 PM PDT 24
Peak memory 213076 kb
Host smart-d60e2aad-a21f-4ae6-898b-c40d1433f59b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71997786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt
ag_regwen_during_op.71997786
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1941355998
Short name T524
Test name
Test status
Simulation time 1302364993 ps
CPU time 4.56 seconds
Started Apr 21 01:30:49 PM PDT 24
Finished Apr 21 01:30:54 PM PDT 24
Peak memory 213264 kb
Host smart-690658f3-8e90-436e-97c1-1b234af9bf42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941355998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1941355998
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1029848355
Short name T417
Test name
Test status
Simulation time 1976813217 ps
CPU time 52.44 seconds
Started Apr 21 01:30:49 PM PDT 24
Finished Apr 21 01:31:42 PM PDT 24
Peak memory 274340 kb
Host smart-daf9f4cf-82e0-4e21-8b93-a7c6aec01650
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029848355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1029848355
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.629411549
Short name T102
Test name
Test status
Simulation time 403260779 ps
CPU time 16.99 seconds
Started Apr 21 01:30:47 PM PDT 24
Finished Apr 21 01:31:04 PM PDT 24
Peak memory 250780 kb
Host smart-021a46f3-fd96-4d3a-90a6-4977fe8a0b4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629411549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.629411549
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3694105895
Short name T762
Test name
Test status
Simulation time 65491394 ps
CPU time 2.49 seconds
Started Apr 21 01:30:49 PM PDT 24
Finished Apr 21 01:30:52 PM PDT 24
Peak memory 218004 kb
Host smart-534f0d78-4a13-482c-824e-245af7e5989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694105895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3694105895
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2170120926
Short name T860
Test name
Test status
Simulation time 678310593 ps
CPU time 5.82 seconds
Started Apr 21 01:30:48 PM PDT 24
Finished Apr 21 01:30:54 PM PDT 24
Peak memory 214020 kb
Host smart-caa7d46b-825e-44c3-9275-6aed735362b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170120926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2170120926
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1660996338
Short name T416
Test name
Test status
Simulation time 347315821 ps
CPU time 16.91 seconds
Started Apr 21 01:30:47 PM PDT 24
Finished Apr 21 01:31:05 PM PDT 24
Peak memory 225924 kb
Host smart-299022c4-8892-4b85-9b17-9d0a8c1fcab7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660996338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1660996338
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4249356465
Short name T219
Test name
Test status
Simulation time 408093507 ps
CPU time 11.8 seconds
Started Apr 21 01:30:51 PM PDT 24
Finished Apr 21 01:31:03 PM PDT 24
Peak memory 217872 kb
Host smart-0721e28a-9410-4c42-b00d-7ac6aa7f08d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249356465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4249356465
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.7021812
Short name T489
Test name
Test status
Simulation time 1309903233 ps
CPU time 7.88 seconds
Started Apr 21 01:30:49 PM PDT 24
Finished Apr 21 01:30:58 PM PDT 24
Peak memory 217928 kb
Host smart-f23c69ec-bf80-4afd-85a1-46744de0799a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7021812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.7021812
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1166593913
Short name T363
Test name
Test status
Simulation time 2022671264 ps
CPU time 11.75 seconds
Started Apr 21 01:30:49 PM PDT 24
Finished Apr 21 01:31:01 PM PDT 24
Peak memory 217940 kb
Host smart-9214d5e0-b608-496d-8358-c89342951e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166593913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1166593913
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.934705458
Short name T498
Test name
Test status
Simulation time 61824087 ps
CPU time 1.71 seconds
Started Apr 21 01:30:43 PM PDT 24
Finished Apr 21 01:30:45 PM PDT 24
Peak memory 213656 kb
Host smart-f72324a6-97bf-44cb-8be6-046bf90f58cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934705458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.934705458
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.895360915
Short name T845
Test name
Test status
Simulation time 880369744 ps
CPU time 23.19 seconds
Started Apr 21 01:30:45 PM PDT 24
Finished Apr 21 01:31:09 PM PDT 24
Peak memory 248192 kb
Host smart-cdbdf4ce-2375-4b0f-8a89-40973321b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895360915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.895360915
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.972721202
Short name T279
Test name
Test status
Simulation time 368121460 ps
CPU time 7.38 seconds
Started Apr 21 01:30:47 PM PDT 24
Finished Apr 21 01:30:55 PM PDT 24
Peak memory 250844 kb
Host smart-c023af13-be37-4506-ab42-5015139c74d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972721202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.972721202
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1140360304
Short name T39
Test name
Test status
Simulation time 5453148607 ps
CPU time 164.56 seconds
Started Apr 21 01:30:49 PM PDT 24
Finished Apr 21 01:33:34 PM PDT 24
Peak memory 250996 kb
Host smart-f4ee5405-7fad-4af3-bfa8-74450e84301f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140360304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1140360304
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3637236156
Short name T55
Test name
Test status
Simulation time 91832338518 ps
CPU time 556.38 seconds
Started Apr 21 01:30:49 PM PDT 24
Finished Apr 21 01:40:05 PM PDT 24
Peak memory 349468 kb
Host smart-b2b01a18-3409-4545-a0c0-06e9bab81b99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3637236156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3637236156
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2972075318
Short name T304
Test name
Test status
Simulation time 43921339 ps
CPU time 0.86 seconds
Started Apr 21 01:30:45 PM PDT 24
Finished Apr 21 01:30:46 PM PDT 24
Peak memory 212472 kb
Host smart-a885f491-d512-4649-90cb-12452d4ca3ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972075318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2972075318
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.64248734
Short name T657
Test name
Test status
Simulation time 21384038 ps
CPU time 0.94 seconds
Started Apr 21 01:31:02 PM PDT 24
Finished Apr 21 01:31:03 PM PDT 24
Peak memory 209440 kb
Host smart-cbba2446-65a7-4593-a884-0c6a2a2875dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64248734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.64248734
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2782893693
Short name T571
Test name
Test status
Simulation time 282523180 ps
CPU time 13.37 seconds
Started Apr 21 01:30:53 PM PDT 24
Finished Apr 21 01:31:07 PM PDT 24
Peak memory 217824 kb
Host smart-edbb8d23-45e7-472e-a93d-dd4e0d1879f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782893693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2782893693
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2691632002
Short name T755
Test name
Test status
Simulation time 5543506083 ps
CPU time 8.35 seconds
Started Apr 21 01:30:54 PM PDT 24
Finished Apr 21 01:31:03 PM PDT 24
Peak memory 209568 kb
Host smart-c8292024-4944-409b-a4e8-901b435888b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691632002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2691632002
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3048401428
Short name T522
Test name
Test status
Simulation time 4896410819 ps
CPU time 52.08 seconds
Started Apr 21 01:30:53 PM PDT 24
Finished Apr 21 01:31:45 PM PDT 24
Peak memory 217988 kb
Host smart-eb98443d-e5de-468e-b9f2-9c3bc3357fed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048401428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3048401428
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.88903486
Short name T6
Test name
Test status
Simulation time 3046244772 ps
CPU time 6.32 seconds
Started Apr 21 01:30:58 PM PDT 24
Finished Apr 21 01:31:05 PM PDT 24
Peak memory 217460 kb
Host smart-8a54dfb0-0a5c-4240-aafd-6cbb48ceedf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88903486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.88903486
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.828361311
Short name T752
Test name
Test status
Simulation time 280218013 ps
CPU time 8.74 seconds
Started Apr 21 01:30:52 PM PDT 24
Finished Apr 21 01:31:02 PM PDT 24
Peak memory 217816 kb
Host smart-0b6f5c9c-4e5b-4857-9a2c-cfbe47e3e4f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828361311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.828361311
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1974816528
Short name T799
Test name
Test status
Simulation time 1141507649 ps
CPU time 31.1 seconds
Started Apr 21 01:31:00 PM PDT 24
Finished Apr 21 01:31:31 PM PDT 24
Peak memory 213160 kb
Host smart-0eb7d2b1-60d0-4c25-b8ab-bd524b47dbc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974816528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1974816528
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.17667719
Short name T89
Test name
Test status
Simulation time 2819191446 ps
CPU time 9.12 seconds
Started Apr 21 01:30:53 PM PDT 24
Finished Apr 21 01:31:03 PM PDT 24
Peak memory 214152 kb
Host smart-66f64acf-59d5-4b3b-b028-fdfaf6adee11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17667719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.17667719
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3599812037
Short name T411
Test name
Test status
Simulation time 1330151934 ps
CPU time 62.74 seconds
Started Apr 21 01:30:52 PM PDT 24
Finished Apr 21 01:31:55 PM PDT 24
Peak memory 268216 kb
Host smart-3c14ce59-c84f-475f-8a7b-52b7009bf6ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599812037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3599812037
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.835861819
Short name T636
Test name
Test status
Simulation time 1030339608 ps
CPU time 10.29 seconds
Started Apr 21 01:30:54 PM PDT 24
Finished Apr 21 01:31:05 PM PDT 24
Peak memory 249988 kb
Host smart-6b006997-d44f-416a-b2b9-a0e73f1be50a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835861819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.835861819
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1809915013
Short name T725
Test name
Test status
Simulation time 35367373 ps
CPU time 2.35 seconds
Started Apr 21 01:30:50 PM PDT 24
Finished Apr 21 01:30:52 PM PDT 24
Peak memory 217960 kb
Host smart-9510d1e4-6cc8-4bd0-92d1-bca92f0db9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809915013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1809915013
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.605407313
Short name T506
Test name
Test status
Simulation time 3418188012 ps
CPU time 15.68 seconds
Started Apr 21 01:30:53 PM PDT 24
Finished Apr 21 01:31:09 PM PDT 24
Peak memory 217852 kb
Host smart-f8960913-8b56-4cbc-aaea-ab4f38341991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605407313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.605407313
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1424569872
Short name T727
Test name
Test status
Simulation time 1896937346 ps
CPU time 14.72 seconds
Started Apr 21 01:30:59 PM PDT 24
Finished Apr 21 01:31:14 PM PDT 24
Peak memory 218788 kb
Host smart-94b5e85f-c2d1-4bd0-8f58-f2adfcaacc5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424569872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1424569872
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.48070726
Short name T288
Test name
Test status
Simulation time 807100832 ps
CPU time 20.84 seconds
Started Apr 21 01:30:58 PM PDT 24
Finished Apr 21 01:31:19 PM PDT 24
Peak memory 217884 kb
Host smart-350a3fd8-82c1-49cd-bd9d-a09d70c56f75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48070726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dige
st.48070726
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1218613604
Short name T590
Test name
Test status
Simulation time 314401909 ps
CPU time 7.93 seconds
Started Apr 21 01:30:57 PM PDT 24
Finished Apr 21 01:31:05 PM PDT 24
Peak memory 217940 kb
Host smart-c2ebc3ff-7db8-4304-a3ad-52d6ced7d37f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218613604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
218613604
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2721453298
Short name T469
Test name
Test status
Simulation time 928622956 ps
CPU time 7.88 seconds
Started Apr 21 01:31:05 PM PDT 24
Finished Apr 21 01:31:13 PM PDT 24
Peak memory 217944 kb
Host smart-8a82fb65-819e-4ada-a13a-5d18828e8561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721453298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2721453298
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2748285663
Short name T685
Test name
Test status
Simulation time 26803735 ps
CPU time 1.78 seconds
Started Apr 21 01:30:51 PM PDT 24
Finished Apr 21 01:30:53 PM PDT 24
Peak memory 213448 kb
Host smart-e5ed949b-c598-499c-9623-841a952e1fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748285663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2748285663
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1825053017
Short name T36
Test name
Test status
Simulation time 819973113 ps
CPU time 23.96 seconds
Started Apr 21 01:30:50 PM PDT 24
Finished Apr 21 01:31:14 PM PDT 24
Peak memory 250796 kb
Host smart-c2270f2d-4913-4ee1-af51-ab867a475304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825053017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1825053017
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.449711521
Short name T558
Test name
Test status
Simulation time 54442880 ps
CPU time 9.3 seconds
Started Apr 21 01:30:52 PM PDT 24
Finished Apr 21 01:31:01 PM PDT 24
Peak memory 250856 kb
Host smart-8b0aff82-9926-423b-943e-2bccf8ec1516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449711521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.449711521
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1182167943
Short name T85
Test name
Test status
Simulation time 5890879324 ps
CPU time 184.07 seconds
Started Apr 21 01:30:56 PM PDT 24
Finished Apr 21 01:34:00 PM PDT 24
Peak memory 275552 kb
Host smart-6dde7ad3-ba42-4b99-9b7b-812e09eaec78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182167943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1182167943
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.523963481
Short name T713
Test name
Test status
Simulation time 19630929 ps
CPU time 1.07 seconds
Started Apr 21 01:30:48 PM PDT 24
Finished Apr 21 01:30:50 PM PDT 24
Peak memory 211412 kb
Host smart-336f927f-aabc-4082-90aa-f800b29d6ef1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523963481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.523963481
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2132939635
Short name T112
Test name
Test status
Simulation time 17858924 ps
CPU time 0.91 seconds
Started Apr 21 01:31:08 PM PDT 24
Finished Apr 21 01:31:09 PM PDT 24
Peak memory 209448 kb
Host smart-83f28f0f-ee83-4c54-ae0f-332d79d481cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132939635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2132939635
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.4038797879
Short name T446
Test name
Test status
Simulation time 60992191 ps
CPU time 0.88 seconds
Started Apr 21 01:31:03 PM PDT 24
Finished Apr 21 01:31:04 PM PDT 24
Peak memory 209416 kb
Host smart-72bf2ce7-3c86-48c7-8771-813443292194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038797879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4038797879
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.239150956
Short name T581
Test name
Test status
Simulation time 401827867 ps
CPU time 8.08 seconds
Started Apr 21 01:31:01 PM PDT 24
Finished Apr 21 01:31:09 PM PDT 24
Peak memory 217872 kb
Host smart-17f4079a-9649-4d55-b70f-69993bf9b54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239150956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.239150956
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2689762245
Short name T30
Test name
Test status
Simulation time 356070132 ps
CPU time 3.28 seconds
Started Apr 21 01:31:06 PM PDT 24
Finished Apr 21 01:31:10 PM PDT 24
Peak memory 209312 kb
Host smart-30fe51fa-9029-44fa-9a85-42446654c36b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689762245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2689762245
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1591855456
Short name T255
Test name
Test status
Simulation time 9936189499 ps
CPU time 36.73 seconds
Started Apr 21 01:31:05 PM PDT 24
Finished Apr 21 01:31:42 PM PDT 24
Peak memory 218868 kb
Host smart-6c7d3a91-1e5b-4b26-ba90-434b36a77bf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591855456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1591855456
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3241695106
Short name T599
Test name
Test status
Simulation time 116751859 ps
CPU time 2.21 seconds
Started Apr 21 01:31:08 PM PDT 24
Finished Apr 21 01:31:10 PM PDT 24
Peak memory 217708 kb
Host smart-0743e964-8308-47ab-8a85-4fe394b3e51d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241695106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
241695106
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.736474193
Short name T712
Test name
Test status
Simulation time 268694974 ps
CPU time 8.51 seconds
Started Apr 21 01:31:06 PM PDT 24
Finished Apr 21 01:31:15 PM PDT 24
Peak memory 217888 kb
Host smart-6be89815-7ed9-4496-b4e3-b716b798ac88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736474193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.736474193
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3965893526
Short name T305
Test name
Test status
Simulation time 1397974646 ps
CPU time 18.07 seconds
Started Apr 21 01:31:07 PM PDT 24
Finished Apr 21 01:31:26 PM PDT 24
Peak memory 213160 kb
Host smart-bd1ae8ba-7205-47a8-9d58-54f4891f2503
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965893526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3965893526
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3305870428
Short name T801
Test name
Test status
Simulation time 1715287136 ps
CPU time 3.38 seconds
Started Apr 21 01:31:03 PM PDT 24
Finished Apr 21 01:31:07 PM PDT 24
Peak memory 213088 kb
Host smart-dff7486c-56fc-4b79-ae03-91a472bbff08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305870428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3305870428
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2314680446
Short name T388
Test name
Test status
Simulation time 5514564962 ps
CPU time 65.8 seconds
Started Apr 21 01:31:06 PM PDT 24
Finished Apr 21 01:32:13 PM PDT 24
Peak memory 272040 kb
Host smart-af6bb44d-fa2b-44d0-be16-82dfc69d6c91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314680446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2314680446
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.849353420
Short name T502
Test name
Test status
Simulation time 1245749951 ps
CPU time 18.98 seconds
Started Apr 21 01:31:04 PM PDT 24
Finished Apr 21 01:31:24 PM PDT 24
Peak memory 217796 kb
Host smart-d9707919-dd16-4ff5-9e5e-76172e37256a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849353420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.849353420
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2650429885
Short name T118
Test name
Test status
Simulation time 386918017 ps
CPU time 2.25 seconds
Started Apr 21 01:31:03 PM PDT 24
Finished Apr 21 01:31:06 PM PDT 24
Peak memory 217812 kb
Host smart-c03ad4c1-56cd-407e-83e0-d0acc9a3fd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650429885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2650429885
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3454220242
Short name T603
Test name
Test status
Simulation time 248022838 ps
CPU time 5.58 seconds
Started Apr 21 01:31:05 PM PDT 24
Finished Apr 21 01:31:11 PM PDT 24
Peak memory 217728 kb
Host smart-f43af857-d026-4278-a24d-d7eb9b9d994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454220242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3454220242
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.671294314
Short name T722
Test name
Test status
Simulation time 494617765 ps
CPU time 12.18 seconds
Started Apr 21 01:31:07 PM PDT 24
Finished Apr 21 01:31:20 PM PDT 24
Peak memory 225928 kb
Host smart-0fdc35a5-1b41-41d6-ba51-fa6bb4999227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671294314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.671294314
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1184622896
Short name T368
Test name
Test status
Simulation time 2723631453 ps
CPU time 9.01 seconds
Started Apr 21 01:31:08 PM PDT 24
Finished Apr 21 01:31:17 PM PDT 24
Peak memory 217980 kb
Host smart-9cc71ebe-bc86-4771-a31a-53b5d409e757
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184622896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1184622896
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3989819998
Short name T555
Test name
Test status
Simulation time 425223838 ps
CPU time 13.8 seconds
Started Apr 21 01:31:08 PM PDT 24
Finished Apr 21 01:31:22 PM PDT 24
Peak memory 217856 kb
Host smart-31693857-1d03-41eb-a65c-e3c23bede676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989819998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
989819998
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.65737007
Short name T270
Test name
Test status
Simulation time 1770550380 ps
CPU time 9.41 seconds
Started Apr 21 01:31:04 PM PDT 24
Finished Apr 21 01:31:14 PM PDT 24
Peak memory 217916 kb
Host smart-b5589372-2097-40ce-82a6-e78417d60cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65737007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.65737007
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.4207445231
Short name T309
Test name
Test status
Simulation time 76792527 ps
CPU time 1.42 seconds
Started Apr 21 01:31:01 PM PDT 24
Finished Apr 21 01:31:03 PM PDT 24
Peak memory 213044 kb
Host smart-63b07c7e-5f19-456a-97a8-18499fdd16ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207445231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4207445231
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1637968662
Short name T612
Test name
Test status
Simulation time 1132494677 ps
CPU time 30.34 seconds
Started Apr 21 01:31:00 PM PDT 24
Finished Apr 21 01:31:31 PM PDT 24
Peak memory 250828 kb
Host smart-4de08245-3909-44c5-9fcc-a290f8220c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637968662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1637968662
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.407391041
Short name T230
Test name
Test status
Simulation time 131636030 ps
CPU time 6.65 seconds
Started Apr 21 01:31:02 PM PDT 24
Finished Apr 21 01:31:08 PM PDT 24
Peak memory 250296 kb
Host smart-706f71c8-0a87-4479-ae74-f89cdf9e83f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407391041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.407391041
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.4082116092
Short name T849
Test name
Test status
Simulation time 12662621360 ps
CPU time 209.87 seconds
Started Apr 21 01:31:08 PM PDT 24
Finished Apr 21 01:34:38 PM PDT 24
Peak memory 268228 kb
Host smart-6d7c3046-d209-4bc2-b30a-94b0e61fac45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082116092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.4082116092
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2165820419
Short name T332
Test name
Test status
Simulation time 29963540 ps
CPU time 0.98 seconds
Started Apr 21 01:31:03 PM PDT 24
Finished Apr 21 01:31:04 PM PDT 24
Peak memory 208520 kb
Host smart-b7ea150c-f5aa-4f20-9adb-2e4a0b116d9a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165820419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2165820419
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1974975420
Short name T227
Test name
Test status
Simulation time 93506631 ps
CPU time 0.94 seconds
Started Apr 21 01:31:19 PM PDT 24
Finished Apr 21 01:31:20 PM PDT 24
Peak memory 209576 kb
Host smart-1113fdcc-0956-47ae-9990-e0a0ce2ad360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974975420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1974975420
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4041810502
Short name T546
Test name
Test status
Simulation time 62196170 ps
CPU time 0.87 seconds
Started Apr 21 01:31:17 PM PDT 24
Finished Apr 21 01:31:18 PM PDT 24
Peak memory 209448 kb
Host smart-7fec3561-32bb-460d-8680-90b7b7d15c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041810502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4041810502
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3784641024
Short name T420
Test name
Test status
Simulation time 1785196758 ps
CPU time 12.55 seconds
Started Apr 21 01:31:21 PM PDT 24
Finished Apr 21 01:31:34 PM PDT 24
Peak memory 217808 kb
Host smart-a12c5fc9-177d-4e04-8a77-dfb07a87df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784641024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3784641024
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3662545150
Short name T8
Test name
Test status
Simulation time 367275448 ps
CPU time 5.59 seconds
Started Apr 21 01:31:15 PM PDT 24
Finished Apr 21 01:31:21 PM PDT 24
Peak memory 209424 kb
Host smart-c1ae0b64-428d-4a28-982a-b0cb7f0453fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662545150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3662545150
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2834149961
Short name T24
Test name
Test status
Simulation time 2108456719 ps
CPU time 57.92 seconds
Started Apr 21 01:31:16 PM PDT 24
Finished Apr 21 01:32:14 PM PDT 24
Peak memory 217756 kb
Host smart-f8b5b1e0-da15-4554-84d2-1a584c24d31b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834149961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2834149961
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2577053739
Short name T7
Test name
Test status
Simulation time 9433912929 ps
CPU time 32.18 seconds
Started Apr 21 01:31:17 PM PDT 24
Finished Apr 21 01:31:50 PM PDT 24
Peak memory 217828 kb
Host smart-ee0d8843-ba3e-4402-ad2d-11077b7b21c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577053739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
577053739
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.941484916
Short name T638
Test name
Test status
Simulation time 1317617915 ps
CPU time 1.93 seconds
Started Apr 21 01:31:16 PM PDT 24
Finished Apr 21 01:31:18 PM PDT 24
Peak memory 217828 kb
Host smart-1ffe93be-f983-47fd-bf02-d016e0014bed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941484916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.941484916
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2737144536
Short name T443
Test name
Test status
Simulation time 3491850305 ps
CPU time 19.48 seconds
Started Apr 21 01:31:17 PM PDT 24
Finished Apr 21 01:31:37 PM PDT 24
Peak memory 213832 kb
Host smart-0a11b74c-95e0-4525-99bf-430727956877
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737144536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2737144536
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1872458074
Short name T400
Test name
Test status
Simulation time 96147205 ps
CPU time 2.89 seconds
Started Apr 21 01:31:16 PM PDT 24
Finished Apr 21 01:31:20 PM PDT 24
Peak memory 212504 kb
Host smart-cc270c1f-f011-4c87-b5ec-2198ce782b52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872458074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1872458074
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1114465327
Short name T847
Test name
Test status
Simulation time 7446873242 ps
CPU time 46.5 seconds
Started Apr 21 01:31:14 PM PDT 24
Finished Apr 21 01:32:01 PM PDT 24
Peak memory 268636 kb
Host smart-96140acc-6d26-4bf5-bc5a-ee81e6b1c7be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114465327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1114465327
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3644877828
Short name T862
Test name
Test status
Simulation time 4010326862 ps
CPU time 33.28 seconds
Started Apr 21 01:31:16 PM PDT 24
Finished Apr 21 01:31:49 PM PDT 24
Peak memory 242684 kb
Host smart-d61701bd-bda8-4058-af7f-c5cf1e47d36f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644877828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3644877828
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.597041149
Short name T439
Test name
Test status
Simulation time 81043567 ps
CPU time 1.58 seconds
Started Apr 21 01:31:14 PM PDT 24
Finished Apr 21 01:31:16 PM PDT 24
Peak memory 217820 kb
Host smart-5ff19c23-f285-4b91-9405-7cc4afc75ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597041149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.597041149
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2283264270
Short name T186
Test name
Test status
Simulation time 311083601 ps
CPU time 19.84 seconds
Started Apr 21 01:31:13 PM PDT 24
Finished Apr 21 01:31:33 PM PDT 24
Peak memory 217652 kb
Host smart-8d7ca696-f087-43f6-85c0-404ea5e12170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283264270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2283264270
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.4289105520
Short name T702
Test name
Test status
Simulation time 400350659 ps
CPU time 11.7 seconds
Started Apr 21 01:31:17 PM PDT 24
Finished Apr 21 01:31:29 PM PDT 24
Peak memory 225968 kb
Host smart-a6e3cb1d-b94d-4e4b-b722-7d654ac96f03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289105520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.4289105520
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.570344463
Short name T741
Test name
Test status
Simulation time 672173080 ps
CPU time 13.14 seconds
Started Apr 21 01:31:17 PM PDT 24
Finished Apr 21 01:31:31 PM PDT 24
Peak memory 217876 kb
Host smart-cbfafa04-e14a-49b7-b4cf-3d9f05e31199
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570344463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.570344463
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3793669051
Short name T183
Test name
Test status
Simulation time 1208444698 ps
CPU time 12.18 seconds
Started Apr 21 01:31:16 PM PDT 24
Finished Apr 21 01:31:28 PM PDT 24
Peak memory 217820 kb
Host smart-08096662-4b65-4dac-bd73-3bd64c05e087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793669051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
793669051
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.712412805
Short name T804
Test name
Test status
Simulation time 342360809 ps
CPU time 7.59 seconds
Started Apr 21 01:31:14 PM PDT 24
Finished Apr 21 01:31:22 PM PDT 24
Peak memory 224992 kb
Host smart-b55a0c25-d2eb-44c0-a581-821461206384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712412805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.712412805
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1686625298
Short name T78
Test name
Test status
Simulation time 66707507 ps
CPU time 1.19 seconds
Started Apr 21 01:31:09 PM PDT 24
Finished Apr 21 01:31:10 PM PDT 24
Peak memory 213324 kb
Host smart-218eb701-c98d-4751-b6b1-05a18952881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686625298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1686625298
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.887263011
Short name T185
Test name
Test status
Simulation time 2590049889 ps
CPU time 20.28 seconds
Started Apr 21 01:31:11 PM PDT 24
Finished Apr 21 01:31:31 PM PDT 24
Peak memory 250968 kb
Host smart-5a2041f1-3b85-458b-935c-e768238c48b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887263011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.887263011
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4257719478
Short name T857
Test name
Test status
Simulation time 379138311 ps
CPU time 3.54 seconds
Started Apr 21 01:31:12 PM PDT 24
Finished Apr 21 01:31:16 PM PDT 24
Peak memory 217856 kb
Host smart-1f91143a-7edd-4504-be55-609f95fde7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257719478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4257719478
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.964871940
Short name T769
Test name
Test status
Simulation time 4464993509 ps
CPU time 133.23 seconds
Started Apr 21 01:31:17 PM PDT 24
Finished Apr 21 01:33:30 PM PDT 24
Peak memory 496696 kb
Host smart-b5578b78-ebab-4107-8bf5-3f8e72aaa30b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964871940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.964871940
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1068965304
Short name T41
Test name
Test status
Simulation time 53556564 ps
CPU time 0.96 seconds
Started Apr 21 01:31:07 PM PDT 24
Finished Apr 21 01:31:08 PM PDT 24
Peak memory 211468 kb
Host smart-c42d940e-707f-4797-9c85-049dd76a1e96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068965304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1068965304
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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