LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	4.820s	272.468us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.160s	75.606us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	66.951us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.650s	130.943us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.300s	36.657us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.040s	46.112us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	66.951us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	36.657us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.500s	1.454ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.700s	652.840us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	12.953us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.410s	196.828us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.340s	2.333ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_prog_failure	4.410s	196.828us	50	50	100.00
		lc_ctrl_errors	24.340s	2.333ms	50	50	100.00
		lc_ctrl_security_escalation	16.200s	1.022ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.151m	7.037ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.940s	15.337ms	20	20	100.00
		lc_ctrl_jtag_errors	1.444m	3.225ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.960s	806.276us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.280s	4.010ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.940s	15.337ms	20	20	100.00
		lc_ctrl_jtag_errors	1.444m	3.225ms	20	20	100.00
		lc_ctrl_jtag_access	20.150s	4.743ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.570s	3.257ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.230s	399.200us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.720s	144.233us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.020s	1.075ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.720s	984.886us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.250s	50.777us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.960s	1.585ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.150s	351.362us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	34.620s	1.518ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.210s	16.804us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	14.336m	195.118ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.380s	119.091us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.120s	128.992us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.120s	128.992us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.160s	75.606us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	66.951us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	36.657us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.830s	37.420us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.160s	75.606us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	66.951us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	36.657us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.830s	37.420us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.740s	480.857us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.740s	480.857us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.700s	652.840us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.170s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	39.200s	1.060ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.200s	1.022ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.500s	1.454ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.280s	4.010ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.090s	2.388ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.090s	2.388ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.760s	1.225ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.670s	2.095ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.670s	2.095ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.812h	114.538ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.89	95.68	93.31	100.00	98.55	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.112776192792082448557716857558107031401097459160936548237952041104963768184978
      Line 13693, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12612451832 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12612451832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.106393178500840425156384519443041351010800680198744950447243152867958285040231
      Line 1543, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2990253947 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2990253947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 6 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.104120314467326707351423845985645084986673925957882942248955587006299276162052
      Line 1534, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3276439130 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3276439130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.lc_ctrl_stress_all_with_rand_reset.44604466178298962363920007553455242115502399825272226096872005541934388068345
      Line 34688, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19347184701 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 19347184701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

  • Test lc_ctrl_stress_all has 1 failures.

    • 20.lc_ctrl_stress_all.99414078497774235916498904135761978818557125568961937761809617006901527640931
      Line 10456, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 30584166240 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 30584166240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 0.lc_ctrl_stress_all.34032190224350862995829791012530841708115364674993573649263861836735345816649
      Line 6855, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 123145387685 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 123145387685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.62286799943553804671391133426312114028784399694493821365964118478393855017822
      Line 59479, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 189868159259 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 189868159259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 34.lc_ctrl_volatile_unlock_smoke.92629985238981284043494018670580528415028269391552101935286273203000049150703
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 145363915 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0xb963bc04) == 0x1
        UVM_INFO @ 145363915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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