LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.330s	375.576us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.410s	13.600us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.490s	13.672us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.400s	49.496us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.890s	150.808us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.290s	33.302us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.490s	13.672us	20	20	100.00
		lc_ctrl_csr_aliasing	1.890s	150.808us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.400s	160.416us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.680s	329.624us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.410s	11.213us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.780s	2.953ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.090s	2.815ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_prog_failure	5.780s	2.953ms	50	50	100.00
		lc_ctrl_errors	27.090s	2.815ms	50	50	100.00
		lc_ctrl_security_escalation	18.650s	921.474us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.351m	24.397ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.570s	2.727ms	20	20	100.00
		lc_ctrl_jtag_errors	2.363m	12.901ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.380s	1.781ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.810s	4.494ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.570s	2.727ms	20	20	100.00
		lc_ctrl_jtag_errors	2.363m	12.901ms	19	20	95.00
		lc_ctrl_jtag_access	35.670s	1.585ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	50.120s	8.200ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.090s	199.901us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.370s	58.007us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	41.640s	2.061ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.860s	872.797us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.150s	142.088us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.820s	173.299us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.720s	251.494us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.450s	612.545us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	2.070s	45.763us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.031m	18.565ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.030s	35.788us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.200s	130.605us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.200s	130.605us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.410s	13.600us	5	5	100.00
		lc_ctrl_csr_rw	1.490s	13.672us	20	20	100.00
		lc_ctrl_csr_aliasing	1.890s	150.808us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.240s	227.081us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.410s	13.600us	5	5	100.00
		lc_ctrl_csr_rw	1.490s	13.672us	20	20	100.00
		lc_ctrl_csr_aliasing	1.890s	150.808us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.240s	227.081us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.700s	524.500us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.700s	524.500us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.680s	329.624us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.990s	337.703us	50	50	100.00
		lc_ctrl_sec_cm	36.620s	4.292ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.650s	921.474us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.400s	160.416us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.810s	4.494ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	31.920s	2.979ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	31.920s	2.979ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	30.210s	5.158ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	29.030s	7.530ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	29.030s	7.530ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.395m	24.179ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.97	95.41	93.40	97.67	98.53	99.00	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 31 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.4415093435800157100139045972245732840067048350461235420754742506273709361502
      Line 10180, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6646583045 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6646583045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.29415301249602092659258419541135241456779587443775744749470883883402649332571
      Line 138, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 113334224 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 113334224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 29 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 1.lc_ctrl_jtag_errors.9964209894762685306185532747566531121404907583657291686243064438678284203816
      Line 1150, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 410622566 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 410622566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 46.lc_ctrl_stress_all_with_rand_reset.66122769031881581688162692197859856035361118709836747298482668549723578395698
      Line 10396, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14654048052 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 14654048052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.10.13_03.39.16
• 2024.10.10_10.15.31
• 2024.10.04_00.42.24
• 2024.09.25_11.01.24
• 2024.09.19_09.05.09
• 2024.09.12_10.16.47
• 2024.09.10_08.11.38