LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.840s	228.686us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.800s	21.424us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.480s	29.062us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.190s	512.790us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.520s	59.644us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.160s	23.645us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.480s	29.062us	20	20	100.00
		lc_ctrl_csr_aliasing	2.520s	59.644us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	22.850s	251.253us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	30.680s	374.521us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.390s	21.640us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.070s	200.952us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.490s	914.222us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_prog_failure	7.070s	200.952us	50	50	100.00
		lc_ctrl_errors	25.490s	914.222us	50	50	100.00
		lc_ctrl_security_escalation	18.940s	394.349us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.404m	8.254ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.520s	2.146ms	20	20	100.00
		lc_ctrl_jtag_errors	2.047m	4.427ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.710s	350.309us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	50.200s	1.391ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.520s	2.146ms	20	20	100.00
		lc_ctrl_jtag_errors	2.047m	4.427ms	20	20	100.00
		lc_ctrl_jtag_access	22.850s	735.856us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.540s	3.082ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.480s	145.934us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.580s	434.814us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	56.860s	22.821ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.700s	1.006ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.330s	277.321us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.570s	287.681us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.760s	95.172us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	48.540s	3.446ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.910s	120.618us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.263m	21.393ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.070s	33.721us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.160s	219.130us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.160s	219.130us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.800s	21.424us	5	5	100.00
		lc_ctrl_csr_rw	1.480s	29.062us	20	20	100.00
		lc_ctrl_csr_aliasing	2.520s	59.644us	5	5	100.00
		lc_ctrl_same_csr_outstanding	3.110s	49.215us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.800s	21.424us	5	5	100.00
		lc_ctrl_csr_rw	1.480s	29.062us	20	20	100.00
		lc_ctrl_csr_aliasing	2.520s	59.644us	5	5	100.00
		lc_ctrl_same_csr_outstanding	3.110s	49.215us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
		lc_ctrl_tl_intg_err	6.630s	856.188us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.630s	856.188us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	30.680s	374.521us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.098m	3.347ms	50	50	100.00
		lc_ctrl_sec_cm	1.232m	887.087us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.940s	394.349us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	22.850s	251.253us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	50.200s	1.391ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	32.860s	1.236ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	32.860s	1.236ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	31.970s	1.863ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.080s	2.610ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.080s	2.610ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.166h	211.777ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1012	1030	98.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.99	95.95	93.40	100.00	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 16 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.39105678085846372872654129744140072343016084270820047749551678196564721960318
      Line 154, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5434495128 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5434495128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.lc_ctrl_stress_all_with_rand_reset.47535815606688603864982132336558816864019404028390978172783833914455746568416
      Line 7556, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 52237156721 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 52237156721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 9.lc_ctrl_stress_all.68718967450790317167384893946904993759513306855018013520924130170518381322970
      Line 7249, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 51997121666 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 51997121666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.103177253287245326421630666193169170971754119844404911618544966308690866254458
      Line 29933, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 71554571338 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 71554571338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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