Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1880456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2096985

1

T1

45

T2

5

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3641013	1			T1	156		T3	5		T4	33337
values[0x0]	167998	1			T2	7		T3	10		T10	16
values[0x1]	168430	1			T2	7		T3	5		T10	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1495299	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2482142

1

T1

69

T2

6

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9957	1			T1	1		T13	9		T14	2
valid_sources[0x01]	9078	1			T13	7		T14	1		T15	2
valid_sources[0x02]	10020	1			T1	4		T13	13		T14	1
valid_sources[0x03]	9647	1			T13	9		T14	1		T15	10
valid_sources[0x04]	9372	1			T1	3		T10	1		T13	8
valid_sources[0x05]	8576	1			T1	2		T13	10		T15	5
valid_sources[0x06]	12367	1			T1	1		T10	1		T13	9
valid_sources[0x07]	13370	1			T13	11		T14	1		T15	3
valid_sources[0x08]	9292	1			T13	11		T14	5		T15	1
valid_sources[0x09]	11068	1			T13	4		T15	8		T16	1
valid_sources[0x0a]	8834	1			T1	1		T13	10		T15	4
valid_sources[0x0b]	9480	1			T13	10		T14	2		T15	4
valid_sources[0x0c]	41607	1			T13	17		T14	3		T15	6
valid_sources[0x0d]	9390	1			T1	1		T13	10		T15	2
valid_sources[0x0e]	41810	1			T13	12		T14	3		T15	5
valid_sources[0x0f]	10058	1			T13	9		T14	1		T15	11
valid_sources[0x10]	14392	1			T13	10		T14	1		T15	5
valid_sources[0x11]	9504	1			T1	1		T13	5		T15	2
valid_sources[0x12]	10029	1			T1	1		T13	13		T14	4
valid_sources[0x13]	10314	1			T1	1		T13	7		T15	6
valid_sources[0x14]	10703	1			T13	15		T14	1		T15	4
valid_sources[0x15]	9347	1			T10	1		T13	10		T14	1
valid_sources[0x16]	9134	1			T13	14		T14	4		T15	4
valid_sources[0x17]	9132	1			T13	10		T14	1		T15	1
valid_sources[0x18]	8933	1			T10	1		T13	10		T14	3
valid_sources[0x19]	12178	1			T13	13		T14	1		T15	3
valid_sources[0x1a]	9103	1			T1	3		T10	1		T13	8
valid_sources[0x1b]	13907	1			T13	8		T15	3		T16	5
valid_sources[0x1c]	8760	1			T1	1		T13	10		T14	2
valid_sources[0x1d]	9347	1			T13	16		T14	1		T15	3
valid_sources[0x1e]	9671	1			T13	14		T14	1		T15	10
valid_sources[0x1f]	10518	1			T13	8		T14	1		T15	4
valid_sources[0x20]	9670	1			T1	5		T13	8		T14	2
valid_sources[0x21]	10488	1			T1	1		T13	10		T15	7
valid_sources[0x22]	9762	1			T13	12		T14	2		T15	3
valid_sources[0x23]	9670	1			T1	1		T4	405		T13	18
valid_sources[0x24]	11441	1			T1	2		T13	10		T14	3
valid_sources[0x25]	9125	1			T1	1		T13	8		T14	1
valid_sources[0x26]	9521	1			T1	1		T13	7		T15	4
valid_sources[0x27]	70331	1			T13	5		T15	9		T16	4
valid_sources[0x28]	9367	1			T10	1		T13	20		T14	1
valid_sources[0x29]	10691	1			T13	7		T14	1		T15	4
valid_sources[0x2a]	9348	1			T13	6		T14	1		T15	8
valid_sources[0x2b]	9009	1			T10	1		T13	10		T14	1
valid_sources[0x2c]	8974	1			T13	9		T14	5		T15	6
valid_sources[0x2d]	10121	1			T1	1		T13	6		T14	2
valid_sources[0x2e]	9179	1			T1	1		T13	9		T15	5
valid_sources[0x2f]	9380	1			T13	11		T14	2		T15	11
valid_sources[0x30]	11698	1			T1	1		T13	20		T14	1
valid_sources[0x31]	9296	1			T1	2		T13	12		T14	1
valid_sources[0x32]	9357	1			T1	1		T13	7		T14	1
valid_sources[0x33]	9404	1			T1	2		T13	11		T15	5
valid_sources[0x34]	9172	1			T3	1		T13	22		T14	3
valid_sources[0x35]	19676	1			T13	9		T14	3		T15	3
valid_sources[0x36]	10615	1			T13	7		T14	3		T15	7
valid_sources[0x37]	11199	1			T1	1		T13	6		T15	2
valid_sources[0x38]	9038	1			T1	1		T13	12		T14	2
valid_sources[0x39]	9735	1			T1	1		T13	20		T14	2
valid_sources[0x3a]	9079	1			T1	1		T13	15		T14	1
valid_sources[0x3b]	9795	1			T13	8		T15	5		T18	1
valid_sources[0x3c]	11110	1			T13	11		T14	1		T15	9
valid_sources[0x3d]	100709	1			T1	1		T13	12		T15	3
valid_sources[0x3e]	16641	1			T13	11		T14	1		T15	4
valid_sources[0x3f]	9492	1			T2	1		T13	10		T14	1
valid_sources[0x40]	9537	1			T1	1		T13	14		T14	3
valid_sources[0x41]	10311	1			T13	7		T14	1		T15	7
valid_sources[0x42]	8967	1			T3	2		T13	7		T14	1
valid_sources[0x43]	9043	1			T1	1		T13	10		T14	3
valid_sources[0x44]	92920	1			T13	8		T14	1		T15	4
valid_sources[0x45]	10868	1			T10	1		T13	15		T14	1
valid_sources[0x46]	11604	1			T10	1		T13	10		T14	1
valid_sources[0x47]	187374	1			T13	12		T15	5		T16	8
valid_sources[0x48]	53159	1			T13	2		T14	3		T15	7
valid_sources[0x49]	9357	1			T13	11		T14	2		T15	8
valid_sources[0x4a]	8930	1			T13	7		T14	1		T15	1
valid_sources[0x4b]	8899	1			T13	20		T15	1		T16	8
valid_sources[0x4c]	9373	1			T1	1		T13	9		T14	1
valid_sources[0x4d]	10675	1			T10	1		T13	10		T14	2
valid_sources[0x4e]	11377	1			T1	1		T13	11		T14	2
valid_sources[0x4f]	9329	1			T13	12		T15	2		T16	4
valid_sources[0x50]	9490	1			T1	2		T13	12		T15	7
valid_sources[0x51]	9362	1			T13	17		T15	5		T16	1
valid_sources[0x52]	9663	1			T13	17		T14	2		T15	8
valid_sources[0x53]	9838	1			T1	1		T13	9		T14	1
valid_sources[0x54]	9579	1			T13	11		T14	1		T15	9
valid_sources[0x55]	9215	1			T1	1		T11	6		T13	12
valid_sources[0x56]	9708	1			T13	8		T14	4		T15	6
valid_sources[0x57]	9488	1			T13	14		T15	4		T16	7
valid_sources[0x58]	13070	1			T2	1		T13	13		T15	6
valid_sources[0x59]	12221	1			T13	5		T14	2		T15	3
valid_sources[0x5a]	11324	1			T1	1		T13	12		T14	1
valid_sources[0x5b]	9380	1			T13	13		T14	1		T15	4
valid_sources[0x5c]	12661	1			T1	1		T13	7		T14	2
valid_sources[0x5d]	10231	1			T1	1		T13	6		T15	6
valid_sources[0x5e]	19218	1			T10	1		T13	5		T14	1
valid_sources[0x5f]	8673	1			T1	1		T13	13		T14	1
valid_sources[0x60]	11169	1			T13	10		T15	1		T16	2
valid_sources[0x61]	34358	1			T13	14		T15	2		T19	1
valid_sources[0x62]	9079	1			T13	9		T15	2		T16	6
valid_sources[0x63]	10021	1			T2	1		T13	9		T14	2
valid_sources[0x64]	9640	1			T13	18		T15	3		T16	4
valid_sources[0x65]	12771	1			T13	14		T14	1		T16	7
valid_sources[0x66]	9442	1			T13	8		T14	2		T15	4
valid_sources[0x67]	11342	1			T1	3		T13	9		T14	1
valid_sources[0x68]	9665	1			T3	1		T13	9		T14	1
valid_sources[0x69]	9422	1			T13	7		T14	1		T15	5
valid_sources[0x6a]	9234	1			T13	5		T15	5		T16	5
valid_sources[0x6b]	9264	1			T13	6		T14	2		T15	11
valid_sources[0x6c]	10281	1			T1	3		T13	11		T14	1
valid_sources[0x6d]	9292	1			T1	1		T2	1		T13	15
valid_sources[0x6e]	9419	1			T1	1		T3	1		T13	6
valid_sources[0x6f]	9952	1			T13	9		T16	1		T19	12
valid_sources[0x70]	9633	1			T1	3		T13	7		T14	2
valid_sources[0x71]	24946	1			T1	1		T13	8		T14	2
valid_sources[0x72]	9142	1			T1	1		T13	9		T15	3
valid_sources[0x73]	15515	1			T13	14		T14	1		T15	5
valid_sources[0x74]	9509	1			T1	1		T11	10		T13	14
valid_sources[0x75]	10250	1			T13	8		T14	6		T15	10
valid_sources[0x76]	10727	1			T13	14		T14	3		T15	2
valid_sources[0x77]	12159	1			T13	16		T15	9		T18	7
valid_sources[0x78]	10025	1			T13	8		T14	1		T15	2
valid_sources[0x79]	16060	1			T13	14		T14	1		T15	7
valid_sources[0x7a]	17104	1			T1	2		T2	1		T10	2
valid_sources[0x7b]	76042	1			T1	1		T2	1		T10	1
valid_sources[0x7c]	9897	1			T1	1		T13	11		T15	13
valid_sources[0x7d]	9784	1			T13	5		T14	1		T15	6
valid_sources[0x7e]	12156	1			T13	13		T14	3		T15	6
valid_sources[0x7f]	9371	1			T13	11		T14	1		T15	7
valid_sources[0x80]	8369	1			T1	1		T13	12		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1807229

1

T1

45

T3

1

T4

16654

values[0x0]

all_enables

biggest_size

145593

1

T2

4

T3

9

T10

6

values[0x1]

all_enables

biggest_size

144163

1

T2

1

T3

3

T10

3