Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106767407	15648	0	0
claim_transition_if_regwen_rd_A	106767407	1422	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106767407	15648	0	0
T4	120142	1	0	0
T5	214368	0	0	0
T12	974	0	0	0
T13	46687	0	0	0
T14	6913	0	0	0
T15	37774	0	0	0
T16	43747	0	0	0
T17	24170	0	0	0
T18	26328	0	0	0
T19	27308	0	0	0
T20	0	6	0	0
T44	0	18	0	0
T48	0	16	0	0
T106	0	8	0	0
T145	0	14	0	0
T146	0	9	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	16	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106767407	1422	0	0
T103	6488	32	0	0
T104	2444	14	0	0
T105	12620	20	0	0
T107	1621	5	0	0
T112	4894	65	0	0
T113	3558	202	0	0
T114	3894	28	0	0
T127	11295	66	0	0
T150	4529	27	0	0
T151	4392	57	0	0