Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1626510	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1853519

1

T2

225

T3

737

T7

1848

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3130468	1			T2	205		T3	659		T7	2521
values[0x0]	174194	1			T2	99		T3	237		T7	328
values[0x1]	175367	1			T2	78		T3	251		T7	344

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1291276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2188753

1

T2

263

T3

843

T7

2125

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10971	1			T7	9		T8	10		T11	8
valid_sources[0x01]	10206	1			T7	3		T8	12		T11	4
valid_sources[0x02]	51954	1			T7	2		T8	11		T10	1
valid_sources[0x03]	10119	1			T7	16		T8	13		T11	6
valid_sources[0x04]	9727	1			T8	16		T11	7		T12	1
valid_sources[0x05]	29231	1			T7	44		T8	11		T11	7
valid_sources[0x06]	9496	1			T7	29		T8	12		T11	4
valid_sources[0x07]	9628	1			T2	2		T7	2		T8	5
valid_sources[0x08]	9749	1			T7	20		T10	2		T11	9
valid_sources[0x09]	9880	1			T7	2		T8	6		T11	8
valid_sources[0x0a]	9947	1			T7	4		T8	29		T11	8
valid_sources[0x0b]	9618	1			T7	11		T11	4		T12	1
valid_sources[0x0c]	9598	1			T7	21		T8	13		T11	11
valid_sources[0x0d]	10109	1			T7	18		T8	16		T11	5
valid_sources[0x0e]	10181	1			T7	1		T8	22		T11	5
valid_sources[0x0f]	11360	1			T7	3		T8	8		T11	8
valid_sources[0x10]	9590	1			T7	16		T8	12		T11	1
valid_sources[0x11]	10428	1			T7	3		T8	10		T11	9
valid_sources[0x12]	17321	1			T7	19		T8	22		T11	8
valid_sources[0x13]	9717	1			T7	9		T8	7		T11	4
valid_sources[0x14]	10637	1			T7	1		T8	13		T11	6
valid_sources[0x15]	12498	1			T7	13		T8	16		T11	7
valid_sources[0x16]	9598	1			T8	1		T11	3		T13	91
valid_sources[0x17]	11816	1			T7	3		T8	6		T11	7
valid_sources[0x18]	10171	1			T7	34		T8	24		T11	5
valid_sources[0x19]	9976	1			T7	12		T8	22		T11	11
valid_sources[0x1a]	10470	1			T7	24		T8	9		T11	7
valid_sources[0x1b]	9479	1			T7	10		T8	22		T11	7
valid_sources[0x1c]	9828	1			T7	13		T8	23		T11	4
valid_sources[0x1d]	9928	1			T7	1		T8	8		T11	6
valid_sources[0x1e]	9874	1			T7	8		T11	7		T12	1
valid_sources[0x1f]	9858	1			T2	30		T7	29		T8	3
valid_sources[0x20]	10984	1			T7	5		T11	9		T12	3
valid_sources[0x21]	11295	1			T7	25		T8	18		T11	10
valid_sources[0x22]	10096	1			T7	10		T8	11		T11	5
valid_sources[0x23]	10050	1			T7	12		T8	19		T11	5
valid_sources[0x24]	9488	1			T7	43		T8	6		T11	9
valid_sources[0x25]	9567	1			T7	8		T8	3		T11	14
valid_sources[0x26]	9557	1			T7	8		T11	5		T13	93
valid_sources[0x27]	11120	1			T7	25		T8	10		T11	7
valid_sources[0x28]	9948	1			T7	1		T8	5		T11	7
valid_sources[0x29]	31753	1			T7	51		T8	8		T11	4
valid_sources[0x2a]	9642	1			T8	39		T11	4		T12	1
valid_sources[0x2b]	10577	1			T7	34		T11	11		T12	4
valid_sources[0x2c]	9896	1			T7	7		T8	18		T11	9
valid_sources[0x2d]	9820	1			T7	16		T8	5		T11	5
valid_sources[0x2e]	10083	1			T7	9		T8	30		T10	1
valid_sources[0x2f]	10156	1			T7	28		T8	9		T11	8
valid_sources[0x30]	11761	1			T7	42		T8	4		T11	9
valid_sources[0x31]	9881	1			T7	9		T8	10		T11	3
valid_sources[0x32]	9588	1			T7	1		T8	3		T11	8
valid_sources[0x33]	10214	1			T2	10		T7	38		T8	31
valid_sources[0x34]	10205	1			T7	11		T8	10		T11	4
valid_sources[0x35]	10657	1			T7	14		T10	1		T11	11
valid_sources[0x36]	9778	1			T2	4		T7	14		T8	13
valid_sources[0x37]	9499	1			T7	7		T8	2		T11	4
valid_sources[0x38]	9554	1			T7	5		T8	7		T10	5
valid_sources[0x39]	9779	1			T7	16		T11	4		T13	188
valid_sources[0x3a]	12591	1			T7	18		T8	21		T11	11
valid_sources[0x3b]	9854	1			T7	25		T10	1		T11	5
valid_sources[0x3c]	9500	1			T2	2		T8	7		T10	1
valid_sources[0x3d]	9292	1			T8	19		T11	6		T13	119
valid_sources[0x3e]	9666	1			T7	2		T8	11		T11	5
valid_sources[0x3f]	9716	1			T7	11		T8	6		T11	8
valid_sources[0x40]	23186	1			T7	3		T8	5		T11	9
valid_sources[0x41]	16983	1			T7	17		T8	20		T11	11
valid_sources[0x42]	9609	1			T7	23		T8	13		T10	1
valid_sources[0x43]	9450	1			T7	6		T11	6		T12	1
valid_sources[0x44]	11020	1			T7	19		T8	4		T11	5
valid_sources[0x45]	11670	1			T2	31		T7	3		T8	13
valid_sources[0x46]	11168	1			T7	1		T8	2		T11	5
valid_sources[0x47]	9782	1			T7	52		T8	14		T11	5
valid_sources[0x48]	12584	1			T2	1		T7	10		T8	11
valid_sources[0x49]	9907	1			T7	20		T8	11		T11	12
valid_sources[0x4a]	76616	1			T7	16		T8	21		T11	2
valid_sources[0x4b]	11228	1			T7	6		T8	29		T11	8
valid_sources[0x4c]	9674	1			T7	8		T8	7		T11	6
valid_sources[0x4d]	9882	1			T7	14		T8	11		T11	6
valid_sources[0x4e]	9382	1			T2	40		T8	13		T11	5
valid_sources[0x4f]	9991	1			T7	16		T8	26		T11	10
valid_sources[0x50]	10023	1			T7	22		T8	37		T11	4
valid_sources[0x51]	9541	1			T7	13		T8	9		T10	2
valid_sources[0x52]	9663	1			T7	20		T8	16		T11	3
valid_sources[0x53]	10058	1			T7	32		T8	12		T11	11
valid_sources[0x54]	16045	1			T2	5		T11	7		T13	127
valid_sources[0x55]	10063	1			T7	5		T8	4		T11	6
valid_sources[0x56]	10843	1			T7	11		T8	1		T11	8
valid_sources[0x57]	123286	1			T7	13		T8	9		T11	5
valid_sources[0x58]	11474	1			T7	3		T11	11		T12	1
valid_sources[0x59]	9538	1			T2	25		T7	13		T8	10
valid_sources[0x5a]	10238	1			T2	7		T7	6		T8	4
valid_sources[0x5b]	9916	1			T7	14		T8	7		T10	1
valid_sources[0x5c]	10733	1			T7	12		T8	21		T11	13
valid_sources[0x5d]	13345	1			T2	4		T7	5		T11	7
valid_sources[0x5e]	10978	1			T7	3		T8	5		T10	1
valid_sources[0x5f]	10871	1			T8	10		T10	2		T11	5
valid_sources[0x60]	9763	1			T7	32		T8	16		T11	11
valid_sources[0x61]	9826	1			T7	16		T8	42		T11	5
valid_sources[0x62]	10105	1			T8	3		T11	8		T12	2
valid_sources[0x63]	10208	1			T8	4		T10	1		T11	10
valid_sources[0x64]	9442	1			T7	22		T8	5		T11	4
valid_sources[0x65]	9568	1			T7	8		T8	12		T11	9
valid_sources[0x66]	11768	1			T7	6		T8	8		T11	9
valid_sources[0x67]	9906	1			T7	11		T8	11		T10	1
valid_sources[0x68]	11487	1			T7	11		T8	9		T11	5
valid_sources[0x69]	14599	1			T7	6		T8	2		T11	4
valid_sources[0x6a]	10302	1			T7	6		T8	3		T10	2
valid_sources[0x6b]	9796	1			T7	14		T8	10		T11	6
valid_sources[0x6c]	10522	1			T2	5		T7	12		T8	7
valid_sources[0x6d]	10385	1			T7	27		T8	10		T11	10
valid_sources[0x6e]	9638	1			T7	1		T8	20		T11	7
valid_sources[0x6f]	9421	1			T7	4		T10	1		T11	6
valid_sources[0x70]	11110	1			T7	11		T8	3		T10	1
valid_sources[0x71]	10546	1			T7	8		T8	7		T11	8
valid_sources[0x72]	10029	1			T7	4		T8	28		T11	3
valid_sources[0x73]	9430	1			T7	4		T8	3		T11	5
valid_sources[0x74]	10994	1			T7	20		T8	9		T11	4
valid_sources[0x75]	9827	1			T8	28		T11	7		T12	2
valid_sources[0x76]	10777	1			T2	9		T7	18		T8	10
valid_sources[0x77]	15090	1			T7	2		T8	24		T11	4
valid_sources[0x78]	9940	1			T7	1		T8	17		T11	8
valid_sources[0x79]	9829	1			T7	43		T11	6		T12	1
valid_sources[0x7a]	10036	1			T7	3		T8	6		T11	10
valid_sources[0x7b]	10194	1			T7	5		T11	6		T13	145
valid_sources[0x7c]	18277	1			T7	7		T8	3		T11	5
valid_sources[0x7d]	16248	1			T7	28		T8	6		T11	8
valid_sources[0x7e]	54308	1			T8	22		T11	7		T13	219
valid_sources[0x7f]	99412	1			T7	4		T8	8		T11	9
valid_sources[0x80]	9825	1			T2	27		T7	16		T8	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1551663

1

T2

101

T3

315

T7

1265

values[0x0]

all_enables

biggest_size

151303

1

T2

72

T3

211

T7

280

values[0x1]

all_enables

biggest_size

150553

1

T2

52

T3

211

T7

303