Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	112123087	12578	0	0
claim_transition_if_regwen_rd_A	112123087	843	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112123087	12578	0	0
T5	53160	0	0	0
T13	137399	1	0	0
T14	249070	0	0	0
T15	41835	0	0	0
T24	1235	0	0	0
T25	1236	0	0	0
T28	3126	0	0	0
T31	21917	0	0	0
T35	34351	0	0	0
T46	4150	0	0	0
T90	0	2	0	0
T91	0	9	0	0
T92	0	2	0	0
T96	0	1	0	0
T115	0	8	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	15	0	0
T157	0	4	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112123087	843	0	0
T45	0	12	0	0
T90	143608	2	0	0
T94	0	4	0	0
T119	0	10	0	0
T120	0	52	0	0
T158	0	7	0	0
T159	0	4	0	0
T160	0	28	0	0
T161	0	1	0	0
T162	0	15	0	0
T163	30107	0	0	0
T164	5568	0	0	0
T165	3854	0	0	0
T166	1358	0	0	0
T167	933	0	0	0
T168	7844	0	0	0
T169	9761	0	0	0
T170	149526	0	0	0
T171	6780	0	0	0