Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1829266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2051191

1

T1

20

T2

1558

T3

1098

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3529158	1			T1	80		T2	2077		T3	1448
values[0x0]	175372	1			T2	330		T3	197		T10	8
values[0x1]	175927	1			T2	286		T3	235		T10	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1454746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2425711

1

T1

33

T2

1801

T3

1262

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11527	1			T11	5		T12	1		T4	1
valid_sources[0x01]	13028	1			T11	2		T5	173		T22	2
valid_sources[0x02]	10811	1			T4	4		T5	159		T21	7
valid_sources[0x03]	21417	1			T4	7		T5	141		T21	1
valid_sources[0x04]	11559	1			T1	1		T4	1		T5	154
valid_sources[0x05]	10792	1			T11	1		T4	2		T5	155
valid_sources[0x06]	10674	1			T11	2		T12	1		T4	9
valid_sources[0x07]	10851	1			T12	2		T4	2		T5	164
valid_sources[0x08]	10924	1			T1	5		T12	4		T4	1
valid_sources[0x09]	11722	1			T11	2		T12	1		T4	6
valid_sources[0x0a]	12948	1			T11	16		T4	2		T5	150
valid_sources[0x0b]	49310	1			T4	5		T5	210		T18	5
valid_sources[0x0c]	20651	1			T1	6		T5	179		T21	1
valid_sources[0x0d]	11206	1			T11	10		T4	5		T5	150
valid_sources[0x0e]	13243	1			T11	10		T4	2		T5	162
valid_sources[0x0f]	10938	1			T4	2		T5	191		T18	1
valid_sources[0x10]	11249	1			T11	2		T4	3		T5	177
valid_sources[0x11]	10980	1			T4	1		T5	172		T21	1
valid_sources[0x12]	31437	1			T11	4		T4	4		T5	161
valid_sources[0x13]	12255	1			T4	7		T5	161		T21	1
valid_sources[0x14]	10903	1			T11	2		T5	182		T18	3
valid_sources[0x15]	23633	1			T11	3		T12	1		T4	8
valid_sources[0x16]	10903	1			T11	4		T12	1		T4	7
valid_sources[0x17]	10940	1			T4	1		T5	149		T18	4
valid_sources[0x18]	12786	1			T11	5		T12	2		T5	151
valid_sources[0x19]	11174	1			T4	4		T5	139		T21	3
valid_sources[0x1a]	10690	1			T12	1		T4	1		T5	122
valid_sources[0x1b]	12526	1			T11	5		T4	3		T5	178
valid_sources[0x1c]	11332	1			T1	3		T4	4		T5	153
valid_sources[0x1d]	10753	1			T11	4		T5	183		T18	8
valid_sources[0x1e]	13103	1			T11	7		T4	1		T5	157
valid_sources[0x1f]	12353	1			T10	1		T4	8		T5	146
valid_sources[0x20]	13508	1			T4	1		T5	150		T22	1
valid_sources[0x21]	10990	1			T4	1		T5	156		T21	2
valid_sources[0x22]	10918	1			T11	1		T12	1		T4	1
valid_sources[0x23]	10374	1			T11	9		T4	2		T5	156
valid_sources[0x24]	11881	1			T4	3		T5	177		T18	3
valid_sources[0x25]	12782	1			T11	2		T4	3		T5	149
valid_sources[0x26]	10242	1			T4	1		T5	132		T18	6
valid_sources[0x27]	11015	1			T4	5		T5	187		T30	6
valid_sources[0x28]	12128	1			T4	3		T5	141		T21	2
valid_sources[0x29]	10675	1			T5	137		T30	1		T20	5
valid_sources[0x2a]	10417	1			T11	1		T4	1		T5	182
valid_sources[0x2b]	11106	1			T11	1		T12	1		T4	2
valid_sources[0x2c]	12579	1			T11	7		T4	4		T5	151
valid_sources[0x2d]	11019	1			T11	2		T12	1		T4	2
valid_sources[0x2e]	11402	1			T11	16		T4	5		T5	156
valid_sources[0x2f]	10815	1			T1	1		T11	1		T4	2
valid_sources[0x30]	12729	1			T11	2		T4	4		T5	130
valid_sources[0x31]	11880	1			T11	4		T4	2		T5	161
valid_sources[0x32]	13333	1			T12	2		T4	1		T5	177
valid_sources[0x33]	11199	1			T12	1		T4	4		T5	207
valid_sources[0x34]	11237	1			T4	4		T5	139		T21	1
valid_sources[0x35]	11460	1			T11	6		T12	1		T4	5
valid_sources[0x36]	10723	1			T4	5		T5	164		T18	4
valid_sources[0x37]	11160	1			T11	3		T4	4		T5	180
valid_sources[0x38]	12679	1			T4	4		T5	163		T21	1
valid_sources[0x39]	10689	1			T5	141		T18	6		T30	5
valid_sources[0x3a]	14658	1			T11	6		T4	3		T5	177
valid_sources[0x3b]	17708	1			T1	1		T11	1		T4	2
valid_sources[0x3c]	10890	1			T10	1		T12	2		T4	2
valid_sources[0x3d]	10851	1			T11	3		T4	4		T5	166
valid_sources[0x3e]	11034	1			T11	1		T4	2		T5	161
valid_sources[0x3f]	10956	1			T11	12		T4	3		T5	147
valid_sources[0x40]	10994	1			T10	1		T12	2		T4	4
valid_sources[0x41]	12216	1			T11	5		T4	6		T5	146
valid_sources[0x42]	13713	1			T4	5		T5	167		T21	1
valid_sources[0x43]	11123	1			T4	2		T5	176		T7	4
valid_sources[0x44]	61365	1			T4	4		T5	179		T18	4
valid_sources[0x45]	17876	1			T12	1		T4	1		T5	153
valid_sources[0x46]	12314	1			T4	1		T5	143		T21	1
valid_sources[0x47]	91228	1			T11	4		T4	6		T5	149
valid_sources[0x48]	10575	1			T10	1		T11	2		T4	2
valid_sources[0x49]	18464	1			T4	3		T5	159		T21	1
valid_sources[0x4a]	172548	1			T11	2		T5	167		T18	1
valid_sources[0x4b]	12246	1			T10	1		T11	1		T4	3
valid_sources[0x4c]	10570	1			T11	4		T12	1		T4	2
valid_sources[0x4d]	10646	1			T11	3		T4	4		T5	158
valid_sources[0x4e]	12074	1			T11	2		T4	1		T5	166
valid_sources[0x4f]	139718	1			T11	4		T12	1		T4	2
valid_sources[0x50]	14319	1			T4	5		T5	169		T18	3
valid_sources[0x51]	12003	1			T11	10		T4	1		T5	166
valid_sources[0x52]	10910	1			T4	2		T5	169		T18	4
valid_sources[0x53]	10485	1			T10	1		T11	3		T4	2
valid_sources[0x54]	11313	1			T10	1		T11	6		T12	1
valid_sources[0x55]	11042	1			T4	5		T5	152		T30	8
valid_sources[0x56]	11206	1			T11	7		T4	5		T5	147
valid_sources[0x57]	12945	1			T1	1		T10	1		T11	2
valid_sources[0x58]	14650	1			T11	1		T4	3		T5	141
valid_sources[0x59]	11008	1			T1	3		T11	3		T5	167
valid_sources[0x5a]	12336	1			T11	3		T4	4		T5	146
valid_sources[0x5b]	13377	1			T4	4		T5	146		T18	1
valid_sources[0x5c]	10905	1			T1	4		T11	1		T4	2
valid_sources[0x5d]	11433	1			T10	1		T4	1		T5	170
valid_sources[0x5e]	26541	1			T11	2		T4	1		T5	205
valid_sources[0x5f]	21984	1			T11	18		T12	2		T5	150
valid_sources[0x60]	11206	1			T4	1		T5	161		T18	2
valid_sources[0x61]	11996	1			T11	2		T4	4		T5	159
valid_sources[0x62]	10379	1			T1	5		T4	2		T5	163
valid_sources[0x63]	10521	1			T11	11		T4	7		T5	126
valid_sources[0x64]	29922	1			T10	2		T4	3		T5	154
valid_sources[0x65]	11099	1			T11	4		T4	5		T5	150
valid_sources[0x66]	10740	1			T4	5		T5	164		T18	4
valid_sources[0x67]	11102	1			T11	5		T4	1		T5	181
valid_sources[0x68]	10953	1			T1	2		T12	1		T5	148
valid_sources[0x69]	11920	1			T11	1		T4	5		T5	146
valid_sources[0x6a]	10986	1			T4	2		T5	168		T7	1
valid_sources[0x6b]	11692	1			T11	3		T4	9		T5	154
valid_sources[0x6c]	11219	1			T4	1		T5	135		T18	4
valid_sources[0x6d]	10535	1			T4	8		T5	160		T22	1
valid_sources[0x6e]	13166	1			T11	5		T4	4		T5	170
valid_sources[0x6f]	10732	1			T11	2		T4	7		T5	160
valid_sources[0x70]	11195	1			T12	3		T4	1		T5	183
valid_sources[0x71]	10425	1			T11	7		T4	6		T5	181
valid_sources[0x72]	11328	1			T4	4		T5	183		T21	4
valid_sources[0x73]	13306	1			T4	5		T5	171		T18	1
valid_sources[0x74]	10954	1			T12	1		T4	2		T5	150
valid_sources[0x75]	10780	1			T11	3		T4	1		T5	171
valid_sources[0x76]	10972	1			T4	4		T5	162		T22	3
valid_sources[0x77]	13302	1			T10	1		T11	2		T12	4
valid_sources[0x78]	11704	1			T11	12		T4	1		T5	153
valid_sources[0x79]	10828	1			T4	5		T5	165		T18	2
valid_sources[0x7a]	12316	1			T4	4		T5	144		T21	1
valid_sources[0x7b]	11194	1			T1	2		T11	4		T4	1
valid_sources[0x7c]	13782	1			T12	1		T4	4		T5	145
valid_sources[0x7d]	10683	1			T11	5		T4	6		T5	140
valid_sources[0x7e]	10926	1			T1	1		T11	5		T12	1
valid_sources[0x7f]	14479	1			T11	3		T4	6		T5	146
valid_sources[0x80]	11801	1			T1	1		T11	2		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1748534

1

T1

20

T2

1017

T3

717

values[0x0]

all_enables

biggest_size

152137

1

T2

288

T3

180

T10

8

values[0x1]

all_enables

biggest_size

150520

1

T2

253

T3

201

T10

3