Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	107153640	13852	0	0
claim_transition_if_regwen_rd_A	107153640	2356	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107153640	13852	0	0
T5	180470	2	0	0
T6	64423	0	0	0
T7	52820	0	0	0
T15	79451	0	0	0
T16	184256	0	0	0
T17	37121	0	0	0
T18	56463	0	0	0
T21	2292	0	0	0
T22	2430	0	0	0
T30	17647	0	0	0
T42	0	1	0	0
T46	0	5	0	0
T57	0	7	0	0
T88	0	4	0	0
T93	0	3	0	0
T95	0	2	0	0
T147	0	6	0	0
T148	0	8	0	0
T149	0	8	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107153640	2356	0	0
T42	333174	0	0	0
T56	207334	0	0	0
T59	151942	0	0	0
T93	149478	9	0	0
T95	0	1	0	0
T110	283788	0	0	0
T147	0	10	0	0
T150	0	7	0	0
T151	0	16	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	9	0	0
T155	0	3	0	0
T156	0	227	0	0
T157	296096	0	0	0
T158	33311	0	0	0
T159	210626	0	0	0
T160	228506	0	0	0
T161	34689	0	0	0