| T819 |
/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.739811289 |
|
|
Apr 28 12:52:25 PM PDT 24 |
Apr 28 12:52:36 PM PDT 24 |
594329806 ps |
| T820 |
/workspace/coverage/default/24.lc_ctrl_prog_failure.4119436016 |
|
|
Apr 28 12:53:26 PM PDT 24 |
Apr 28 12:53:29 PM PDT 24 |
62223437 ps |
| T821 |
/workspace/coverage/default/35.lc_ctrl_stress_all.569545639 |
|
|
Apr 28 12:53:55 PM PDT 24 |
Apr 28 12:56:35 PM PDT 24 |
11654648467 ps |
| T822 |
/workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1556473170 |
|
|
Apr 28 12:53:11 PM PDT 24 |
Apr 28 12:53:22 PM PDT 24 |
2060813970 ps |
| T55 |
/workspace/coverage/default/3.lc_ctrl_sec_cm.141447380 |
|
|
Apr 28 12:52:10 PM PDT 24 |
Apr 28 12:52:46 PM PDT 24 |
217763718 ps |
| T823 |
/workspace/coverage/default/5.lc_ctrl_claim_transition_if.2634300208 |
|
|
Apr 28 12:52:15 PM PDT 24 |
Apr 28 12:52:17 PM PDT 24 |
9941018 ps |
| T824 |
/workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1965835162 |
|
|
Apr 28 12:54:12 PM PDT 24 |
Apr 28 12:54:13 PM PDT 24 |
13971331 ps |
| T825 |
/workspace/coverage/default/46.lc_ctrl_alert_test.3620206354 |
|
|
Apr 28 12:54:32 PM PDT 24 |
Apr 28 12:54:34 PM PDT 24 |
40818906 ps |
| T826 |
/workspace/coverage/default/31.lc_ctrl_state_failure.2979768197 |
|
|
Apr 28 12:53:48 PM PDT 24 |
Apr 28 12:54:15 PM PDT 24 |
531919864 ps |
| T827 |
/workspace/coverage/default/33.lc_ctrl_sec_token_mux.2451362328 |
|
|
Apr 28 12:54:03 PM PDT 24 |
Apr 28 12:54:14 PM PDT 24 |
987032832 ps |
| T828 |
/workspace/coverage/default/6.lc_ctrl_jtag_smoke.2768668714 |
|
|
Apr 28 12:52:25 PM PDT 24 |
Apr 28 12:52:30 PM PDT 24 |
445459187 ps |
| T829 |
/workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3419652816 |
|
|
Apr 28 12:53:39 PM PDT 24 |
Apr 28 12:53:40 PM PDT 24 |
16316483 ps |
| T830 |
/workspace/coverage/default/2.lc_ctrl_jtag_smoke.924616484 |
|
|
Apr 28 12:52:05 PM PDT 24 |
Apr 28 12:52:26 PM PDT 24 |
3631271358 ps |
| T831 |
/workspace/coverage/default/23.lc_ctrl_state_failure.1994512317 |
|
|
Apr 28 12:53:27 PM PDT 24 |
Apr 28 12:53:47 PM PDT 24 |
467413607 ps |
| T832 |
/workspace/coverage/default/7.lc_ctrl_errors.2846989735 |
|
|
Apr 28 12:52:25 PM PDT 24 |
Apr 28 12:52:37 PM PDT 24 |
1269986084 ps |
| T105 |
/workspace/coverage/default/2.lc_ctrl_sec_cm.376437275 |
|
|
Apr 28 12:52:15 PM PDT 24 |
Apr 28 12:52:40 PM PDT 24 |
749946110 ps |
| T833 |
/workspace/coverage/default/29.lc_ctrl_state_post_trans.1945314659 |
|
|
Apr 28 12:53:48 PM PDT 24 |
Apr 28 12:53:56 PM PDT 24 |
62155187 ps |
| T834 |
/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2541319396 |
|
|
Apr 28 12:52:50 PM PDT 24 |
Apr 28 12:53:48 PM PDT 24 |
6782370671 ps |
| T835 |
/workspace/coverage/default/42.lc_ctrl_sec_mubi.996567209 |
|
|
Apr 28 12:54:20 PM PDT 24 |
Apr 28 12:54:36 PM PDT 24 |
3031060917 ps |
| T49 |
/workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.4266869522 |
|
|
Apr 28 12:53:00 PM PDT 24 |
Apr 28 01:04:15 PM PDT 24 |
26501204651 ps |
| T836 |
/workspace/coverage/default/43.lc_ctrl_jtag_access.1930088862 |
|
|
Apr 28 12:54:23 PM PDT 24 |
Apr 28 12:54:34 PM PDT 24 |
590631910 ps |
| T837 |
/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.638910696 |
|
|
Apr 28 12:53:10 PM PDT 24 |
Apr 28 12:54:05 PM PDT 24 |
5802661904 ps |
| T838 |
/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2747826841 |
|
|
Apr 28 12:53:09 PM PDT 24 |
Apr 28 12:53:52 PM PDT 24 |
1705311486 ps |
| T839 |
/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3937073887 |
|
|
Apr 28 12:52:28 PM PDT 24 |
Apr 28 12:52:36 PM PDT 24 |
2227109612 ps |
| T840 |
/workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3856109214 |
|
|
Apr 28 12:53:16 PM PDT 24 |
Apr 28 12:53:29 PM PDT 24 |
2827342563 ps |
| T841 |
/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2626541825 |
|
|
Apr 28 12:53:34 PM PDT 24 |
Apr 28 12:53:35 PM PDT 24 |
43000498 ps |
| T842 |
/workspace/coverage/default/25.lc_ctrl_sec_token_digest.1988452215 |
|
|
Apr 28 12:53:33 PM PDT 24 |
Apr 28 12:53:43 PM PDT 24 |
3056469884 ps |
| T843 |
/workspace/coverage/default/2.lc_ctrl_sec_token_mux.2275227235 |
|
|
Apr 28 12:52:07 PM PDT 24 |
Apr 28 12:52:17 PM PDT 24 |
3844238385 ps |
| T844 |
/workspace/coverage/default/14.lc_ctrl_jtag_smoke.2165159006 |
|
|
Apr 28 12:52:56 PM PDT 24 |
Apr 28 12:52:58 PM PDT 24 |
66668783 ps |
| T845 |
/workspace/coverage/default/38.lc_ctrl_sec_mubi.4208445873 |
|
|
Apr 28 12:54:06 PM PDT 24 |
Apr 28 12:54:16 PM PDT 24 |
824677121 ps |
| T221 |
/workspace/coverage/default/6.lc_ctrl_claim_transition_if.3633607918 |
|
|
Apr 28 12:52:21 PM PDT 24 |
Apr 28 12:52:23 PM PDT 24 |
36029204 ps |
| T846 |
/workspace/coverage/default/4.lc_ctrl_sec_token_digest.4149405062 |
|
|
Apr 28 12:52:17 PM PDT 24 |
Apr 28 12:52:26 PM PDT 24 |
589929095 ps |
| T847 |
/workspace/coverage/default/45.lc_ctrl_sec_token_mux.1644150895 |
|
|
Apr 28 12:54:33 PM PDT 24 |
Apr 28 12:54:41 PM PDT 24 |
733849751 ps |
| T848 |
/workspace/coverage/default/8.lc_ctrl_sec_token_digest.794656467 |
|
|
Apr 28 12:52:31 PM PDT 24 |
Apr 28 12:52:42 PM PDT 24 |
620229195 ps |
| T849 |
/workspace/coverage/default/15.lc_ctrl_smoke.3739933484 |
|
|
Apr 28 12:52:59 PM PDT 24 |
Apr 28 12:53:03 PM PDT 24 |
46111677 ps |
| T850 |
/workspace/coverage/default/10.lc_ctrl_security_escalation.3654455707 |
|
|
Apr 28 12:52:41 PM PDT 24 |
Apr 28 12:52:53 PM PDT 24 |
1285090078 ps |
| T851 |
/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2774626375 |
|
|
Apr 28 12:53:40 PM PDT 24 |
Apr 28 12:53:41 PM PDT 24 |
24890610 ps |
| T852 |
/workspace/coverage/default/34.lc_ctrl_errors.4186774513 |
|
|
Apr 28 12:53:57 PM PDT 24 |
Apr 28 12:54:05 PM PDT 24 |
353948658 ps |
| T853 |
/workspace/coverage/default/36.lc_ctrl_errors.4291717960 |
|
|
Apr 28 12:54:00 PM PDT 24 |
Apr 28 12:54:08 PM PDT 24 |
220846890 ps |
| T854 |
/workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2153850662 |
|
|
Apr 28 12:54:32 PM PDT 24 |
Apr 28 12:54:33 PM PDT 24 |
22142722 ps |
| T855 |
/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1824806816 |
|
|
Apr 28 12:52:43 PM PDT 24 |
Apr 28 12:52:45 PM PDT 24 |
12757638 ps |
| T153 |
/workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1521106566 |
|
|
Apr 28 12:52:59 PM PDT 24 |
Apr 28 01:08:35 PM PDT 24 |
104840979034 ps |
| T856 |
/workspace/coverage/default/12.lc_ctrl_jtag_errors.2946370042 |
|
|
Apr 28 12:52:49 PM PDT 24 |
Apr 28 12:53:18 PM PDT 24 |
2065863880 ps |
| T857 |
/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1744892901 |
|
|
Apr 28 12:52:15 PM PDT 24 |
Apr 28 12:53:29 PM PDT 24 |
13167506776 ps |
| T858 |
/workspace/coverage/default/3.lc_ctrl_security_escalation.3490014608 |
|
|
Apr 28 12:52:14 PM PDT 24 |
Apr 28 12:52:23 PM PDT 24 |
278710662 ps |
| T859 |
/workspace/coverage/default/22.lc_ctrl_jtag_access.1482012175 |
|
|
Apr 28 12:53:20 PM PDT 24 |
Apr 28 12:53:27 PM PDT 24 |
7515493143 ps |
| T860 |
/workspace/coverage/default/22.lc_ctrl_smoke.183822431 |
|
|
Apr 28 12:53:24 PM PDT 24 |
Apr 28 12:53:26 PM PDT 24 |
64399446 ps |
| T861 |
/workspace/coverage/default/4.lc_ctrl_state_failure.2430800754 |
|
|
Apr 28 12:52:15 PM PDT 24 |
Apr 28 12:52:43 PM PDT 24 |
1312338125 ps |
| T862 |
/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1562624807 |
|
|
Apr 28 12:53:16 PM PDT 24 |
Apr 28 12:53:18 PM PDT 24 |
13938318 ps |
| T863 |
/workspace/coverage/default/35.lc_ctrl_jtag_access.2491003372 |
|
|
Apr 28 12:53:58 PM PDT 24 |
Apr 28 12:54:00 PM PDT 24 |
94323365 ps |
| T864 |
/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2599880395 |
|
|
Apr 28 12:52:15 PM PDT 24 |
Apr 28 12:53:09 PM PDT 24 |
5768129398 ps |
| T865 |
/workspace/coverage/default/33.lc_ctrl_alert_test.2383185141 |
|
|
Apr 28 12:54:03 PM PDT 24 |
Apr 28 12:54:06 PM PDT 24 |
29125020 ps |
| T866 |
/workspace/coverage/default/12.lc_ctrl_sec_token_mux.156992531 |
|
|
Apr 28 12:52:49 PM PDT 24 |
Apr 28 12:52:55 PM PDT 24 |
159330218 ps |
| T867 |
/workspace/coverage/default/26.lc_ctrl_stress_all.1012203644 |
|
|
Apr 28 12:53:39 PM PDT 24 |
Apr 28 12:56:17 PM PDT 24 |
19234929119 ps |
| T868 |
/workspace/coverage/default/29.lc_ctrl_jtag_access.167879478 |
|
|
Apr 28 12:53:47 PM PDT 24 |
Apr 28 12:53:51 PM PDT 24 |
454309888 ps |
| T869 |
/workspace/coverage/default/36.lc_ctrl_alert_test.1117315242 |
|
|
Apr 28 12:54:04 PM PDT 24 |
Apr 28 12:54:07 PM PDT 24 |
76659193 ps |
| T870 |
/workspace/coverage/default/49.lc_ctrl_jtag_access.2561365498 |
|
|
Apr 28 12:54:38 PM PDT 24 |
Apr 28 12:54:49 PM PDT 24 |
437672503 ps |
| T871 |
/workspace/coverage/default/45.lc_ctrl_stress_all.520620069 |
|
|
Apr 28 12:54:27 PM PDT 24 |
Apr 28 12:55:04 PM PDT 24 |
1638166522 ps |
| T872 |
/workspace/coverage/default/49.lc_ctrl_security_escalation.2837376659 |
|
|
Apr 28 12:54:38 PM PDT 24 |
Apr 28 12:54:50 PM PDT 24 |
474515257 ps |
| T40 |
/workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.767405766 |
|
|
Apr 28 12:52:14 PM PDT 24 |
Apr 28 12:52:16 PM PDT 24 |
26020280 ps |
| T873 |
/workspace/coverage/default/2.lc_ctrl_jtag_access.1150340816 |
|
|
Apr 28 12:52:10 PM PDT 24 |
Apr 28 12:52:16 PM PDT 24 |
1627117080 ps |
| T874 |
/workspace/coverage/default/21.lc_ctrl_smoke.3994356301 |
|
|
Apr 28 12:53:19 PM PDT 24 |
Apr 28 12:53:23 PM PDT 24 |
1237148913 ps |
| T875 |
/workspace/coverage/default/43.lc_ctrl_stress_all.991621309 |
|
|
Apr 28 12:54:23 PM PDT 24 |
Apr 28 12:55:16 PM PDT 24 |
13874382965 ps |
| T876 |
/workspace/coverage/default/21.lc_ctrl_state_post_trans.2629259453 |
|
|
Apr 28 12:53:22 PM PDT 24 |
Apr 28 12:53:31 PM PDT 24 |
199550918 ps |
| T877 |
/workspace/coverage/default/13.lc_ctrl_alert_test.3934562463 |
|
|
Apr 28 12:52:54 PM PDT 24 |
Apr 28 12:52:55 PM PDT 24 |
29940281 ps |
| T878 |
/workspace/coverage/default/49.lc_ctrl_alert_test.2874142883 |
|
|
Apr 28 12:54:35 PM PDT 24 |
Apr 28 12:54:37 PM PDT 24 |
15990412 ps |
| T879 |
/workspace/coverage/default/14.lc_ctrl_alert_test.1256197317 |
|
|
Apr 28 12:52:59 PM PDT 24 |
Apr 28 12:53:01 PM PDT 24 |
74903223 ps |
| T880 |
/workspace/coverage/default/17.lc_ctrl_jtag_smoke.2429015679 |
|
|
Apr 28 12:53:06 PM PDT 24 |
Apr 28 12:53:12 PM PDT 24 |
2386501417 ps |
| T881 |
/workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1167421477 |
|
|
Apr 28 12:52:48 PM PDT 24 |
Apr 28 12:53:01 PM PDT 24 |
2728715919 ps |
| T144 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1991894415 |
|
|
Apr 28 02:54:51 PM PDT 24 |
Apr 28 02:54:53 PM PDT 24 |
107147278 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4025674805 |
|
|
Apr 28 02:55:24 PM PDT 24 |
Apr 28 02:55:27 PM PDT 24 |
316488992 ps |
| T112 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2819329973 |
|
|
Apr 28 02:54:58 PM PDT 24 |
Apr 28 02:55:01 PM PDT 24 |
43851087 ps |
| T113 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.585947973 |
|
|
Apr 28 02:54:31 PM PDT 24 |
Apr 28 02:54:33 PM PDT 24 |
45101100 ps |
| T882 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.152309985 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:35 PM PDT 24 |
68353015 ps |
| T114 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3267016379 |
|
|
Apr 28 02:54:17 PM PDT 24 |
Apr 28 02:54:19 PM PDT 24 |
124196918 ps |
| T209 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2766200757 |
|
|
Apr 28 02:55:24 PM PDT 24 |
Apr 28 02:55:26 PM PDT 24 |
110409634 ps |
| T115 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1278158757 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:48 PM PDT 24 |
463622268 ps |
| T154 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.283688596 |
|
|
Apr 28 02:55:20 PM PDT 24 |
Apr 28 02:55:22 PM PDT 24 |
23562612 ps |
| T883 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3398406519 |
|
|
Apr 28 02:54:51 PM PDT 24 |
Apr 28 02:54:53 PM PDT 24 |
14626852 ps |
| T163 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.38751939 |
|
|
Apr 28 02:55:13 PM PDT 24 |
Apr 28 02:55:14 PM PDT 24 |
56158673 ps |
| T210 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3812373847 |
|
|
Apr 28 02:54:13 PM PDT 24 |
Apr 28 02:54:15 PM PDT 24 |
67866718 ps |
| T155 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.908142538 |
|
|
Apr 28 02:55:02 PM PDT 24 |
Apr 28 02:55:04 PM PDT 24 |
14981701 ps |
| T884 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3598613025 |
|
|
Apr 28 02:54:46 PM PDT 24 |
Apr 28 02:54:47 PM PDT 24 |
12930242 ps |
| T145 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3959817247 |
|
|
Apr 28 02:55:08 PM PDT 24 |
Apr 28 02:55:14 PM PDT 24 |
751529116 ps |
| T146 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3690922025 |
|
|
Apr 28 02:54:14 PM PDT 24 |
Apr 28 02:54:33 PM PDT 24 |
3342032508 ps |
| T116 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4003362690 |
|
|
Apr 28 02:55:14 PM PDT 24 |
Apr 28 02:55:16 PM PDT 24 |
19598602 ps |
| T885 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2955925929 |
|
|
Apr 28 02:54:12 PM PDT 24 |
Apr 28 02:54:14 PM PDT 24 |
35168406 ps |
| T156 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1899408691 |
|
|
Apr 28 02:54:32 PM PDT 24 |
Apr 28 02:54:34 PM PDT 24 |
164275769 ps |
| T164 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3238582800 |
|
|
Apr 28 02:55:17 PM PDT 24 |
Apr 28 02:55:19 PM PDT 24 |
29846690 ps |
| T886 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.211185059 |
|
|
Apr 28 02:55:07 PM PDT 24 |
Apr 28 02:55:09 PM PDT 24 |
51105973 ps |
| T122 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3100248795 |
|
|
Apr 28 02:55:18 PM PDT 24 |
Apr 28 02:55:22 PM PDT 24 |
104479673 ps |
| T117 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4108071456 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:37 PM PDT 24 |
297556563 ps |
| T184 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.992746358 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:26 PM PDT 24 |
69100959 ps |
| T118 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1588940377 |
|
|
Apr 28 02:55:24 PM PDT 24 |
Apr 28 02:55:27 PM PDT 24 |
129755030 ps |
| T143 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3618257895 |
|
|
Apr 28 02:54:50 PM PDT 24 |
Apr 28 02:54:53 PM PDT 24 |
439617038 ps |
| T198 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3800640320 |
|
|
Apr 28 02:55:25 PM PDT 24 |
Apr 28 02:55:26 PM PDT 24 |
29309122 ps |
| T199 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4119489277 |
|
|
Apr 28 02:55:07 PM PDT 24 |
Apr 28 02:55:08 PM PDT 24 |
12706552 ps |
| T121 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3751983917 |
|
|
Apr 28 02:55:15 PM PDT 24 |
Apr 28 02:55:18 PM PDT 24 |
169826947 ps |
| T887 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2083615756 |
|
|
Apr 28 02:55:02 PM PDT 24 |
Apr 28 02:55:05 PM PDT 24 |
63670967 ps |
| T140 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2551674934 |
|
|
Apr 28 02:54:57 PM PDT 24 |
Apr 28 02:54:59 PM PDT 24 |
195674619 ps |
| T888 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.725641947 |
|
|
Apr 28 02:55:05 PM PDT 24 |
Apr 28 02:55:07 PM PDT 24 |
63932975 ps |
| T889 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.678051745 |
|
|
Apr 28 02:55:24 PM PDT 24 |
Apr 28 02:55:25 PM PDT 24 |
27841099 ps |
| T890 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.249180299 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:24 PM PDT 24 |
74805110 ps |
| T211 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1457198370 |
|
|
Apr 28 02:55:00 PM PDT 24 |
Apr 28 02:55:03 PM PDT 24 |
92562089 ps |
| T141 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1935934829 |
|
|
Apr 28 02:55:05 PM PDT 24 |
Apr 28 02:55:29 PM PDT 24 |
4433321950 ps |
| T891 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4085585770 |
|
|
Apr 28 02:54:07 PM PDT 24 |
Apr 28 02:54:13 PM PDT 24 |
752770769 ps |
| T142 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1221364804 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:05 PM PDT 24 |
400235644 ps |
| T892 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.436945664 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:28 PM PDT 24 |
411412588 ps |
| T893 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.214315352 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:48 PM PDT 24 |
91061400 ps |
| T894 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4212331681 |
|
|
Apr 28 02:54:34 PM PDT 24 |
Apr 28 02:54:42 PM PDT 24 |
683720237 ps |
| T124 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2579037963 |
|
|
Apr 28 02:55:12 PM PDT 24 |
Apr 28 02:55:14 PM PDT 24 |
595965206 ps |
| T212 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2882371859 |
|
|
Apr 28 02:54:51 PM PDT 24 |
Apr 28 02:54:53 PM PDT 24 |
88039231 ps |
| T895 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.306732771 |
|
|
Apr 28 02:54:57 PM PDT 24 |
Apr 28 02:54:59 PM PDT 24 |
149530909 ps |
| T896 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2239970436 |
|
|
Apr 28 02:54:08 PM PDT 24 |
Apr 28 02:54:10 PM PDT 24 |
193907497 ps |
| T897 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2655072136 |
|
|
Apr 28 02:54:44 PM PDT 24 |
Apr 28 02:54:46 PM PDT 24 |
153168990 ps |
| T898 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3163998643 |
|
|
Apr 28 02:55:08 PM PDT 24 |
Apr 28 02:55:09 PM PDT 24 |
68176723 ps |
| T899 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3932774686 |
|
|
Apr 28 02:54:12 PM PDT 24 |
Apr 28 02:54:14 PM PDT 24 |
52915238 ps |
| T213 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4134238282 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:47 PM PDT 24 |
79428282 ps |
| T127 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.755518195 |
|
|
Apr 28 02:55:18 PM PDT 24 |
Apr 28 02:55:22 PM PDT 24 |
204807458 ps |
| T214 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.346365606 |
|
|
Apr 28 02:54:55 PM PDT 24 |
Apr 28 02:54:56 PM PDT 24 |
18053108 ps |
| T215 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3175551699 |
|
|
Apr 28 02:55:20 PM PDT 24 |
Apr 28 02:55:22 PM PDT 24 |
33490235 ps |
| T216 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3532279336 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:35 PM PDT 24 |
28788862 ps |
| T900 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1798391666 |
|
|
Apr 28 02:54:13 PM PDT 24 |
Apr 28 02:54:16 PM PDT 24 |
172065932 ps |
| T119 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1590269486 |
|
|
Apr 28 02:55:12 PM PDT 24 |
Apr 28 02:55:15 PM PDT 24 |
107442202 ps |
| T217 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3789497504 |
|
|
Apr 28 02:55:19 PM PDT 24 |
Apr 28 02:55:20 PM PDT 24 |
49746094 ps |
| T207 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1882320875 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:49 PM PDT 24 |
91838216 ps |
| T901 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.462088324 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:28 PM PDT 24 |
237162634 ps |
| T902 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2835980842 |
|
|
Apr 28 02:54:58 PM PDT 24 |
Apr 28 02:55:03 PM PDT 24 |
594513267 ps |
| T903 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3334137782 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:24 PM PDT 24 |
37850180 ps |
| T904 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.412108769 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:24 PM PDT 24 |
21677347 ps |
| T905 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.175756759 |
|
|
Apr 28 02:54:56 PM PDT 24 |
Apr 28 02:55:00 PM PDT 24 |
683119521 ps |
| T906 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3619036413 |
|
|
Apr 28 02:54:56 PM PDT 24 |
Apr 28 02:54:58 PM PDT 24 |
85687398 ps |
| T907 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1475067164 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:35 PM PDT 24 |
23430105 ps |
| T200 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3738255568 |
|
|
Apr 28 02:55:20 PM PDT 24 |
Apr 28 02:55:22 PM PDT 24 |
15882341 ps |
| T908 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3724755751 |
|
|
Apr 28 02:54:07 PM PDT 24 |
Apr 28 02:54:11 PM PDT 24 |
83373050 ps |
| T909 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3327293846 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:06 PM PDT 24 |
1765582423 ps |
| T201 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2377765681 |
|
|
Apr 28 02:54:46 PM PDT 24 |
Apr 28 02:54:47 PM PDT 24 |
20920011 ps |
| T910 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3490945670 |
|
|
Apr 28 02:55:25 PM PDT 24 |
Apr 28 02:55:27 PM PDT 24 |
72651442 ps |
| T911 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2210045609 |
|
|
Apr 28 02:55:29 PM PDT 24 |
Apr 28 02:55:31 PM PDT 24 |
35759429 ps |
| T912 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1505205678 |
|
|
Apr 28 02:54:12 PM PDT 24 |
Apr 28 02:54:13 PM PDT 24 |
236070549 ps |
| T202 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1156848650 |
|
|
Apr 28 02:54:40 PM PDT 24 |
Apr 28 02:54:42 PM PDT 24 |
61568973 ps |
| T913 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3399362328 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:24 PM PDT 24 |
13630440 ps |
| T914 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2972516656 |
|
|
Apr 28 02:55:18 PM PDT 24 |
Apr 28 02:55:20 PM PDT 24 |
80105843 ps |
| T120 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1970938242 |
|
|
Apr 28 02:54:51 PM PDT 24 |
Apr 28 02:54:56 PM PDT 24 |
161624011 ps |
| T915 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1614632820 |
|
|
Apr 28 02:55:09 PM PDT 24 |
Apr 28 02:55:11 PM PDT 24 |
47675465 ps |
| T916 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2028970596 |
|
|
Apr 28 02:55:20 PM PDT 24 |
Apr 28 02:55:22 PM PDT 24 |
56388926 ps |
| T917 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2344757944 |
|
|
Apr 28 02:54:17 PM PDT 24 |
Apr 28 02:54:19 PM PDT 24 |
79262832 ps |
| T135 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3960189395 |
|
|
Apr 28 02:55:09 PM PDT 24 |
Apr 28 02:55:12 PM PDT 24 |
61140146 ps |
| T918 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2444629454 |
|
|
Apr 28 02:55:09 PM PDT 24 |
Apr 28 02:55:11 PM PDT 24 |
232031451 ps |
| T919 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3602572371 |
|
|
Apr 28 02:54:46 PM PDT 24 |
Apr 28 02:54:59 PM PDT 24 |
1604972495 ps |
| T920 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3956601581 |
|
|
Apr 28 02:54:08 PM PDT 24 |
Apr 28 02:54:09 PM PDT 24 |
56639908 ps |
| T129 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4181828997 |
|
|
Apr 28 02:55:10 PM PDT 24 |
Apr 28 02:55:11 PM PDT 24 |
50277719 ps |
| T921 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.497636166 |
|
|
Apr 28 02:54:46 PM PDT 24 |
Apr 28 02:54:48 PM PDT 24 |
90753874 ps |
| T922 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2539310062 |
|
|
Apr 28 02:54:50 PM PDT 24 |
Apr 28 02:54:52 PM PDT 24 |
14666253 ps |
| T923 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.491488844 |
|
|
Apr 28 02:54:40 PM PDT 24 |
Apr 28 02:54:42 PM PDT 24 |
58219884 ps |
| T924 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3098559479 |
|
|
Apr 28 02:55:14 PM PDT 24 |
Apr 28 02:55:16 PM PDT 24 |
16810614 ps |
| T925 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2578704651 |
|
|
Apr 28 02:55:16 PM PDT 24 |
Apr 28 02:55:18 PM PDT 24 |
28891164 ps |
| T926 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2645012719 |
|
|
Apr 28 02:55:08 PM PDT 24 |
Apr 28 02:55:19 PM PDT 24 |
1197899678 ps |
| T927 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2708638522 |
|
|
Apr 28 02:55:19 PM PDT 24 |
Apr 28 02:55:21 PM PDT 24 |
119392987 ps |
| T136 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1576333807 |
|
|
Apr 28 02:55:20 PM PDT 24 |
Apr 28 02:55:24 PM PDT 24 |
104108026 ps |
| T928 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3471634823 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:04 PM PDT 24 |
24876814 ps |
| T139 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.273133508 |
|
|
Apr 28 02:55:07 PM PDT 24 |
Apr 28 02:55:12 PM PDT 24 |
121170634 ps |
| T203 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3863820043 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:47 PM PDT 24 |
22332742 ps |
| T133 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1828790086 |
|
|
Apr 28 02:55:24 PM PDT 24 |
Apr 28 02:55:33 PM PDT 24 |
608697283 ps |
| T131 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.339930825 |
|
|
Apr 28 02:54:49 PM PDT 24 |
Apr 28 02:54:52 PM PDT 24 |
65709862 ps |
| T929 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2754280278 |
|
|
Apr 28 02:55:09 PM PDT 24 |
Apr 28 02:55:11 PM PDT 24 |
47146428 ps |
| T930 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2242670412 |
|
|
Apr 28 02:55:12 PM PDT 24 |
Apr 28 02:55:14 PM PDT 24 |
97437831 ps |
| T130 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2103806012 |
|
|
Apr 28 02:54:57 PM PDT 24 |
Apr 28 02:55:01 PM PDT 24 |
545433153 ps |
| T931 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1534301290 |
|
|
Apr 28 02:54:41 PM PDT 24 |
Apr 28 02:54:43 PM PDT 24 |
53080485 ps |
| T932 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1908424529 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:03 PM PDT 24 |
23713134 ps |
| T933 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1488498699 |
|
|
Apr 28 02:55:10 PM PDT 24 |
Apr 28 02:55:11 PM PDT 24 |
174255427 ps |
| T934 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1724030377 |
|
|
Apr 28 02:55:06 PM PDT 24 |
Apr 28 02:55:08 PM PDT 24 |
38699973 ps |
| T132 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1643240308 |
|
|
Apr 28 02:54:09 PM PDT 24 |
Apr 28 02:54:12 PM PDT 24 |
108429258 ps |
| T204 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3430251470 |
|
|
Apr 28 02:55:14 PM PDT 24 |
Apr 28 02:55:15 PM PDT 24 |
67596439 ps |
| T935 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2748323594 |
|
|
Apr 28 02:55:00 PM PDT 24 |
Apr 28 02:55:02 PM PDT 24 |
19053967 ps |
| T936 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4252588045 |
|
|
Apr 28 02:54:21 PM PDT 24 |
Apr 28 02:54:23 PM PDT 24 |
14855328 ps |
| T937 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.108618687 |
|
|
Apr 28 02:54:18 PM PDT 24 |
Apr 28 02:54:20 PM PDT 24 |
969518240 ps |
| T205 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.653260417 |
|
|
Apr 28 02:55:23 PM PDT 24 |
Apr 28 02:55:24 PM PDT 24 |
56344031 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1747874564 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:12 PM PDT 24 |
1282015689 ps |
| T939 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1543679037 |
|
|
Apr 28 02:55:12 PM PDT 24 |
Apr 28 02:55:13 PM PDT 24 |
14236074 ps |
| T940 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1761357089 |
|
|
Apr 28 02:54:53 PM PDT 24 |
Apr 28 02:55:13 PM PDT 24 |
17836323397 ps |
| T941 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2106731418 |
|
|
Apr 28 02:55:03 PM PDT 24 |
Apr 28 02:55:07 PM PDT 24 |
99685815 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4018086589 |
|
|
Apr 28 02:55:11 PM PDT 24 |
Apr 28 02:55:13 PM PDT 24 |
54994735 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2975231999 |
|
|
Apr 28 02:54:40 PM PDT 24 |
Apr 28 02:54:42 PM PDT 24 |
36395600 ps |
| T123 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4245101420 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:04 PM PDT 24 |
220830710 ps |
| T944 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3097261910 |
|
|
Apr 28 02:54:55 PM PDT 24 |
Apr 28 02:54:56 PM PDT 24 |
57577026 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.943974407 |
|
|
Apr 28 02:54:11 PM PDT 24 |
Apr 28 02:54:22 PM PDT 24 |
2325907595 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3550022339 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:48 PM PDT 24 |
258914713 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.978842204 |
|
|
Apr 28 02:54:06 PM PDT 24 |
Apr 28 02:54:10 PM PDT 24 |
119817453 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4107563596 |
|
|
Apr 28 02:54:21 PM PDT 24 |
Apr 28 02:54:23 PM PDT 24 |
120559180 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1753073270 |
|
|
Apr 28 02:54:39 PM PDT 24 |
Apr 28 02:54:41 PM PDT 24 |
14476798 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3842161349 |
|
|
Apr 28 02:54:07 PM PDT 24 |
Apr 28 02:54:18 PM PDT 24 |
841229374 ps |
| T951 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1180109957 |
|
|
Apr 28 02:54:44 PM PDT 24 |
Apr 28 02:54:45 PM PDT 24 |
121543184 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1693028766 |
|
|
Apr 28 02:54:24 PM PDT 24 |
Apr 28 02:54:26 PM PDT 24 |
141673305 ps |
| T953 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.454744726 |
|
|
Apr 28 02:55:13 PM PDT 24 |
Apr 28 02:55:15 PM PDT 24 |
105736337 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3887290320 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:36 PM PDT 24 |
169973914 ps |
| T125 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.59057393 |
|
|
Apr 28 02:55:14 PM PDT 24 |
Apr 28 02:55:19 PM PDT 24 |
109175849 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.617441736 |
|
|
Apr 28 02:55:09 PM PDT 24 |
Apr 28 02:55:12 PM PDT 24 |
172221059 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.354059450 |
|
|
Apr 28 02:54:28 PM PDT 24 |
Apr 28 02:54:29 PM PDT 24 |
39053645 ps |
| T957 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.561016942 |
|
|
Apr 28 02:55:23 PM PDT 24 |
Apr 28 02:55:24 PM PDT 24 |
14072130 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3299291434 |
|
|
Apr 28 02:54:58 PM PDT 24 |
Apr 28 02:55:00 PM PDT 24 |
103251460 ps |
| T959 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.843336952 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:54 PM PDT 24 |
678242413 ps |
| T137 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1585497734 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:37 PM PDT 24 |
209333306 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1577642693 |
|
|
Apr 28 02:55:06 PM PDT 24 |
Apr 28 02:55:08 PM PDT 24 |
165915655 ps |
| T961 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.686661769 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:04 PM PDT 24 |
243293888 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.330737218 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:25 PM PDT 24 |
90236923 ps |
| T963 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2614468712 |
|
|
Apr 28 02:54:43 PM PDT 24 |
Apr 28 02:54:45 PM PDT 24 |
162933041 ps |
| T134 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1354385724 |
|
|
Apr 28 02:55:10 PM PDT 24 |
Apr 28 02:55:13 PM PDT 24 |
119665783 ps |
| T964 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.411093255 |
|
|
Apr 28 02:54:34 PM PDT 24 |
Apr 28 02:54:39 PM PDT 24 |
997742729 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2445865247 |
|
|
Apr 28 02:55:07 PM PDT 24 |
Apr 28 02:55:08 PM PDT 24 |
26508016 ps |
| T966 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3401613718 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:04 PM PDT 24 |
213269614 ps |
| T967 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.930370455 |
|
|
Apr 28 02:55:05 PM PDT 24 |
Apr 28 02:55:08 PM PDT 24 |
124210416 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2723924709 |
|
|
Apr 28 02:54:40 PM PDT 24 |
Apr 28 02:54:43 PM PDT 24 |
22355228 ps |
| T969 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.22084223 |
|
|
Apr 28 02:55:09 PM PDT 24 |
Apr 28 02:55:12 PM PDT 24 |
41430578 ps |
| T970 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2325793219 |
|
|
Apr 28 02:55:05 PM PDT 24 |
Apr 28 02:55:41 PM PDT 24 |
1605174010 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.542603591 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:35 PM PDT 24 |
138637341 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.514205254 |
|
|
Apr 28 02:54:24 PM PDT 24 |
Apr 28 02:54:31 PM PDT 24 |
2491781993 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.638105472 |
|
|
Apr 28 02:54:46 PM PDT 24 |
Apr 28 02:54:58 PM PDT 24 |
428778631 ps |
| T974 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1437049213 |
|
|
Apr 28 02:55:12 PM PDT 24 |
Apr 28 02:55:14 PM PDT 24 |
51158468 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3078386941 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:35 PM PDT 24 |
57832143 ps |
| T126 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1853168934 |
|
|
Apr 28 02:55:01 PM PDT 24 |
Apr 28 02:55:04 PM PDT 24 |
48880498 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2661859843 |
|
|
Apr 28 02:54:18 PM PDT 24 |
Apr 28 02:54:20 PM PDT 24 |
182450565 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4117993842 |
|
|
Apr 28 02:55:11 PM PDT 24 |
Apr 28 02:55:16 PM PDT 24 |
684505680 ps |
| T978 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2573857847 |
|
|
Apr 28 02:55:25 PM PDT 24 |
Apr 28 02:55:28 PM PDT 24 |
282474300 ps |
| T979 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3928796651 |
|
|
Apr 28 02:54:13 PM PDT 24 |
Apr 28 02:54:15 PM PDT 24 |
20378958 ps |
| T980 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4210452747 |
|
|
Apr 28 02:55:27 PM PDT 24 |
Apr 28 02:55:30 PM PDT 24 |
29616635 ps |
| T981 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2441437352 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:46 PM PDT 24 |
17624311 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2332723953 |
|
|
Apr 28 02:54:45 PM PDT 24 |
Apr 28 02:54:50 PM PDT 24 |
109949289 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.635469434 |
|
|
Apr 28 02:55:08 PM PDT 24 |
Apr 28 02:55:12 PM PDT 24 |
102906638 ps |
| T984 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1761679455 |
|
|
Apr 28 02:55:09 PM PDT 24 |
Apr 28 02:55:12 PM PDT 24 |
432388571 ps |
| T985 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3063082078 |
|
|
Apr 28 02:55:07 PM PDT 24 |
Apr 28 02:55:09 PM PDT 24 |
16012481 ps |
| T986 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3573995351 |
|
|
Apr 28 02:55:24 PM PDT 24 |
Apr 28 02:55:25 PM PDT 24 |
29145760 ps |
| T987 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4150147464 |
|
|
Apr 28 02:55:13 PM PDT 24 |
Apr 28 02:55:14 PM PDT 24 |
61182491 ps |
| T988 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2106535579 |
|
|
Apr 28 02:54:12 PM PDT 24 |
Apr 28 02:54:14 PM PDT 24 |
45298960 ps |
| T989 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1122449022 |
|
|
Apr 28 02:54:57 PM PDT 24 |
Apr 28 02:55:03 PM PDT 24 |
1963688509 ps |
| T206 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2232581799 |
|
|
Apr 28 02:54:28 PM PDT 24 |
Apr 28 02:54:30 PM PDT 24 |
14779307 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3602264616 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:35 PM PDT 24 |
19440891 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2723821201 |
|
|
Apr 28 02:54:31 PM PDT 24 |
Apr 28 02:54:35 PM PDT 24 |
399854745 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2082358503 |
|
|
Apr 28 02:54:02 PM PDT 24 |
Apr 28 02:54:06 PM PDT 24 |
743012211 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.198593737 |
|
|
Apr 28 02:54:22 PM PDT 24 |
Apr 28 02:54:25 PM PDT 24 |
37347505 ps |
| T994 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1173018528 |
|
|
Apr 28 02:55:03 PM PDT 24 |
Apr 28 02:55:06 PM PDT 24 |
139639114 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2305579842 |
|
|
Apr 28 02:55:20 PM PDT 24 |
Apr 28 02:55:23 PM PDT 24 |
32838091 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1383453997 |
|
|
Apr 28 02:54:33 PM PDT 24 |
Apr 28 02:54:41 PM PDT 24 |
1330558784 ps |
| T138 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1520152977 |
|
|
Apr 28 02:54:44 PM PDT 24 |
Apr 28 02:54:47 PM PDT 24 |
63860852 ps |
| T997 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4151168266 |
|
|
Apr 28 02:55:02 PM PDT 24 |
Apr 28 02:55:04 PM PDT 24 |
54663323 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2431958551 |
|
|
Apr 28 02:55:19 PM PDT 24 |
Apr 28 02:55:21 PM PDT 24 |
113465615 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2859390404 |
|
|
Apr 28 02:55:24 PM PDT 24 |
Apr 28 02:55:27 PM PDT 24 |
19622350 ps |
| T1000 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1446904006 |
|
|
Apr 28 02:55:00 PM PDT 24 |
Apr 28 02:55:18 PM PDT 24 |
674520934 ps |
| T208 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.988158134 |
|
|
Apr 28 02:54:11 PM PDT 24 |
Apr 28 02:54:13 PM PDT 24 |
19942195 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3168073381 |
|
|
Apr 28 02:54:29 PM PDT 24 |
Apr 28 02:54:31 PM PDT 24 |
39114111 ps |