Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.89	95.77	93.31	100.00	98.55	98.76	96.29

Total test records in report: 1004

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1002	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.917458113			Apr 28 02:54:07 PM PDT 24	Apr 28 02:54:10 PM PDT 24	468675319 ps
T1003	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2662104130			Apr 28 02:55:25 PM PDT 24	Apr 28 02:55:26 PM PDT 24	18080360 ps
T128	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2406549994			Apr 28 02:55:26 PM PDT 24	Apr 28 02:55:29 PM PDT 24	180302809 ps
T1004	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2882757417			Apr 28 02:54:55 PM PDT 24	Apr 28 02:54:58 PM PDT 24	1244710164 ps

Test location	/workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1529844302
Short name	T5
Test name
Test status
Simulation time	18799604997 ps
CPU time	366.16 seconds
Started	Apr 28 12:54:28 PM PDT 24
Finished	Apr 28 01:00:35 PM PDT 24
Peak memory	421944 kb
Host	smart-804ba836-0310-4e8b-8038-c3cefb836708
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1529844302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1529844302
Directory	/workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.lc_ctrl_security_escalation.499321408
Short name	T2
Test name
Test status
Simulation time	527989218 ps
CPU time	11.49 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:29 PM PDT 24
Peak memory	217868 kb
Host	smart-371f51a1-2182-42ce-8bcb-0ccd703aa9ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499321408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.499321408
Directory	/workspace/40.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_mubi.1663929320
Short name	T13
Test name
Test status
Simulation time	270102070 ps
CPU time	12.15 seconds
Started	Apr 28 12:52:43 PM PDT 24
Finished	Apr 28 12:52:56 PM PDT 24
Peak memory	225884 kb
Host	smart-5fe0fc06-95f4-4ce1-bc98-2824f860bdfd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663929320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1663929320
Directory	/workspace/11.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4025674805
Short name	T111
Test name
Test status
Simulation time	316488992 ps
CPU time	2.52 seconds
Started	Apr 28 02:55:24 PM PDT 24
Finished	Apr 28 02:55:27 PM PDT 24
Peak memory	222168 kb
Host	smart-089358f7-39a6-4537-a9f4-5d5210950f4f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025674805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg _err.4025674805
Directory	/workspace/17.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/32.lc_ctrl_security_escalation.1238542197
Short name	T53
Test name
Test status
Simulation time	1918967347 ps
CPU time	13.99 seconds
Started	Apr 28 12:53:51 PM PDT 24
Finished	Apr 28 12:54:06 PM PDT 24
Peak memory	224668 kb
Host	smart-46f02997-e253-4e6e-983b-3b0367e43d7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238542197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1238542197
Directory	/workspace/32.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2755761854
Short name	T10
Test name
Test status
Simulation time	15918652 ps
CPU time	1.04 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:33 PM PDT 24
Peak memory	208408 kb
Host	smart-149926b2-2881-4ec1-ad8e-f67e4e6320d2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755761854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct rl_volatile_unlock_smoke.2755761854
Directory	/workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3576026798
Short name	T42
Test name
Test status
Simulation time	33317434560 ps
CPU time	651.69 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 01:05:08 PM PDT 24
Peak memory	447680 kb
Host	smart-b333d364-bac1-4e5a-a340-adaef9c9a343
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3576026798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3576026798
Directory	/workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_cm.141447380
Short name	T55
Test name
Test status
Simulation time	217763718 ps
CPU time	35.57 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:46 PM PDT 24
Peak memory	269068 kb
Host	smart-2282ab37-9846-431c-8740-a37579034059
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141447380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.141447380
Directory	/workspace/3.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1278158757
Short name	T115
Test name
Test status
Simulation time	463622268 ps
CPU time	2.15 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:48 PM PDT 24
Peak memory	218892 kb
Host	smart-d7de16a4-f016-466d-9e98-70c3ea56386c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127815 8757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1278158757
Directory	/workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/34.lc_ctrl_jtag_access.44051987
Short name	T7
Test name
Test status
Simulation time	926709248 ps
CPU time	12.7 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	209424 kb
Host	smart-5b345260-81fb-4c97-8c58-040251be51b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44051987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.44051987
Directory	/workspace/34.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3846285775
Short name	T57
Test name
Test status
Simulation time	46879915303 ps
CPU time	424.57 seconds
Started	Apr 28 12:53:31 PM PDT 24
Finished	Apr 28 01:00:36 PM PDT 24
Peak memory	259144 kb
Host	smart-83ae54e3-8014-491b-addb-8a051bc92d10
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3846285775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3846285775
Directory	/workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.lc_ctrl_security_escalation.2350309848
Short name	T162
Test name
Test status
Simulation time	428343886 ps
CPU time	9.72 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:47 PM PDT 24
Peak memory	217788 kb
Host	smart-15cc9186-5e2b-4e29-b6e8-464459dba737
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350309848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2350309848
Directory	/workspace/9.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/25.lc_ctrl_alert_test.4152603756
Short name	T33
Test name
Test status
Simulation time	39123600 ps
CPU time	0.87 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:53:38 PM PDT 24
Peak memory	209308 kb
Host	smart-a49d3a7c-7976-4089-b579-fc427a839d22
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152603756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.4152603756
Directory	/workspace/25.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_mux.3096044946
Short name	T50
Test name
Test status
Simulation time	1933936729 ps
CPU time	10.02 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:14 PM PDT 24
Peak memory	217796 kb
Host	smart-9552e175-f275-4a83-bc09-0b4a6b9f8295
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096044946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux. 3096044946
Directory	/workspace/36.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1899408691
Short name	T156
Test name
Test status
Simulation time	164275769 ps
CPU time	1.72 seconds
Started	Apr 28 02:54:32 PM PDT 24
Finished	Apr 28 02:54:34 PM PDT 24
Peak memory	209704 kb
Host	smart-3ee22740-97ee-47b5-90e0-77b1c0e7f66c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899408691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin g.1899408691
Directory	/workspace/2.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1970938242
Short name	T120
Test name
Test status
Simulation time	161624011 ps
CPU time	4.29 seconds
Started	Apr 28 02:54:51 PM PDT 24
Finished	Apr 28 02:54:56 PM PDT 24
Peak memory	217892 kb
Host	smart-6a555f0e-f2cb-4d94-b7e5-9e22c92d0de7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970938242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1970938242
Directory	/workspace/5.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_failure.2894063199
Short name	T34
Test name
Test status
Simulation time	1641781894 ps
CPU time	36.08 seconds
Started	Apr 28 12:53:44 PM PDT 24
Finished	Apr 28 12:54:21 PM PDT 24
Peak memory	250824 kb
Host	smart-d13a17ef-9722-4181-84d6-ebaa25d3ad84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894063199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2894063199
Directory	/workspace/30.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2158508860
Short name	T46
Test name
Test status
Simulation time	192571859211 ps
CPU time	7008.3 seconds
Started	Apr 28 12:52:42 PM PDT 24
Finished	Apr 28 02:49:32 PM PDT 24
Peak memory	758900 kb
Host	smart-a10cd3d5-2bff-4e80-8bc0-c964134a5464
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2158508860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2158508860
Directory	/workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1643240308
Short name	T132
Test name
Test status
Simulation time	108429258 ps
CPU time	2.78 seconds
Started	Apr 28 02:54:09 PM PDT 24
Finished	Apr 28 02:54:12 PM PDT 24
Peak memory	222292 kb
Host	smart-c9d446c8-f8fb-4826-ab49-ba4f53abdc20
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643240308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_ err.1643240308
Directory	/workspace/0.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/23.lc_ctrl_smoke.1334044040
Short name	T11
Test name
Test status
Simulation time	94649751 ps
CPU time	3.03 seconds
Started	Apr 28 12:53:21 PM PDT 24
Finished	Apr 28 12:53:25 PM PDT 24
Peak memory	217684 kb
Host	smart-1be531c0-bcaa-40e0-8406-997dc4a1a8a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334044040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1334044040
Directory	/workspace/23.lc_ctrl_smoke/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1354385724
Short name	T134
Test name
Test status
Simulation time	119665783 ps
CPU time	3.16 seconds
Started	Apr 28 02:55:10 PM PDT 24
Finished	Apr 28 02:55:13 PM PDT 24
Peak memory	222268 kb
Host	smart-d80662c8-3e39-4008-985a-52794c24ae48
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354385724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg _err.1354385724
Directory	/workspace/11.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.755518195
Short name	T127
Test name
Test status
Simulation time	204807458 ps
CPU time	3.9 seconds
Started	Apr 28 02:55:18 PM PDT 24
Finished	Apr 28 02:55:22 PM PDT 24
Peak memory	217764 kb
Host	smart-92d30a6c-2333-477d-b2c7-249959bfd1d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755518195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_ err.755518195
Directory	/workspace/14.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.339930825
Short name	T131
Test name
Test status
Simulation time	65709862 ps
CPU time	2.6 seconds
Started	Apr 28 02:54:49 PM PDT 24
Finished	Apr 28 02:54:52 PM PDT 24
Peak memory	217784 kb
Host	smart-d4640aad-767b-4804-a262-e54e6fd5a43e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339930825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e rr.339930825
Directory	/workspace/5.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3812373847
Short name	T210
Test name
Test status
Simulation time	67866718 ps
CPU time	1.24 seconds
Started	Apr 28 02:54:13 PM PDT 24
Finished	Apr 28 02:54:15 PM PDT 24
Peak memory	209596 kb
Host	smart-cf25938b-81ba-49f8-bdef-3610671f8700
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812373847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _same_csr_outstanding.3812373847
Directory	/workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/default/4.lc_ctrl_security_escalation.194903893
Short name	T51
Test name
Test status
Simulation time	434771299 ps
CPU time	5.7 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	224152 kb
Host	smart-e10670f0-4416-4d46-b327-3f4e00e55617
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194903893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.194903893
Directory	/workspace/4.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3100248795
Short name	T122
Test name
Test status
Simulation time	104479673 ps
CPU time	3.89 seconds
Started	Apr 28 02:55:18 PM PDT 24
Finished	Apr 28 02:55:22 PM PDT 24
Peak memory	217752 kb
Host	smart-e7b24fe9-b1fb-4b41-90c1-7bd169e9fef2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100248795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg _err.3100248795
Directory	/workspace/15.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1828790086
Short name	T133
Test name
Test status
Simulation time	608697283 ps
CPU time	7.48 seconds
Started	Apr 28 02:55:24 PM PDT 24
Finished	Apr 28 02:55:33 PM PDT 24
Peak memory	217784 kb
Host	smart-1cb8ef04-2afd-4851-bd42-4a8240051446
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828790086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg _err.1828790086
Directory	/workspace/19.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4245101420
Short name	T123
Test name
Test status
Simulation time	220830710 ps
CPU time	2.04 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:04 PM PDT 24
Peak memory	222100 kb
Host	smart-76b658d1-024c-4644-bdf8-e551dcf5f3b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245101420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_ err.4245101420
Directory	/workspace/8.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.lc_ctrl_claim_transition_if.2241231941
Short name	T222
Test name
Test status
Simulation time	57977218 ps
CPU time	0.88 seconds
Started	Apr 28 12:52:05 PM PDT 24
Finished	Apr 28 12:52:07 PM PDT 24
Peak memory	209224 kb
Host	smart-ed2e3a85-58f0-4b3b-962b-5c8b2f407901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241231941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2241231941
Directory	/workspace/1.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/6.lc_ctrl_claim_transition_if.3633607918
Short name	T221
Test name
Test status
Simulation time	36029204 ps
CPU time	0.83 seconds
Started	Apr 28 12:52:21 PM PDT 24
Finished	Apr 28 12:52:23 PM PDT 24
Peak memory	209192 kb
Host	smart-1492a10e-bd76-41fd-b0d7-aad358d5f2b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633607918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3633607918
Directory	/workspace/6.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/7.lc_ctrl_claim_transition_if.2776606463
Short name	T223
Test name
Test status
Simulation time	12372771 ps
CPU time	0.83 seconds
Started	Apr 28 12:52:29 PM PDT 24
Finished	Apr 28 12:52:32 PM PDT 24
Peak memory	209220 kb
Host	smart-13263601-2c4a-4dd1-97d6-ad75c36997ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776606463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2776606463
Directory	/workspace/7.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/9.lc_ctrl_claim_transition_if.4095730736
Short name	T225
Test name
Test status
Simulation time	18011512 ps
CPU time	0.88 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:33 PM PDT 24
Peak memory	209304 kb
Host	smart-05910292-fee9-4829-aac2-f963d829bb0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095730736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4095730736
Directory	/workspace/9.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3842161349
Short name	T950
Test name
Test status
Simulation time	841229374 ps
CPU time	10.04 seconds
Started	Apr 28 02:54:07 PM PDT 24
Finished	Apr 28 02:54:18 PM PDT 24
Peak memory	209364 kb
Host	smart-a5cacdf3-3766-42e8-80ea-a40c8a747e47
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842161349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3842161349
Directory	/workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.59057393
Short name	T125
Test name
Test status
Simulation time	109175849 ps
CPU time	4.41 seconds
Started	Apr 28 02:55:14 PM PDT 24
Finished	Apr 28 02:55:19 PM PDT 24
Peak memory	217840 kb
Host	smart-73c22c7a-9af6-4c77-aa13-7fc7a9c6600e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59057393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_e rr.59057393
Directory	/workspace/12.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1576333807
Short name	T136
Test name
Test status
Simulation time	104108026 ps
CPU time	2.62 seconds
Started	Apr 28 02:55:20 PM PDT 24
Finished	Apr 28 02:55:24 PM PDT 24
Peak memory	222008 kb
Host	smart-4c21a773-b2c1-48ba-ab25-e9b78496b1cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576333807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg _err.1576333807
Directory	/workspace/16.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.585947973
Short name	T113
Test name
Test status
Simulation time	45101100 ps
CPU time	1.77 seconds
Started	Apr 28 02:54:31 PM PDT 24
Finished	Apr 28 02:54:33 PM PDT 24
Peak memory	221596 kb
Host	smart-9f98d0d8-927c-4119-9f1a-edf103588aff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585947973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e rr.585947973
Directory	/workspace/2.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.577514817
Short name	T48
Test name
Test status
Simulation time	66824139561 ps
CPU time	1282.1 seconds
Started	Apr 28 12:52:53 PM PDT 24
Finished	Apr 28 01:14:16 PM PDT 24
Peak memory	281364 kb
Host	smart-fb0fbdbd-8819-4a44-a1da-4afa8fda1b88
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=577514817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.577514817
Directory	/workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.862583139
Short name	T17
Test name
Test status
Simulation time	757583362 ps
CPU time	16.89 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:17 PM PDT 24
Peak memory	250656 kb
Host	smart-628cab7b-18b5-4abf-962b-0fb47053f9cf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862583139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_ jtag_state_post_trans.862583139
Directory	/workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_errors.329762937
Short name	T16
Test name
Test status
Simulation time	6824308688 ps
CPU time	53.12 seconds
Started	Apr 28 12:52:39 PM PDT 24
Finished	Apr 28 12:53:32 PM PDT 24
Peak memory	217772 kb
Host	smart-08d14846-eb12-4a2a-ba15-f4bd959f744c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329762937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er rors.329762937
Directory	/workspace/10.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2955925929
Short name	T885
Test name
Test status
Simulation time	35168406 ps
CPU time	1.65 seconds
Started	Apr 28 02:54:12 PM PDT 24
Finished	Apr 28 02:54:14 PM PDT 24
Peak memory	209536 kb
Host	smart-34bd93fc-2301-4431-ae16-2e3d0ffd5a74
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955925929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin g.2955925929
Directory	/workspace/0.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3932774686
Short name	T899
Test name
Test status
Simulation time	52915238 ps
CPU time	1.47 seconds
Started	Apr 28 02:54:12 PM PDT 24
Finished	Apr 28 02:54:14 PM PDT 24
Peak memory	209244 kb
Host	smart-fab37a8a-18e2-4d6e-80a6-a2c0160a3528
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932774686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas h.3932774686
Directory	/workspace/0.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.988158134
Short name	T208
Test name
Test status
Simulation time	19942195 ps
CPU time	0.95 seconds
Started	Apr 28 02:54:11 PM PDT 24
Finished	Apr 28 02:54:13 PM PDT 24
Peak memory	210108 kb
Host	smart-dee813c3-299f-4657-a822-bafe5f233bfa
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988158134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset .988158134
Directory	/workspace/0.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3928796651
Short name	T979
Test name
Test status
Simulation time	20378958 ps
CPU time	1.34 seconds
Started	Apr 28 02:54:13 PM PDT 24
Finished	Apr 28 02:54:15 PM PDT 24
Peak memory	217836 kb
Host	smart-aaf96f76-d370-465a-8a43-29d958cf6e82
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928796651 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3928796651
Directory	/workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2106535579
Short name	T988
Test name
Test status
Simulation time	45298960 ps
CPU time	0.83 seconds
Started	Apr 28 02:54:12 PM PDT 24
Finished	Apr 28 02:54:14 PM PDT 24
Peak memory	209044 kb
Host	smart-f0381a7a-ad8d-42c5-815b-8b569e27a103
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106535579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2106535579
Directory	/workspace/0.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2239970436
Short name	T896
Test name
Test status
Simulation time	193907497 ps
CPU time	1.29 seconds
Started	Apr 28 02:54:08 PM PDT 24
Finished	Apr 28 02:54:10 PM PDT 24
Peak memory	209500 kb
Host	smart-a0f3e5ac-3e91-4d39-ae81-841aa4874e1e
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239970436 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2239970436
Directory	/workspace/0.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4085585770
Short name	T891
Test name
Test status
Simulation time	752770769 ps
CPU time	5.67 seconds
Started	Apr 28 02:54:07 PM PDT 24
Finished	Apr 28 02:54:13 PM PDT 24
Peak memory	209304 kb
Host	smart-1bbbc3e4-96e7-45fe-b668-6c3642979fee
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085585770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4085585770
Directory	/workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2082358503
Short name	T992
Test name
Test status
Simulation time	743012211 ps
CPU time	3.09 seconds
Started	Apr 28 02:54:02 PM PDT 24
Finished	Apr 28 02:54:06 PM PDT 24
Peak memory	211020 kb
Host	smart-2003e05d-6eab-4a34-9aab-143053c14f58
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082358503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2082358503
Directory	/workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3724755751
Short name	T908
Test name
Test status
Simulation time	83373050 ps
CPU time	2.66 seconds
Started	Apr 28 02:54:07 PM PDT 24
Finished	Apr 28 02:54:11 PM PDT 24
Peak memory	217860 kb
Host	smart-b2c8c2d1-6e86-4b58-a6c8-2e6de74a1a36
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372475 5751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3724755751
Directory	/workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.917458113
Short name	T1002
Test name
Test status
Simulation time	468675319 ps
CPU time	3.09 seconds
Started	Apr 28 02:54:07 PM PDT 24
Finished	Apr 28 02:54:10 PM PDT 24
Peak memory	209460 kb
Host	smart-d2650d04-a99d-462f-87a2-84e8157cbdcb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917458113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.917458113
Directory	/workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3956601581
Short name	T920
Test name
Test status
Simulation time	56639908 ps
CPU time	0.97 seconds
Started	Apr 28 02:54:08 PM PDT 24
Finished	Apr 28 02:54:09 PM PDT 24
Peak memory	209616 kb
Host	smart-ada99df7-b585-46f5-ba23-63fc9e512a09
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956601581 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3956601581
Directory	/workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.978842204
Short name	T947
Test name
Test status
Simulation time	119817453 ps
CPU time	3.2 seconds
Started	Apr 28 02:54:06 PM PDT 24
Finished	Apr 28 02:54:10 PM PDT 24
Peak memory	217892 kb
Host	smart-3c05f317-625b-4e0a-a0bd-45e9805eb766
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978842204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.978842204
Directory	/workspace/0.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3399362328
Short name	T913
Test name
Test status
Simulation time	13630440 ps
CPU time	0.98 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:24 PM PDT 24
Peak memory	209624 kb
Host	smart-80568266-0828-404e-95a5-a212dac96128
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399362328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin g.3399362328
Directory	/workspace/1.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.330737218
Short name	T962
Test name
Test status
Simulation time	90236923 ps
CPU time	2.38 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:25 PM PDT 24
Peak memory	209604 kb
Host	smart-bf3d0961-eab0-4c64-b3ef-4f7bc586c878
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330737218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash .330737218
Directory	/workspace/1.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.412108769
Short name	T904
Test name
Test status
Simulation time	21677347 ps
CPU time	0.91 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:24 PM PDT 24
Peak memory	210084 kb
Host	smart-2288a905-dc5d-4c93-9a0a-6acce5056913
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412108769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset .412108769
Directory	/workspace/1.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.249180299
Short name	T890
Test name
Test status
Simulation time	74805110 ps
CPU time	1.43 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:24 PM PDT 24
Peak memory	219260 kb
Host	smart-1848652e-c0b6-437b-ab5b-9d0ccf9f1115
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249180299 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.249180299
Directory	/workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4252588045
Short name	T936
Test name
Test status
Simulation time	14855328 ps
CPU time	0.98 seconds
Started	Apr 28 02:54:21 PM PDT 24
Finished	Apr 28 02:54:23 PM PDT 24
Peak memory	209620 kb
Host	smart-3a95db36-dfab-4ed4-9a01-dfe3d719e288
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252588045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.4252588045
Directory	/workspace/1.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2661859843
Short name	T976
Test name
Test status
Simulation time	182450565 ps
CPU time	1.18 seconds
Started	Apr 28 02:54:18 PM PDT 24
Finished	Apr 28 02:54:20 PM PDT 24
Peak memory	209476 kb
Host	smart-feda0a41-86ac-4c15-98e2-66e263b45594
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661859843 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2661859843
Directory	/workspace/1.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.943974407
Short name	T945
Test name
Test status
Simulation time	2325907595 ps
CPU time	9.91 seconds
Started	Apr 28 02:54:11 PM PDT 24
Finished	Apr 28 02:54:22 PM PDT 24
Peak memory	209380 kb
Host	smart-0a430fff-7db4-46e2-9483-0d998eaaab8a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943974407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.lc_ctrl_jtag_csr_aliasing.943974407
Directory	/workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3690922025
Short name	T146
Test name
Test status
Simulation time	3342032508 ps
CPU time	18.36 seconds
Started	Apr 28 02:54:14 PM PDT 24
Finished	Apr 28 02:54:33 PM PDT 24
Peak memory	209560 kb
Host	smart-b2e8a12f-04fe-4945-8971-f048cbd7a684
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690922025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3690922025
Directory	/workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1798391666
Short name	T900
Test name
Test status
Simulation time	172065932 ps
CPU time	2.22 seconds
Started	Apr 28 02:54:13 PM PDT 24
Finished	Apr 28 02:54:16 PM PDT 24
Peak memory	210888 kb
Host	smart-b12f7a8d-bd0b-4c9d-a22a-f565d9443b8f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798391666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1798391666
Directory	/workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.108618687
Short name	T937
Test name
Test status
Simulation time	969518240 ps
CPU time	2 seconds
Started	Apr 28 02:54:18 PM PDT 24
Finished	Apr 28 02:54:20 PM PDT 24
Peak memory	217816 kb
Host	smart-8c232e85-d69d-4220-a8dc-042df65db75b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108618 687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.108618687
Directory	/workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1505205678
Short name	T912
Test name
Test status
Simulation time	236070549 ps
CPU time	1.26 seconds
Started	Apr 28 02:54:12 PM PDT 24
Finished	Apr 28 02:54:13 PM PDT 24
Peak memory	209496 kb
Host	smart-6e67180c-140c-4574-9774-d2a4a7db5d51
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505205678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.1505205678
Directory	/workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2344757944
Short name	T917
Test name
Test status
Simulation time	79262832 ps
CPU time	1.34 seconds
Started	Apr 28 02:54:17 PM PDT 24
Finished	Apr 28 02:54:19 PM PDT 24
Peak memory	211560 kb
Host	smart-6c6aab7f-a1f3-44a3-9aa8-8085771bf44e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344757944 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2344757944
Directory	/workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3334137782
Short name	T903
Test name
Test status
Simulation time	37850180 ps
CPU time	1.36 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:24 PM PDT 24
Peak memory	209636 kb
Host	smart-87995a07-0bb2-4a53-9d58-6a2def21d733
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334137782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _same_csr_outstanding.3334137782
Directory	/workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3267016379
Short name	T114
Test name
Test status
Simulation time	124196918 ps
CPU time	1.87 seconds
Started	Apr 28 02:54:17 PM PDT 24
Finished	Apr 28 02:54:19 PM PDT 24
Peak memory	218000 kb
Host	smart-79e1ef8b-8616-4add-8870-fd74e7746d0d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267016379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3267016379
Directory	/workspace/1.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.992746358
Short name	T184
Test name
Test status
Simulation time	69100959 ps
CPU time	2.55 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:26 PM PDT 24
Peak memory	217828 kb
Host	smart-9d25c608-4bdd-457d-85b9-b5ea45cf23a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992746358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e rr.992746358
Directory	/workspace/1.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1614632820
Short name	T915
Test name
Test status
Simulation time	47675465 ps
CPU time	1.61 seconds
Started	Apr 28 02:55:09 PM PDT 24
Finished	Apr 28 02:55:11 PM PDT 24
Peak memory	218064 kb
Host	smart-ad7b0064-1a43-4078-914c-8ce298160a99
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614632820 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1614632820
Directory	/workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4119489277
Short name	T199
Test name
Test status
Simulation time	12706552 ps
CPU time	0.82 seconds
Started	Apr 28 02:55:07 PM PDT 24
Finished	Apr 28 02:55:08 PM PDT 24
Peak memory	209540 kb
Host	smart-bed40ed0-9511-472b-a907-81ca28dcc36c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119489277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.4119489277
Directory	/workspace/10.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2445865247
Short name	T965
Test name
Test status
Simulation time	26508016 ps
CPU time	1 seconds
Started	Apr 28 02:55:07 PM PDT 24
Finished	Apr 28 02:55:08 PM PDT 24
Peak memory	209604 kb
Host	smart-e6918ef6-9e5e-4898-82cc-108de616bfe3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445865247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_same_csr_outstanding.2445865247
Directory	/workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.617441736
Short name	T955
Test name
Test status
Simulation time	172221059 ps
CPU time	2.65 seconds
Started	Apr 28 02:55:09 PM PDT 24
Finished	Apr 28 02:55:12 PM PDT 24
Peak memory	219100 kb
Host	smart-ff594542-d420-4cab-a7eb-d8a9a85ca079
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617441736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.617441736
Directory	/workspace/10.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3960189395
Short name	T135
Test name
Test status
Simulation time	61140146 ps
CPU time	2 seconds
Started	Apr 28 02:55:09 PM PDT 24
Finished	Apr 28 02:55:12 PM PDT 24
Peak memory	222124 kb
Host	smart-1f639dcf-1563-46df-b12f-1a4772b349ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960189395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg _err.3960189395
Directory	/workspace/10.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3098559479
Short name	T924
Test name
Test status
Simulation time	16810614 ps
CPU time	1.12 seconds
Started	Apr 28 02:55:14 PM PDT 24
Finished	Apr 28 02:55:16 PM PDT 24
Peak memory	219508 kb
Host	smart-373a7a2b-cf88-46f7-9506-27ba9ae28b7e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098559479 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3098559479
Directory	/workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1543679037
Short name	T939
Test name
Test status
Simulation time	14236074 ps
CPU time	0.8 seconds
Started	Apr 28 02:55:12 PM PDT 24
Finished	Apr 28 02:55:13 PM PDT 24
Peak memory	209620 kb
Host	smart-0bd29909-7db8-4f25-9560-bf7c493f9a33
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543679037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1543679037
Directory	/workspace/11.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2578704651
Short name	T925
Test name
Test status
Simulation time	28891164 ps
CPU time	1.12 seconds
Started	Apr 28 02:55:16 PM PDT 24
Finished	Apr 28 02:55:18 PM PDT 24
Peak memory	209644 kb
Host	smart-0b4ee331-2777-4e12-be32-d510b3a5d97a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578704651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_same_csr_outstanding.2578704651
Directory	/workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.22084223
Short name	T969
Test name
Test status
Simulation time	41430578 ps
CPU time	2.93 seconds
Started	Apr 28 02:55:09 PM PDT 24
Finished	Apr 28 02:55:12 PM PDT 24
Peak memory	217948 kb
Host	smart-2fc1504d-c33b-461f-b181-197b857e6c9c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22084223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.22084223
Directory	/workspace/11.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.38751939
Short name	T163
Test name
Test status
Simulation time	56158673 ps
CPU time	0.98 seconds
Started	Apr 28 02:55:13 PM PDT 24
Finished	Apr 28 02:55:14 PM PDT 24
Peak memory	217792 kb
Host	smart-2734c463-e097-4619-bfc0-0de665e01637
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38751939 -assert nopostproc +UVM_TESTNAME=l c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.38751939
Directory	/workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3430251470
Short name	T204
Test name
Test status
Simulation time	67596439 ps
CPU time	0.86 seconds
Started	Apr 28 02:55:14 PM PDT 24
Finished	Apr 28 02:55:15 PM PDT 24
Peak memory	209568 kb
Host	smart-0bd86696-cd64-4003-981e-9b64d49b0a8f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430251470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3430251470
Directory	/workspace/12.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1437049213
Short name	T974
Test name
Test status
Simulation time	51158468 ps
CPU time	1.09 seconds
Started	Apr 28 02:55:12 PM PDT 24
Finished	Apr 28 02:55:14 PM PDT 24
Peak memory	209624 kb
Host	smart-b2f42bf9-9f5c-47c5-b59f-a5c2e07aec74
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437049213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_same_csr_outstanding.1437049213
Directory	/workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1590269486
Short name	T119
Test name
Test status
Simulation time	107442202 ps
CPU time	2.72 seconds
Started	Apr 28 02:55:12 PM PDT 24
Finished	Apr 28 02:55:15 PM PDT 24
Peak memory	217960 kb
Host	smart-7fa00c38-4260-43ad-a57d-0f55df904e95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590269486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1590269486
Directory	/workspace/12.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4003362690
Short name	T116
Test name
Test status
Simulation time	19598602 ps
CPU time	1.23 seconds
Started	Apr 28 02:55:14 PM PDT 24
Finished	Apr 28 02:55:16 PM PDT 24
Peak memory	218224 kb
Host	smart-31cfc623-b247-49ef-be50-3431c01102a8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003362690 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.4003362690
Directory	/workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4150147464
Short name	T987
Test name
Test status
Simulation time	61182491 ps
CPU time	0.79 seconds
Started	Apr 28 02:55:13 PM PDT 24
Finished	Apr 28 02:55:14 PM PDT 24
Peak memory	209076 kb
Host	smart-770ff589-f7f7-437c-b23a-0ff1d7f398d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150147464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4150147464
Directory	/workspace/13.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2242670412
Short name	T930
Test name
Test status
Simulation time	97437831 ps
CPU time	1.46 seconds
Started	Apr 28 02:55:12 PM PDT 24
Finished	Apr 28 02:55:14 PM PDT 24
Peak memory	211704 kb
Host	smart-0bf33b6e-c7a1-43eb-a9eb-1c7db0e83254
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242670412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_same_csr_outstanding.2242670412
Directory	/workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.454744726
Short name	T953
Test name
Test status
Simulation time	105736337 ps
CPU time	1.95 seconds
Started	Apr 28 02:55:13 PM PDT 24
Finished	Apr 28 02:55:15 PM PDT 24
Peak memory	217908 kb
Host	smart-8c06795a-d4da-4fed-a89f-a4e198b9a155
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454744726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.454744726
Directory	/workspace/13.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2579037963
Short name	T124
Test name
Test status
Simulation time	595965206 ps
CPU time	1.73 seconds
Started	Apr 28 02:55:12 PM PDT 24
Finished	Apr 28 02:55:14 PM PDT 24
Peak memory	221868 kb
Host	smart-364e4180-c76a-4eb5-83ae-01570db74130
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579037963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg _err.2579037963
Directory	/workspace/13.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3238582800
Short name	T164
Test name
Test status
Simulation time	29846690 ps
CPU time	1.13 seconds
Started	Apr 28 02:55:17 PM PDT 24
Finished	Apr 28 02:55:19 PM PDT 24
Peak memory	220056 kb
Host	smart-e806ff57-cc09-4a3c-ba79-49e791ea11b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238582800 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3238582800
Directory	/workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3738255568
Short name	T200
Test name
Test status
Simulation time	15882341 ps
CPU time	1.06 seconds
Started	Apr 28 02:55:20 PM PDT 24
Finished	Apr 28 02:55:22 PM PDT 24
Peak memory	209480 kb
Host	smart-56bbdfb5-aa16-4c5b-a4d0-7417af23e802
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738255568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3738255568
Directory	/workspace/14.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3789497504
Short name	T217
Test name
Test status
Simulation time	49746094 ps
CPU time	1.09 seconds
Started	Apr 28 02:55:19 PM PDT 24
Finished	Apr 28 02:55:20 PM PDT 24
Peak memory	209692 kb
Host	smart-7bc37b1f-b6bd-4255-8600-c1bb742f8a62
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789497504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_same_csr_outstanding.3789497504
Directory	/workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3751983917
Short name	T121
Test name
Test status
Simulation time	169826947 ps
CPU time	2.54 seconds
Started	Apr 28 02:55:15 PM PDT 24
Finished	Apr 28 02:55:18 PM PDT 24
Peak memory	217800 kb
Host	smart-d3ddc749-3658-43b8-925d-cf7c1a633476
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751983917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3751983917
Directory	/workspace/14.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2708638522
Short name	T927
Test name
Test status
Simulation time	119392987 ps
CPU time	1.37 seconds
Started	Apr 28 02:55:19 PM PDT 24
Finished	Apr 28 02:55:21 PM PDT 24
Peak memory	219400 kb
Host	smart-0b106473-8952-493d-8120-fbd092ba4e72
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708638522 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2708638522
Directory	/workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2028970596
Short name	T916
Test name
Test status
Simulation time	56388926 ps
CPU time	1.02 seconds
Started	Apr 28 02:55:20 PM PDT 24
Finished	Apr 28 02:55:22 PM PDT 24
Peak memory	209600 kb
Host	smart-a7644d3f-dbdf-4dcc-8e71-2ace6c3a05ba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028970596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2028970596
Directory	/workspace/15.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2972516656
Short name	T914
Test name
Test status
Simulation time	80105843 ps
CPU time	1.39 seconds
Started	Apr 28 02:55:18 PM PDT 24
Finished	Apr 28 02:55:20 PM PDT 24
Peak memory	217756 kb
Host	smart-709fe2cf-8ea1-4742-9101-a0ceabc0c18d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972516656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr l_same_csr_outstanding.2972516656
Directory	/workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2305579842
Short name	T995
Test name
Test status
Simulation time	32838091 ps
CPU time	1.94 seconds
Started	Apr 28 02:55:20 PM PDT 24
Finished	Apr 28 02:55:23 PM PDT 24
Peak memory	217968 kb
Host	smart-0d0e77c7-433f-4841-8c76-31468d999c3f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305579842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2305579842
Directory	/workspace/15.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.283688596
Short name	T154
Test name
Test status
Simulation time	23562612 ps
CPU time	1.43 seconds
Started	Apr 28 02:55:20 PM PDT 24
Finished	Apr 28 02:55:22 PM PDT 24
Peak memory	217828 kb
Host	smart-0319fe12-6960-41b9-98d5-3a4a311aeab8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283688596 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.283688596
Directory	/workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.561016942
Short name	T957
Test name
Test status
Simulation time	14072130 ps
CPU time	0.93 seconds
Started	Apr 28 02:55:23 PM PDT 24
Finished	Apr 28 02:55:24 PM PDT 24
Peak memory	209324 kb
Host	smart-d3792de1-14f1-4592-8575-5c12409f19b0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561016942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.561016942
Directory	/workspace/16.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3175551699
Short name	T215
Test name
Test status
Simulation time	33490235 ps
CPU time	1.18 seconds
Started	Apr 28 02:55:20 PM PDT 24
Finished	Apr 28 02:55:22 PM PDT 24
Peak memory	209556 kb
Host	smart-6b58209b-fa9b-426b-bec1-2767e865b6a2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175551699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.3175551699
Directory	/workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2431958551
Short name	T998
Test name
Test status
Simulation time	113465615 ps
CPU time	2.14 seconds
Started	Apr 28 02:55:19 PM PDT 24
Finished	Apr 28 02:55:21 PM PDT 24
Peak memory	217908 kb
Host	smart-f801dc1a-cb30-412d-9939-21eb8b0c9f79
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431958551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2431958551
Directory	/workspace/16.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2662104130
Short name	T1003
Test name
Test status
Simulation time	18080360 ps
CPU time	1.03 seconds
Started	Apr 28 02:55:25 PM PDT 24
Finished	Apr 28 02:55:26 PM PDT 24
Peak memory	217924 kb
Host	smart-5da20d7d-8c04-4dbd-961e-0a643ff0026e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662104130 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2662104130
Directory	/workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3800640320
Short name	T198
Test name
Test status
Simulation time	29309122 ps
CPU time	0.9 seconds
Started	Apr 28 02:55:25 PM PDT 24
Finished	Apr 28 02:55:26 PM PDT 24
Peak memory	209580 kb
Host	smart-692f426b-b8bf-4e0f-9f43-f63d920d3a8c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800640320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3800640320
Directory	/workspace/17.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2766200757
Short name	T209
Test name
Test status
Simulation time	110409634 ps
CPU time	1.28 seconds
Started	Apr 28 02:55:24 PM PDT 24
Finished	Apr 28 02:55:26 PM PDT 24
Peak memory	211756 kb
Host	smart-4ee5f1bd-6e23-4f5f-975e-6de5ac7886b2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766200757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_same_csr_outstanding.2766200757
Directory	/workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1588940377
Short name	T118
Test name
Test status
Simulation time	129755030 ps
CPU time	1.62 seconds
Started	Apr 28 02:55:24 PM PDT 24
Finished	Apr 28 02:55:27 PM PDT 24
Peak memory	217912 kb
Host	smart-8142e456-30c1-4b6d-ad8f-fe272ad12617
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588940377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1588940377
Directory	/workspace/17.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3573995351
Short name	T986
Test name
Test status
Simulation time	29145760 ps
CPU time	1.26 seconds
Started	Apr 28 02:55:24 PM PDT 24
Finished	Apr 28 02:55:25 PM PDT 24
Peak memory	217844 kb
Host	smart-ea46852f-19fe-4e9d-906c-fa63bc38f294
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573995351 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3573995351
Directory	/workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.653260417
Short name	T205
Test name
Test status
Simulation time	56344031 ps
CPU time	0.81 seconds
Started	Apr 28 02:55:23 PM PDT 24
Finished	Apr 28 02:55:24 PM PDT 24
Peak memory	209524 kb
Host	smart-ab304f10-e5c6-431c-9617-a82d720bd601
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653260417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.653260417
Directory	/workspace/18.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2859390404
Short name	T999
Test name
Test status
Simulation time	19622350 ps
CPU time	1.46 seconds
Started	Apr 28 02:55:24 PM PDT 24
Finished	Apr 28 02:55:27 PM PDT 24
Peak memory	211788 kb
Host	smart-2ff67bf7-cd84-457f-8795-9510b9a42bc0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859390404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_same_csr_outstanding.2859390404
Directory	/workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4210452747
Short name	T980
Test name
Test status
Simulation time	29616635 ps
CPU time	2.15 seconds
Started	Apr 28 02:55:27 PM PDT 24
Finished	Apr 28 02:55:30 PM PDT 24
Peak memory	218108 kb
Host	smart-80a1fe16-9341-4bcc-a9e4-bd3a88c7156d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210452747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4210452747
Directory	/workspace/18.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2406549994
Short name	T128
Test name
Test status
Simulation time	180302809 ps
CPU time	2.38 seconds
Started	Apr 28 02:55:26 PM PDT 24
Finished	Apr 28 02:55:29 PM PDT 24
Peak memory	217816 kb
Host	smart-5a900e82-a1fa-41d1-aa51-48cf4ff94369
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406549994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg _err.2406549994
Directory	/workspace/18.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3490945670
Short name	T910
Test name
Test status
Simulation time	72651442 ps
CPU time	1.35 seconds
Started	Apr 28 02:55:25 PM PDT 24
Finished	Apr 28 02:55:27 PM PDT 24
Peak memory	219732 kb
Host	smart-1589da05-0af6-48a6-a925-57f659fb7a35
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490945670 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3490945670
Directory	/workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.678051745
Short name	T889
Test name
Test status
Simulation time	27841099 ps
CPU time	0.86 seconds
Started	Apr 28 02:55:24 PM PDT 24
Finished	Apr 28 02:55:25 PM PDT 24
Peak memory	209572 kb
Host	smart-0bbbed3e-212c-4355-8326-9b1df8f58b6a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678051745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.678051745
Directory	/workspace/19.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2210045609
Short name	T911
Test name
Test status
Simulation time	35759429 ps
CPU time	1.25 seconds
Started	Apr 28 02:55:29 PM PDT 24
Finished	Apr 28 02:55:31 PM PDT 24
Peak memory	209516 kb
Host	smart-c0f3a5bb-dd47-4b03-a9e6-5a8ddbe6e97c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210045609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr l_same_csr_outstanding.2210045609
Directory	/workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2573857847
Short name	T978
Test name
Test status
Simulation time	282474300 ps
CPU time	2.4 seconds
Started	Apr 28 02:55:25 PM PDT 24
Finished	Apr 28 02:55:28 PM PDT 24
Peak memory	217868 kb
Host	smart-c8b2a1fc-4d18-48a1-9a50-0f2162ab4689
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573857847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2573857847
Directory	/workspace/19.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.152309985
Short name	T882
Test name
Test status
Simulation time	68353015 ps
CPU time	1.77 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:35 PM PDT 24
Peak memory	208792 kb
Host	smart-656b78f3-2408-40ba-8c0f-bb605b9ef231
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152309985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash .152309985
Directory	/workspace/2.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2232581799
Short name	T206
Test name
Test status
Simulation time	14779307 ps
CPU time	1.14 seconds
Started	Apr 28 02:54:28 PM PDT 24
Finished	Apr 28 02:54:30 PM PDT 24
Peak memory	210752 kb
Host	smart-556f4d9e-3064-4463-920c-9e95a502b857
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232581799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese t.2232581799
Directory	/workspace/2.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1475067164
Short name	T907
Test name
Test status
Simulation time	23430105 ps
CPU time	1.84 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:35 PM PDT 24
Peak memory	219300 kb
Host	smart-da5ef7e4-e33a-41e6-ad4d-760251cea334
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475067164 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1475067164
Directory	/workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.354059450
Short name	T956
Test name
Test status
Simulation time	39053645 ps
CPU time	0.93 seconds
Started	Apr 28 02:54:28 PM PDT 24
Finished	Apr 28 02:54:29 PM PDT 24
Peak memory	209548 kb
Host	smart-616e6004-b93b-448e-a761-6399f36ba860
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354059450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.354059450
Directory	/workspace/2.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3168073381
Short name	T1001
Test name
Test status
Simulation time	39114111 ps
CPU time	1.52 seconds
Started	Apr 28 02:54:29 PM PDT 24
Finished	Apr 28 02:54:31 PM PDT 24
Peak memory	209456 kb
Host	smart-2ca1e7bd-f997-4fb0-896b-8290c9a77377
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168073381 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3168073381
Directory	/workspace/2.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.514205254
Short name	T972
Test name
Test status
Simulation time	2491781993 ps
CPU time	6.28 seconds
Started	Apr 28 02:54:24 PM PDT 24
Finished	Apr 28 02:54:31 PM PDT 24
Peak memory	209552 kb
Host	smart-043fe916-c8d1-44b8-a707-b0a380a9e4f4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514205254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_aliasing.514205254
Directory	/workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.436945664
Short name	T892
Test name
Test status
Simulation time	411412588 ps
CPU time	5.39 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:28 PM PDT 24
Peak memory	208732 kb
Host	smart-b6fa51fe-f71e-4523-a43a-f6cf708e46ad
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436945664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.436945664
Directory	/workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.462088324
Short name	T901
Test name
Test status
Simulation time	237162634 ps
CPU time	5.7 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:28 PM PDT 24
Peak memory	211212 kb
Host	smart-0c90bf71-42fa-4e54-bf17-0b93d23b6651
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462088324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.462088324
Directory	/workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4107563596
Short name	T948
Test name
Test status
Simulation time	120559180 ps
CPU time	1.79 seconds
Started	Apr 28 02:54:21 PM PDT 24
Finished	Apr 28 02:54:23 PM PDT 24
Peak memory	217868 kb
Host	smart-cf08c336-8238-41c4-a4b4-85db0966757e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410756 3596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4107563596
Directory	/workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1693028766
Short name	T952
Test name
Test status
Simulation time	141673305 ps
CPU time	1.21 seconds
Started	Apr 28 02:54:24 PM PDT 24
Finished	Apr 28 02:54:26 PM PDT 24
Peak memory	209436 kb
Host	smart-5da97c38-6252-4758-835c-f504ef93977e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693028766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.1693028766
Directory	/workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.198593737
Short name	T993
Test name
Test status
Simulation time	37347505 ps
CPU time	1.75 seconds
Started	Apr 28 02:54:22 PM PDT 24
Finished	Apr 28 02:54:25 PM PDT 24
Peak memory	211808 kb
Host	smart-259d41bd-21ef-4603-ba58-91dc5cf65719
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198593737 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.198593737
Directory	/workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3602264616
Short name	T990
Test name
Test status
Simulation time	19440891 ps
CPU time	1.47 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:35 PM PDT 24
Peak memory	211748 kb
Host	smart-0cdd3ae1-53f8-40d1-9e8a-6f08a87fc371
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602264616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _same_csr_outstanding.3602264616
Directory	/workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2723821201
Short name	T991
Test name
Test status
Simulation time	399854745 ps
CPU time	3.08 seconds
Started	Apr 28 02:54:31 PM PDT 24
Finished	Apr 28 02:54:35 PM PDT 24
Peak memory	217932 kb
Host	smart-0d78efe1-ab26-4b32-880e-b173e204f085
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723821201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2723821201
Directory	/workspace/2.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1156848650
Short name	T202
Test name
Test status
Simulation time	61568973 ps
CPU time	1.38 seconds
Started	Apr 28 02:54:40 PM PDT 24
Finished	Apr 28 02:54:42 PM PDT 24
Peak memory	209556 kb
Host	smart-7b6463f6-a73d-431a-8a3f-935e8ea905ae
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156848650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin g.1156848650
Directory	/workspace/3.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1534301290
Short name	T931
Test name
Test status
Simulation time	53080485 ps
CPU time	2.03 seconds
Started	Apr 28 02:54:41 PM PDT 24
Finished	Apr 28 02:54:43 PM PDT 24
Peak memory	209088 kb
Host	smart-e4dc5ca5-d833-4e6d-bde0-55571aa24b1c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534301290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas h.1534301290
Directory	/workspace/3.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1753073270
Short name	T949
Test name
Test status
Simulation time	14476798 ps
CPU time	1.03 seconds
Started	Apr 28 02:54:39 PM PDT 24
Finished	Apr 28 02:54:41 PM PDT 24
Peak memory	209760 kb
Host	smart-2b1ab739-2a7a-463e-a288-c39c7040cdc4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753073270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese t.1753073270
Directory	/workspace/3.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.491488844
Short name	T923
Test name
Test status
Simulation time	58219884 ps
CPU time	1.19 seconds
Started	Apr 28 02:54:40 PM PDT 24
Finished	Apr 28 02:54:42 PM PDT 24
Peak memory	217900 kb
Host	smart-26671594-44d4-4433-b0c7-ac36307167ce
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491488844 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.491488844
Directory	/workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2975231999
Short name	T943
Test name
Test status
Simulation time	36395600 ps
CPU time	0.87 seconds
Started	Apr 28 02:54:40 PM PDT 24
Finished	Apr 28 02:54:42 PM PDT 24
Peak memory	208976 kb
Host	smart-7281d5b8-f4b5-4e00-8047-cc47dece7081
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975231999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2975231999
Directory	/workspace/3.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.542603591
Short name	T971
Test name
Test status
Simulation time	138637341 ps
CPU time	1.21 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:35 PM PDT 24
Peak memory	209460 kb
Host	smart-d3486223-3fd9-4201-a219-18c831e9439b
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542603591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.lc_ctrl_jtag_alert_test.542603591
Directory	/workspace/3.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1383453997
Short name	T996
Test name
Test status
Simulation time	1330558784 ps
CPU time	6.44 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:41 PM PDT 24
Peak memory	209308 kb
Host	smart-184793b5-e6fa-453d-afdf-fac4c1a03b2e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383453997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1383453997
Directory	/workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4212331681
Short name	T894
Test name
Test status
Simulation time	683720237 ps
CPU time	7.55 seconds
Started	Apr 28 02:54:34 PM PDT 24
Finished	Apr 28 02:54:42 PM PDT 24
Peak memory	209516 kb
Host	smart-f9b73f98-968a-4a30-84f8-abe591322b01
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212331681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4212331681
Directory	/workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3078386941
Short name	T975
Test name
Test status
Simulation time	57832143 ps
CPU time	1.24 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:35 PM PDT 24
Peak memory	210840 kb
Host	smart-ea29da48-555f-4d9b-804b-8a94b79a1063
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078386941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3078386941
Directory	/workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.411093255
Short name	T964
Test name
Test status
Simulation time	997742729 ps
CPU time	4.28 seconds
Started	Apr 28 02:54:34 PM PDT 24
Finished	Apr 28 02:54:39 PM PDT 24
Peak memory	218924 kb
Host	smart-f9146e39-915e-453e-976b-af98910b902c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411093 255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.411093255
Directory	/workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3887290320
Short name	T954
Test name
Test status
Simulation time	169973914 ps
CPU time	1.47 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:36 PM PDT 24
Peak memory	209520 kb
Host	smart-ea1b4eb2-f538-4d30-ae84-1e4d6a6f86c4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887290320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.3887290320
Directory	/workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3532279336
Short name	T216
Test name
Test status
Simulation time	28788862 ps
CPU time	0.97 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:35 PM PDT 24
Peak memory	209720 kb
Host	smart-bdad34bd-6777-4ad5-9d70-751783d694e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532279336 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3532279336
Directory	/workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2723924709
Short name	T968
Test name
Test status
Simulation time	22355228 ps
CPU time	1.43 seconds
Started	Apr 28 02:54:40 PM PDT 24
Finished	Apr 28 02:54:43 PM PDT 24
Peak memory	217836 kb
Host	smart-b3632d52-e901-4038-be32-f6545f9a1da4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723924709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _same_csr_outstanding.2723924709
Directory	/workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4108071456
Short name	T117
Test name
Test status
Simulation time	297556563 ps
CPU time	2.65 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:37 PM PDT 24
Peak memory	218520 kb
Host	smart-a4991cd5-13eb-4410-911d-422f37899bd9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108071456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4108071456
Directory	/workspace/3.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1585497734
Short name	T137
Test name
Test status
Simulation time	209333306 ps
CPU time	2.49 seconds
Started	Apr 28 02:54:33 PM PDT 24
Finished	Apr 28 02:54:37 PM PDT 24
Peak memory	217780 kb
Host	smart-527c47fa-a0d7-4130-b4ab-32cc9419945f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585497734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_ err.1585497734
Directory	/workspace/3.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2377765681
Short name	T201
Test name
Test status
Simulation time	20920011 ps
CPU time	0.96 seconds
Started	Apr 28 02:54:46 PM PDT 24
Finished	Apr 28 02:54:47 PM PDT 24
Peak memory	209612 kb
Host	smart-ead54a52-7030-466a-9c30-70d4de72fb4c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377765681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin g.2377765681
Directory	/workspace/4.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1882320875
Short name	T207
Test name
Test status
Simulation time	91838216 ps
CPU time	3.18 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:49 PM PDT 24
Peak memory	209628 kb
Host	smart-fa6d9408-5a7d-4aac-89b7-3cc0ca787683
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882320875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas h.1882320875
Directory	/workspace/4.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3598613025
Short name	T884
Test name
Test status
Simulation time	12930242 ps
CPU time	0.9 seconds
Started	Apr 28 02:54:46 PM PDT 24
Finished	Apr 28 02:54:47 PM PDT 24
Peak memory	210068 kb
Host	smart-67d14e73-4e78-4acf-bcf6-df4b3447d3e4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598613025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese t.3598613025
Directory	/workspace/4.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1180109957
Short name	T951
Test name
Test status
Simulation time	121543184 ps
CPU time	1.08 seconds
Started	Apr 28 02:54:44 PM PDT 24
Finished	Apr 28 02:54:45 PM PDT 24
Peak memory	219076 kb
Host	smart-9512b051-5ead-402f-bb54-39a6711a3d8a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180109957 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1180109957
Directory	/workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3863820043
Short name	T203
Test name
Test status
Simulation time	22332742 ps
CPU time	1 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:47 PM PDT 24
Peak memory	209624 kb
Host	smart-d2709295-470d-46ce-9eda-9b0779a788d5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863820043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3863820043
Directory	/workspace/4.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.497636166
Short name	T921
Test name
Test status
Simulation time	90753874 ps
CPU time	1.5 seconds
Started	Apr 28 02:54:46 PM PDT 24
Finished	Apr 28 02:54:48 PM PDT 24
Peak memory	209360 kb
Host	smart-77290b45-cd29-47f0-9345-50777a1f9ac7
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497636166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.lc_ctrl_jtag_alert_test.497636166
Directory	/workspace/4.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.638105472
Short name	T973
Test name
Test status
Simulation time	428778631 ps
CPU time	10.81 seconds
Started	Apr 28 02:54:46 PM PDT 24
Finished	Apr 28 02:54:58 PM PDT 24
Peak memory	208700 kb
Host	smart-c4322084-d2bb-414a-b463-737a98d7f0b5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638105472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_aliasing.638105472
Directory	/workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3602572371
Short name	T919
Test name
Test status
Simulation time	1604972495 ps
CPU time	13.09 seconds
Started	Apr 28 02:54:46 PM PDT 24
Finished	Apr 28 02:54:59 PM PDT 24
Peak memory	209424 kb
Host	smart-d6f265ad-57c9-4bb8-88b6-8fec7828b38f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602572371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3602572371
Directory	/workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.214315352
Short name	T893
Test name
Test status
Simulation time	91061400 ps
CPU time	1.79 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:48 PM PDT 24
Peak memory	210860 kb
Host	smart-21ab9ad1-f0f3-4d58-b304-1b6b5326f262
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214315352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.214315352
Directory	/workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2655072136
Short name	T897
Test name
Test status
Simulation time	153168990 ps
CPU time	1.15 seconds
Started	Apr 28 02:54:44 PM PDT 24
Finished	Apr 28 02:54:46 PM PDT 24
Peak memory	209540 kb
Host	smart-763a0f83-c152-4329-b669-d71e6982e674
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655072136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.2655072136
Directory	/workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4134238282
Short name	T213
Test name
Test status
Simulation time	79428282 ps
CPU time	1.08 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:47 PM PDT 24
Peak memory	209100 kb
Host	smart-5debc5fd-d615-4576-94af-32f137762ceb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134238282 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4134238282
Directory	/workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2441437352
Short name	T981
Test name
Test status
Simulation time	17624311 ps
CPU time	1 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:46 PM PDT 24
Peak memory	209584 kb
Host	smart-e06c2cdf-aa79-4400-8f0f-77bee9ed2d6b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441437352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _same_csr_outstanding.2441437352
Directory	/workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2332723953
Short name	T982
Test name
Test status
Simulation time	109949289 ps
CPU time	4.34 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:50 PM PDT 24
Peak memory	217920 kb
Host	smart-46158cdb-c9e4-4d60-8515-8fdf506db863
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332723953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2332723953
Directory	/workspace/4.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1520152977
Short name	T138
Test name
Test status
Simulation time	63860852 ps
CPU time	2.08 seconds
Started	Apr 28 02:54:44 PM PDT 24
Finished	Apr 28 02:54:47 PM PDT 24
Peak memory	222316 kb
Host	smart-4860304a-8bb6-4838-baf7-f8b00719e5e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520152977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_ err.1520152977
Directory	/workspace/4.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3299291434
Short name	T958
Test name
Test status
Simulation time	103251460 ps
CPU time	1.16 seconds
Started	Apr 28 02:54:58 PM PDT 24
Finished	Apr 28 02:55:00 PM PDT 24
Peak memory	218888 kb
Host	smart-1df91da4-afd9-4c7f-9beb-82a06ec29a77
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299291434 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3299291434
Directory	/workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3398406519
Short name	T883
Test name
Test status
Simulation time	14626852 ps
CPU time	1 seconds
Started	Apr 28 02:54:51 PM PDT 24
Finished	Apr 28 02:54:53 PM PDT 24
Peak memory	209000 kb
Host	smart-de6d4d72-b7ae-4a98-b81a-65386de58cc5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398406519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3398406519
Directory	/workspace/5.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1991894415
Short name	T144
Test name
Test status
Simulation time	107147278 ps
CPU time	0.96 seconds
Started	Apr 28 02:54:51 PM PDT 24
Finished	Apr 28 02:54:53 PM PDT 24
Peak memory	208112 kb
Host	smart-73274433-43ae-4652-ac55-215afd351014
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991894415 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1991894415
Directory	/workspace/5.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1761357089
Short name	T940
Test name
Test status
Simulation time	17836323397 ps
CPU time	20.08 seconds
Started	Apr 28 02:54:53 PM PDT 24
Finished	Apr 28 02:55:13 PM PDT 24
Peak memory	209596 kb
Host	smart-64c9648d-25aa-4101-bbd8-dade87db3eb5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761357089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1761357089
Directory	/workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.843336952
Short name	T959
Test name
Test status
Simulation time	678242413 ps
CPU time	8.62 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:54 PM PDT 24
Peak memory	208264 kb
Host	smart-ceda42a5-81fb-4bb9-a7f7-0e27b833dd42
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843336952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.843336952
Directory	/workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3550022339
Short name	T946
Test name
Test status
Simulation time	258914713 ps
CPU time	2.14 seconds
Started	Apr 28 02:54:45 PM PDT 24
Finished	Apr 28 02:54:48 PM PDT 24
Peak memory	210948 kb
Host	smart-98f9e23f-3933-4bf7-9674-435919ec16ad
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550022339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3550022339
Directory	/workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3618257895
Short name	T143
Test name
Test status
Simulation time	439617038 ps
CPU time	2.8 seconds
Started	Apr 28 02:54:50 PM PDT 24
Finished	Apr 28 02:54:53 PM PDT 24
Peak memory	218660 kb
Host	smart-b76f8c85-2eef-4fe4-8ffb-355a9cc6a008
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361825 7895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3618257895
Directory	/workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2614468712
Short name	T963
Test name
Test status
Simulation time	162933041 ps
CPU time	1.08 seconds
Started	Apr 28 02:54:43 PM PDT 24
Finished	Apr 28 02:54:45 PM PDT 24
Peak memory	208500 kb
Host	smart-f7a1dd40-0777-40a8-a85a-a073ece3e282
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614468712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.2614468712
Directory	/workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2539310062
Short name	T922
Test name
Test status
Simulation time	14666253 ps
CPU time	1 seconds
Started	Apr 28 02:54:50 PM PDT 24
Finished	Apr 28 02:54:52 PM PDT 24
Peak memory	209492 kb
Host	smart-f97fb696-94b0-4561-9f33-e529b2e65c25
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539310062 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2539310062
Directory	/workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2882371859
Short name	T212
Test name
Test status
Simulation time	88039231 ps
CPU time	1.04 seconds
Started	Apr 28 02:54:51 PM PDT 24
Finished	Apr 28 02:54:53 PM PDT 24
Peak memory	209588 kb
Host	smart-ef84506b-607d-4ae2-aeac-2a7e7c0a7f0d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882371859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _same_csr_outstanding.2882371859
Directory	/workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3619036413
Short name	T906
Test name
Test status
Simulation time	85687398 ps
CPU time	1.12 seconds
Started	Apr 28 02:54:56 PM PDT 24
Finished	Apr 28 02:54:58 PM PDT 24
Peak memory	217832 kb
Host	smart-a67acf66-6fb9-4259-a13a-e4f46ada1a45
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619036413 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3619036413
Directory	/workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3097261910
Short name	T944
Test name
Test status
Simulation time	57577026 ps
CPU time	0.87 seconds
Started	Apr 28 02:54:55 PM PDT 24
Finished	Apr 28 02:54:56 PM PDT 24
Peak memory	209624 kb
Host	smart-75c14e18-a04f-4d52-8888-bd8261961501
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097261910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3097261910
Directory	/workspace/6.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.725641947
Short name	T888
Test name
Test status
Simulation time	63932975 ps
CPU time	1.46 seconds
Started	Apr 28 02:55:05 PM PDT 24
Finished	Apr 28 02:55:07 PM PDT 24
Peak memory	208148 kb
Host	smart-6e21cd4e-9694-47a1-8c43-abea73f874d4
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725641947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.lc_ctrl_jtag_alert_test.725641947
Directory	/workspace/6.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.175756759
Short name	T905
Test name
Test status
Simulation time	683119521 ps
CPU time	4.03 seconds
Started	Apr 28 02:54:56 PM PDT 24
Finished	Apr 28 02:55:00 PM PDT 24
Peak memory	209272 kb
Host	smart-308ccc4d-56bf-4b67-ad97-87352aa159c5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175756759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.lc_ctrl_jtag_csr_aliasing.175756759
Directory	/workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2325793219
Short name	T970
Test name
Test status
Simulation time	1605174010 ps
CPU time	36.02 seconds
Started	Apr 28 02:55:05 PM PDT 24
Finished	Apr 28 02:55:41 PM PDT 24
Peak memory	209344 kb
Host	smart-ae22e329-60cd-433a-bda3-0df69854b9f8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325793219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2325793219
Directory	/workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2551674934
Short name	T140
Test name
Test status
Simulation time	195674619 ps
CPU time	1.32 seconds
Started	Apr 28 02:54:57 PM PDT 24
Finished	Apr 28 02:54:59 PM PDT 24
Peak memory	210576 kb
Host	smart-ff53b88d-19c8-42ae-9f43-d693595ee33e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551674934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2551674934
Directory	/workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2882757417
Short name	T1004
Test name
Test status
Simulation time	1244710164 ps
CPU time	1.85 seconds
Started	Apr 28 02:54:55 PM PDT 24
Finished	Apr 28 02:54:58 PM PDT 24
Peak memory	222380 kb
Host	smart-902a9250-b0b7-4ed0-a59a-50805f76056d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288275 7417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2882757417
Directory	/workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.306732771
Short name	T895
Test name
Test status
Simulation time	149530909 ps
CPU time	2.22 seconds
Started	Apr 28 02:54:57 PM PDT 24
Finished	Apr 28 02:54:59 PM PDT 24
Peak memory	209536 kb
Host	smart-ec78cfdc-58fe-4521-98fc-e1658e975568
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306732771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.306732771
Directory	/workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1577642693
Short name	T960
Test name
Test status
Simulation time	165915655 ps
CPU time	1.3 seconds
Started	Apr 28 02:55:06 PM PDT 24
Finished	Apr 28 02:55:08 PM PDT 24
Peak memory	209568 kb
Host	smart-4a91b0b9-b571-48ef-82ad-09e5d16a874d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577642693 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1577642693
Directory	/workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.346365606
Short name	T214
Test name
Test status
Simulation time	18053108 ps
CPU time	1.02 seconds
Started	Apr 28 02:54:55 PM PDT 24
Finished	Apr 28 02:54:56 PM PDT 24
Peak memory	209580 kb
Host	smart-f41e3563-c546-4861-b9a2-08878e04afc7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346365606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ same_csr_outstanding.346365606
Directory	/workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2103806012
Short name	T130
Test name
Test status
Simulation time	545433153 ps
CPU time	3.62 seconds
Started	Apr 28 02:54:57 PM PDT 24
Finished	Apr 28 02:55:01 PM PDT 24
Peak memory	217904 kb
Host	smart-c86c70f7-afec-4883-8b54-01a8e263d770
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103806012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2103806012
Directory	/workspace/6.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2819329973
Short name	T112
Test name
Test status
Simulation time	43851087 ps
CPU time	2.11 seconds
Started	Apr 28 02:54:58 PM PDT 24
Finished	Apr 28 02:55:01 PM PDT 24
Peak memory	222152 kb
Host	smart-c1697bb5-6fef-49eb-92e2-90bf030ddf53
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819329973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_ err.2819329973
Directory	/workspace/6.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3471634823
Short name	T928
Test name
Test status
Simulation time	24876814 ps
CPU time	1.67 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:04 PM PDT 24
Peak memory	220100 kb
Host	smart-1c044508-9256-4ab0-bbf9-275ec5278805
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471634823 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3471634823
Directory	/workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.908142538
Short name	T155
Test name
Test status
Simulation time	14981701 ps
CPU time	1 seconds
Started	Apr 28 02:55:02 PM PDT 24
Finished	Apr 28 02:55:04 PM PDT 24
Peak memory	209472 kb
Host	smart-1640eaa3-decc-4d01-b9bf-2881b9ccfd48
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908142538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.908142538
Directory	/workspace/7.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3401613718
Short name	T966
Test name
Test status
Simulation time	213269614 ps
CPU time	1.9 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:04 PM PDT 24
Peak memory	209476 kb
Host	smart-43628127-bcaa-480a-a4df-74de165adab1
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401613718 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3401613718
Directory	/workspace/7.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1935934829
Short name	T141
Test name
Test status
Simulation time	4433321950 ps
CPU time	23.16 seconds
Started	Apr 28 02:55:05 PM PDT 24
Finished	Apr 28 02:55:29 PM PDT 24
Peak memory	209568 kb
Host	smart-31bafb3a-32c0-4f27-8ce5-dee1cbc3aa66
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935934829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1935934829
Directory	/workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1122449022
Short name	T989
Test name
Test status
Simulation time	1963688509 ps
CPU time	5.57 seconds
Started	Apr 28 02:54:57 PM PDT 24
Finished	Apr 28 02:55:03 PM PDT 24
Peak memory	209172 kb
Host	smart-a2319a1f-98a4-46c4-9213-a1c6d8d64efb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122449022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1122449022
Directory	/workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2835980842
Short name	T902
Test name
Test status
Simulation time	594513267 ps
CPU time	3.88 seconds
Started	Apr 28 02:54:58 PM PDT 24
Finished	Apr 28 02:55:03 PM PDT 24
Peak memory	211272 kb
Host	smart-6abf4f64-8542-440a-b504-b64bcc115bbf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835980842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2835980842
Directory	/workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.635469434
Short name	T983
Test name
Test status
Simulation time	102906638 ps
CPU time	3.48 seconds
Started	Apr 28 02:55:08 PM PDT 24
Finished	Apr 28 02:55:12 PM PDT 24
Peak memory	223328 kb
Host	smart-2313829d-eb5e-424b-b8c2-af2a14512140
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635469 434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.635469434
Directory	/workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.930370455
Short name	T967
Test name
Test status
Simulation time	124210416 ps
CPU time	1.9 seconds
Started	Apr 28 02:55:05 PM PDT 24
Finished	Apr 28 02:55:08 PM PDT 24
Peak memory	209504 kb
Host	smart-8992b7e5-7fd1-4ccb-b9e9-2f0b4a118cb1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930370455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.930370455
Directory	/workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4151168266
Short name	T997
Test name
Test status
Simulation time	54663323 ps
CPU time	1.77 seconds
Started	Apr 28 02:55:02 PM PDT 24
Finished	Apr 28 02:55:04 PM PDT 24
Peak memory	209592 kb
Host	smart-3bf0f2b5-2cb5-4c32-92bf-262b885e7a1b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151168266 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4151168266
Directory	/workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1457198370
Short name	T211
Test name
Test status
Simulation time	92562089 ps
CPU time	1.42 seconds
Started	Apr 28 02:55:00 PM PDT 24
Finished	Apr 28 02:55:03 PM PDT 24
Peak memory	209636 kb
Host	smart-a0029159-1ef5-436a-9953-2910186d5c2d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457198370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _same_csr_outstanding.1457198370
Directory	/workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2106731418
Short name	T941
Test name
Test status
Simulation time	99685815 ps
CPU time	3 seconds
Started	Apr 28 02:55:03 PM PDT 24
Finished	Apr 28 02:55:07 PM PDT 24
Peak memory	217896 kb
Host	smart-46f3085f-feea-4bd6-bcf7-927e205bc009
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106731418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2106731418
Directory	/workspace/7.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1853168934
Short name	T126
Test name
Test status
Simulation time	48880498 ps
CPU time	1.91 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:04 PM PDT 24
Peak memory	221776 kb
Host	smart-4e425f0b-0b73-4ddc-93bb-cc3a0c1c31d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853168934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_ err.1853168934
Directory	/workspace/7.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3163998643
Short name	T898
Test name
Test status
Simulation time	68176723 ps
CPU time	1.02 seconds
Started	Apr 28 02:55:08 PM PDT 24
Finished	Apr 28 02:55:09 PM PDT 24
Peak memory	217812 kb
Host	smart-46dfa534-e150-4cf8-9cc6-4c88148179d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163998643 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3163998643
Directory	/workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1908424529
Short name	T932
Test name
Test status
Simulation time	23713134 ps
CPU time	0.85 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:03 PM PDT 24
Peak memory	209552 kb
Host	smart-ab8e3185-fef9-45cc-a253-9e848c686f11
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908424529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1908424529
Directory	/workspace/8.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2083615756
Short name	T887
Test name
Test status
Simulation time	63670967 ps
CPU time	2.14 seconds
Started	Apr 28 02:55:02 PM PDT 24
Finished	Apr 28 02:55:05 PM PDT 24
Peak memory	208184 kb
Host	smart-4643fffb-f383-4192-93ec-d6e47ada7efd
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083615756 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2083615756
Directory	/workspace/8.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1747874564
Short name	T938
Test name
Test status
Simulation time	1282015689 ps
CPU time	10.36 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:12 PM PDT 24
Peak memory	209436 kb
Host	smart-8c915c86-1311-446a-9d5b-c7c5d04edb7c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747874564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1747874564
Directory	/workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1446904006
Short name	T1000
Test name
Test status
Simulation time	674520934 ps
CPU time	16.63 seconds
Started	Apr 28 02:55:00 PM PDT 24
Finished	Apr 28 02:55:18 PM PDT 24
Peak memory	208336 kb
Host	smart-41d008d5-8a28-4073-9d8f-c0a5a42fe9a3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446904006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1446904006
Directory	/workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.686661769
Short name	T961
Test name
Test status
Simulation time	243293888 ps
CPU time	2.17 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:04 PM PDT 24
Peak memory	210652 kb
Host	smart-c236218a-2007-4b8a-82d5-a9ebd2f8ef48
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686661769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.686661769
Directory	/workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1221364804
Short name	T142
Test name
Test status
Simulation time	400235644 ps
CPU time	3.2 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:05 PM PDT 24
Peak memory	217880 kb
Host	smart-72a25120-7854-4e3d-aa5c-c8216ef8b93b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122136 4804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1221364804
Directory	/workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3327293846
Short name	T909
Test name
Test status
Simulation time	1765582423 ps
CPU time	3.44 seconds
Started	Apr 28 02:55:01 PM PDT 24
Finished	Apr 28 02:55:06 PM PDT 24
Peak memory	209512 kb
Host	smart-9e635169-9bd0-4164-b400-4dbe88f09e4f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327293846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.3327293846
Directory	/workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2748323594
Short name	T935
Test name
Test status
Simulation time	19053967 ps
CPU time	1.01 seconds
Started	Apr 28 02:55:00 PM PDT 24
Finished	Apr 28 02:55:02 PM PDT 24
Peak memory	209688 kb
Host	smart-c37ea730-1e01-4883-bf96-a2a614b65608
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748323594 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2748323594
Directory	/workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4018086589
Short name	T942
Test name
Test status
Simulation time	54994735 ps
CPU time	1.78 seconds
Started	Apr 28 02:55:11 PM PDT 24
Finished	Apr 28 02:55:13 PM PDT 24
Peak memory	209296 kb
Host	smart-7c1136b5-34cf-4471-8545-a4452de516cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018086589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _same_csr_outstanding.4018086589
Directory	/workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1173018528
Short name	T994
Test name
Test status
Simulation time	139639114 ps
CPU time	2.43 seconds
Started	Apr 28 02:55:03 PM PDT 24
Finished	Apr 28 02:55:06 PM PDT 24
Peak memory	217932 kb
Host	smart-1a13902b-2f5f-4887-ad28-79a04ef76780
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173018528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1173018528
Directory	/workspace/8.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2754280278
Short name	T929
Test name
Test status
Simulation time	47146428 ps
CPU time	1.23 seconds
Started	Apr 28 02:55:09 PM PDT 24
Finished	Apr 28 02:55:11 PM PDT 24
Peak memory	217832 kb
Host	smart-f53b40ef-b488-4471-883f-d7c413350bf7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754280278 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2754280278
Directory	/workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1488498699
Short name	T933
Test name
Test status
Simulation time	174255427 ps
CPU time	0.89 seconds
Started	Apr 28 02:55:10 PM PDT 24
Finished	Apr 28 02:55:11 PM PDT 24
Peak memory	209320 kb
Host	smart-02ee26e0-051f-47a2-b6d2-4f8c96bfe02d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488498699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1488498699
Directory	/workspace/9.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.211185059
Short name	T886
Test name
Test status
Simulation time	51105973 ps
CPU time	1.09 seconds
Started	Apr 28 02:55:07 PM PDT 24
Finished	Apr 28 02:55:09 PM PDT 24
Peak memory	209508 kb
Host	smart-61add3a4-66d1-4724-9fa2-357f8f034320
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211185059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.lc_ctrl_jtag_alert_test.211185059
Directory	/workspace/9.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2645012719
Short name	T926
Test name
Test status
Simulation time	1197899678 ps
CPU time	9.61 seconds
Started	Apr 28 02:55:08 PM PDT 24
Finished	Apr 28 02:55:19 PM PDT 24
Peak memory	208792 kb
Host	smart-9b7aa05b-bf5e-4ac6-a86f-c34eb55ff2b8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645012719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2645012719
Directory	/workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3959817247
Short name	T145
Test name
Test status
Simulation time	751529116 ps
CPU time	5.21 seconds
Started	Apr 28 02:55:08 PM PDT 24
Finished	Apr 28 02:55:14 PM PDT 24
Peak memory	209520 kb
Host	smart-293deac6-4bda-4778-9dde-0350f20aac82
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959817247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3959817247
Directory	/workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1761679455
Short name	T984
Test name
Test status
Simulation time	432388571 ps
CPU time	2.46 seconds
Started	Apr 28 02:55:09 PM PDT 24
Finished	Apr 28 02:55:12 PM PDT 24
Peak memory	209492 kb
Host	smart-2b377270-861c-4acd-aa9c-efac2bfc7cc3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761679455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1761679455
Directory	/workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4117993842
Short name	T977
Test name
Test status
Simulation time	684505680 ps
CPU time	4.59 seconds
Started	Apr 28 02:55:11 PM PDT 24
Finished	Apr 28 02:55:16 PM PDT 24
Peak memory	217832 kb
Host	smart-4886acae-f01b-4585-9597-37545c4d5def
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411799 3842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4117993842
Directory	/workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2444629454
Short name	T918
Test name
Test status
Simulation time	232031451 ps
CPU time	1.35 seconds
Started	Apr 28 02:55:09 PM PDT 24
Finished	Apr 28 02:55:11 PM PDT 24
Peak memory	209500 kb
Host	smart-3b8ab83d-a78f-4d87-bfee-bd8434dbaf37
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444629454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.2444629454
Directory	/workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1724030377
Short name	T934
Test name
Test status
Simulation time	38699973 ps
CPU time	1.22 seconds
Started	Apr 28 02:55:06 PM PDT 24
Finished	Apr 28 02:55:08 PM PDT 24
Peak memory	209556 kb
Host	smart-f0987c6a-8e92-4b5d-9666-b1a60956f3bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724030377 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1724030377
Directory	/workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3063082078
Short name	T985
Test name
Test status
Simulation time	16012481 ps
CPU time	1.18 seconds
Started	Apr 28 02:55:07 PM PDT 24
Finished	Apr 28 02:55:09 PM PDT 24
Peak memory	209080 kb
Host	smart-a603d0ba-eac2-4a9c-ab94-fa07af286830
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063082078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _same_csr_outstanding.3063082078
Directory	/workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4181828997
Short name	T129
Test name
Test status
Simulation time	50277719 ps
CPU time	1.47 seconds
Started	Apr 28 02:55:10 PM PDT 24
Finished	Apr 28 02:55:11 PM PDT 24
Peak memory	217896 kb
Host	smart-327ff50f-a2ab-4f22-9b58-f86cd100c9ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181828997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4181828997
Directory	/workspace/9.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.273133508
Short name	T139
Test name
Test status
Simulation time	121170634 ps
CPU time	4.12 seconds
Started	Apr 28 02:55:07 PM PDT 24
Finished	Apr 28 02:55:12 PM PDT 24
Peak memory	217808 kb
Host	smart-0eeee122-72d4-4da8-ab48-581b2a13993a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273133508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e rr.273133508
Directory	/workspace/9.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.lc_ctrl_alert_test.2855182221
Short name	T632
Test name
Test status
Simulation time	21413778 ps
CPU time	0.95 seconds
Started	Apr 28 12:52:01 PM PDT 24
Finished	Apr 28 12:52:02 PM PDT 24
Peak memory	209336 kb
Host	smart-f2a0b047-71ef-44da-a70f-a6e29843e24c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855182221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2855182221
Directory	/workspace/0.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.lc_ctrl_claim_transition_if.2791936926
Short name	T785
Test name
Test status
Simulation time	52943161 ps
CPU time	0.91 seconds
Started	Apr 28 12:51:56 PM PDT 24
Finished	Apr 28 12:51:58 PM PDT 24
Peak memory	209308 kb
Host	smart-79471405-a670-4068-98f0-bdb6bd2b0132
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791936926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2791936926
Directory	/workspace/0.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/0.lc_ctrl_errors.378188757
Short name	T329
Test name
Test status
Simulation time	526512430 ps
CPU time	8.46 seconds
Started	Apr 28 12:51:55 PM PDT 24
Finished	Apr 28 12:52:04 PM PDT 24
Peak memory	225896 kb
Host	smart-80615be8-691c-4900-8231-3db7a216c8ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378188757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.378188757
Directory	/workspace/0.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_access.1762952056
Short name	T9
Test name
Test status
Simulation time	2267997084 ps
CPU time	13.47 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:52:08 PM PDT 24
Peak memory	209372 kb
Host	smart-1351edd1-34e7-4c27-81e7-49f9e089e3f9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762952056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1762952056
Directory	/workspace/0.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_errors.2987202880
Short name	T638
Test name
Test status
Simulation time	975840969 ps
CPU time	30.87 seconds
Started	Apr 28 12:51:55 PM PDT 24
Finished	Apr 28 12:52:27 PM PDT 24
Peak memory	217788 kb
Host	smart-dfe9f6ff-f33c-48a9-bf1a-3c9eb384633e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987202880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er rors.2987202880
Directory	/workspace/0.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_priority.632188498
Short name	T333
Test name
Test status
Simulation time	736166133 ps
CPU time	7.01 seconds
Started	Apr 28 12:52:03 PM PDT 24
Finished	Apr 28 12:52:11 PM PDT 24
Peak memory	217608 kb
Host	smart-eeec1f70-3b1c-48ed-8f92-7c2ff6333d30
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632188498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.632188498
Directory	/workspace/0.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.877971661
Short name	T471
Test name
Test status
Simulation time	602591450 ps
CPU time	9.74 seconds
Started	Apr 28 12:51:55 PM PDT 24
Finished	Apr 28 12:52:06 PM PDT 24
Peak memory	217652 kb
Host	smart-1942fd87-529a-4a9c-b9ba-5c3d91949e56
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877971661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ prog_failure.877971661
Directory	/workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.829168143
Short name	T388
Test name
Test status
Simulation time	1054341526 ps
CPU time	30.15 seconds
Started	Apr 28 12:52:00 PM PDT 24
Finished	Apr 28 12:52:31 PM PDT 24
Peak memory	213148 kb
Host	smart-bc560e5c-c9f9-41d6-9df9-61ea1da004f4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829168143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j tag_regwen_during_op.829168143
Directory	/workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_smoke.588497831
Short name	T657
Test name
Test status
Simulation time	435077598 ps
CPU time	8.07 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:52:03 PM PDT 24
Peak memory	212992 kb
Host	smart-31e377cc-8ab3-4b29-8a66-f0f577357fb5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588497831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.588497831
Directory	/workspace/0.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1748346230
Short name	T108
Test name
Test status
Simulation time	1481556145 ps
CPU time	41.6 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:52:37 PM PDT 24
Peak memory	248996 kb
Host	smart-84053401-4d17-4221-bb7d-3f935c939401
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748346230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta g_state_failure.1748346230
Directory	/workspace/0.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3909752956
Short name	T651
Test name
Test status
Simulation time	4830954992 ps
CPU time	13.3 seconds
Started	Apr 28 12:51:59 PM PDT 24
Finished	Apr 28 12:52:13 PM PDT 24
Peak memory	250932 kb
Host	smart-ff10ec5e-9232-4225-aeae-3b4511a4bb25
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909752956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_state_post_trans.3909752956
Directory	/workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_prog_failure.2921678936
Short name	T275
Test name
Test status
Simulation time	113158209 ps
CPU time	3.68 seconds
Started	Apr 28 12:51:53 PM PDT 24
Finished	Apr 28 12:51:57 PM PDT 24
Peak memory	217832 kb
Host	smart-2111b233-53ec-4510-9b1d-7736b553497d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921678936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2921678936
Directory	/workspace/0.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_regwen_during_op.502703311
Short name	T218
Test name
Test status
Simulation time	1437116787 ps
CPU time	24.46 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:52:19 PM PDT 24
Peak memory	214428 kb
Host	smart-6868d7f2-2bab-4318-9768-4fd9443d9cdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502703311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.502703311
Directory	/workspace/0.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_cm.3175507010
Short name	T1
Test name
Test status
Simulation time	231426282 ps
CPU time	23.68 seconds
Started	Apr 28 12:52:01 PM PDT 24
Finished	Apr 28 12:52:25 PM PDT 24
Peak memory	284388 kb
Host	smart-20b707a5-63ca-445e-be00-fd23ed1a55c8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175507010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3175507010
Directory	/workspace/0.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_mubi.196878067
Short name	T172
Test name
Test status
Simulation time	231387468 ps
CPU time	11.22 seconds
Started	Apr 28 12:52:04 PM PDT 24
Finished	Apr 28 12:52:16 PM PDT 24
Peak memory	219032 kb
Host	smart-b2ccd5f3-7c96-40b9-9db4-24632a42f0fc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196878067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.196878067
Directory	/workspace/0.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_digest.386783031
Short name	T248
Test name
Test status
Simulation time	1233439952 ps
CPU time	11.8 seconds
Started	Apr 28 12:52:05 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	217808 kb
Host	smart-e626959e-a25d-4301-97f1-711784a55954
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386783031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig est.386783031
Directory	/workspace/0.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_mux.4204967581
Short name	T655
Test name
Test status
Simulation time	542270367 ps
CPU time	6.62 seconds
Started	Apr 28 12:52:01 PM PDT 24
Finished	Apr 28 12:52:09 PM PDT 24
Peak memory	217800 kb
Host	smart-8a482292-1a11-4836-9d5a-40015ed4f45b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204967581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.4 204967581
Directory	/workspace/0.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/0.lc_ctrl_security_escalation.1887013588
Short name	T613
Test name
Test status
Simulation time	1507389801 ps
CPU time	15.07 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:52:11 PM PDT 24
Peak memory	225928 kb
Host	smart-1cc320d5-5216-4cd9-a896-e9fb18025597
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887013588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1887013588
Directory	/workspace/0.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_smoke.854329912
Short name	T509
Test name
Test status
Simulation time	158792681 ps
CPU time	3.01 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:51:58 PM PDT 24
Peak memory	214464 kb
Host	smart-007922c6-b20b-4d0d-90f7-4ae2bb1bb26e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854329912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.854329912
Directory	/workspace/0.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_failure.4273568538
Short name	T543
Test name
Test status
Simulation time	305024048 ps
CPU time	21.86 seconds
Started	Apr 28 12:51:51 PM PDT 24
Finished	Apr 28 12:52:14 PM PDT 24
Peak memory	250780 kb
Host	smart-3ab17d54-b22c-4208-abe0-b53a4844a1cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273568538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.4273568538
Directory	/workspace/0.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_post_trans.1033781786
Short name	T258
Test name
Test status
Simulation time	290481466 ps
CPU time	8.05 seconds
Started	Apr 28 12:51:55 PM PDT 24
Finished	Apr 28 12:52:04 PM PDT 24
Peak memory	250728 kb
Host	smart-0777d386-e3fe-4842-ac60-090fdeb13f4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033781786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1033781786
Directory	/workspace/0.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_stress_all.2578452669
Short name	T160
Test name
Test status
Simulation time	9521252634 ps
CPU time	67.99 seconds
Started	Apr 28 12:51:59 PM PDT 24
Finished	Apr 28 12:53:08 PM PDT 24
Peak memory	249908 kb
Host	smart-42fa26b2-9ba8-4d02-892a-bc87aec4e61c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578452669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.2578452669
Directory	/workspace/0.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3436169731
Short name	T280
Test name
Test status
Simulation time	43284890 ps
CPU time	1 seconds
Started	Apr 28 12:51:56 PM PDT 24
Finished	Apr 28 12:51:58 PM PDT 24
Peak memory	212420 kb
Host	smart-928d9e26-b6b4-43aa-a8f8-36d82c5cab49
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436169731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct rl_volatile_unlock_smoke.3436169731
Directory	/workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_alert_test.30136175
Short name	T629
Test name
Test status
Simulation time	22043823 ps
CPU time	1.21 seconds
Started	Apr 28 12:51:59 PM PDT 24
Finished	Apr 28 12:52:01 PM PDT 24
Peak memory	209368 kb
Host	smart-c700ec2a-b13c-460b-a9e7-73bd42a379e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30136175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.30136175
Directory	/workspace/1.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.lc_ctrl_errors.2950236088
Short name	T704
Test name
Test status
Simulation time	5605077574 ps
CPU time	12.51 seconds
Started	Apr 28 12:52:02 PM PDT 24
Finished	Apr 28 12:52:15 PM PDT 24
Peak memory	218880 kb
Host	smart-10cfaad6-56ab-42bf-ac21-06a65fc927f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950236088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2950236088
Directory	/workspace/1.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_access.3124483006
Short name	T178
Test name
Test status
Simulation time	1240673700 ps
CPU time	12.71 seconds
Started	Apr 28 12:52:05 PM PDT 24
Finished	Apr 28 12:52:19 PM PDT 24
Peak memory	209532 kb
Host	smart-c500c838-9152-48ff-a2a0-49ccf0605f32
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124483006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3124483006
Directory	/workspace/1.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_errors.1003892443
Short name	T628
Test name
Test status
Simulation time	1566612227 ps
CPU time	27.02 seconds
Started	Apr 28 12:52:00 PM PDT 24
Finished	Apr 28 12:52:28 PM PDT 24
Peak memory	217876 kb
Host	smart-cdd0f080-38fb-4025-9157-d44e041a199f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003892443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er rors.1003892443
Directory	/workspace/1.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_priority.2138704563
Short name	T169
Test name
Test status
Simulation time	425478152 ps
CPU time	3.21 seconds
Started	Apr 28 12:52:02 PM PDT 24
Finished	Apr 28 12:52:06 PM PDT 24
Peak memory	217688 kb
Host	smart-e7d3d83f-1bd9-4b88-9d63-9b5e207bf096
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138704563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2 138704563
Directory	/workspace/1.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.529934501
Short name	T766
Test name
Test status
Simulation time	584001449 ps
CPU time	5.62 seconds
Started	Apr 28 12:51:59 PM PDT 24
Finished	Apr 28 12:52:05 PM PDT 24
Peak memory	217704 kb
Host	smart-537f48a7-632f-4bb8-80c6-c497832f0e9e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529934501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ prog_failure.529934501
Directory	/workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1744492311
Short name	T87
Test name
Test status
Simulation time	5889500583 ps
CPU time	14.45 seconds
Started	Apr 28 12:52:05 PM PDT 24
Finished	Apr 28 12:52:20 PM PDT 24
Peak memory	213768 kb
Host	smart-bc1e80dd-dbfc-47db-854b-d67ae94590d6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744492311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_regwen_during_op.1744492311
Directory	/workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_smoke.2718372149
Short name	T596
Test name
Test status
Simulation time	691107407 ps
CPU time	6.14 seconds
Started	Apr 28 12:52:03 PM PDT 24
Finished	Apr 28 12:52:10 PM PDT 24
Peak memory	213384 kb
Host	smart-cf7aa781-2ce5-400c-8416-2f0ddf8c49bf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718372149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke. 2718372149
Directory	/workspace/1.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2600445907
Short name	T424
Test name
Test status
Simulation time	4627031364 ps
CPU time	78.07 seconds
Started	Apr 28 12:52:04 PM PDT 24
Finished	Apr 28 12:53:22 PM PDT 24
Peak memory	268788 kb
Host	smart-4a83871f-d98f-47cb-87e8-796941a829ff
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600445907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_state_failure.2600445907
Directory	/workspace/1.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3807783646
Short name	T404
Test name
Test status
Simulation time	540724170 ps
CPU time	15.58 seconds
Started	Apr 28 12:51:59 PM PDT 24
Finished	Apr 28 12:52:15 PM PDT 24
Peak memory	250644 kb
Host	smart-0993fce6-869f-481d-ac2d-406cd2004e59
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807783646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_state_post_trans.3807783646
Directory	/workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_prog_failure.612911488
Short name	T735
Test name
Test status
Simulation time	217787352 ps
CPU time	3.05 seconds
Started	Apr 28 12:52:01 PM PDT 24
Finished	Apr 28 12:52:05 PM PDT 24
Peak memory	217768 kb
Host	smart-61cd7e2e-21bb-4f27-8ea8-55cb909e8366
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612911488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.612911488
Directory	/workspace/1.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_regwen_during_op.877544639
Short name	T442
Test name
Test status
Simulation time	843655751 ps
CPU time	8.75 seconds
Started	Apr 28 12:52:01 PM PDT 24
Finished	Apr 28 12:52:10 PM PDT 24
Peak memory	217856 kb
Host	smart-50408c5d-0683-499d-8978-fc78401f3354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877544639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.877544639
Directory	/workspace/1.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_cm.3018162679
Short name	T89
Test name
Test status
Simulation time	423698519 ps
CPU time	20.89 seconds
Started	Apr 28 12:51:59 PM PDT 24
Finished	Apr 28 12:52:20 PM PDT 24
Peak memory	268616 kb
Host	smart-885df11f-db14-4b26-a3d5-9952d63277f3
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018162679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3018162679
Directory	/workspace/1.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_mubi.2155074294
Short name	T272
Test name
Test status
Simulation time	1216493015 ps
CPU time	11.76 seconds
Started	Apr 28 12:52:08 PM PDT 24
Finished	Apr 28 12:52:20 PM PDT 24
Peak memory	217764 kb
Host	smart-dcfeb527-58cf-47da-996b-7260edcd5c00
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155074294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2155074294
Directory	/workspace/1.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_digest.17840041
Short name	T625
Test name
Test status
Simulation time	1732257451 ps
CPU time	13.98 seconds
Started	Apr 28 12:52:01 PM PDT 24
Finished	Apr 28 12:52:16 PM PDT 24
Peak memory	217848 kb
Host	smart-7f236d97-112b-46a4-9cef-b18ee3af27b1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17840041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dige st.17840041
Directory	/workspace/1.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_mux.3328606398
Short name	T263
Test name
Test status
Simulation time	689753080 ps
CPU time	7.89 seconds
Started	Apr 28 12:52:08 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	217808 kb
Host	smart-b0a9371b-3b9f-4937-8a47-337afda820a6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328606398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3 328606398
Directory	/workspace/1.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/1.lc_ctrl_security_escalation.4017255807
Short name	T566
Test name
Test status
Simulation time	1614513672 ps
CPU time	9.51 seconds
Started	Apr 28 12:52:00 PM PDT 24
Finished	Apr 28 12:52:11 PM PDT 24
Peak memory	217864 kb
Host	smart-0cd648c5-2a6b-417c-939d-41684a4f755d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017255807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4017255807
Directory	/workspace/1.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/1.lc_ctrl_smoke.208897865
Short name	T81
Test name
Test status
Simulation time	27626937 ps
CPU time	1.01 seconds
Started	Apr 28 12:52:00 PM PDT 24
Finished	Apr 28 12:52:02 PM PDT 24
Peak memory	211600 kb
Host	smart-807c34f5-fef6-43f1-9322-4cdecbf3543e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208897865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.208897865
Directory	/workspace/1.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_failure.1449163091
Short name	T581
Test name
Test status
Simulation time	241415728 ps
CPU time	26.4 seconds
Started	Apr 28 12:52:04 PM PDT 24
Finished	Apr 28 12:52:31 PM PDT 24
Peak memory	250864 kb
Host	smart-0b7c7c09-176f-4662-9037-fd7183aa6ea7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449163091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1449163091
Directory	/workspace/1.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_post_trans.1696641235
Short name	T532
Test name
Test status
Simulation time	57453115 ps
CPU time	8 seconds
Started	Apr 28 12:52:02 PM PDT 24
Finished	Apr 28 12:52:10 PM PDT 24
Peak memory	247164 kb
Host	smart-9910adb0-4ab6-48dd-8541-c86228b2a90a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696641235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1696641235
Directory	/workspace/1.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all.589529240
Short name	T779
Test name
Test status
Simulation time	1701365120 ps
CPU time	65.47 seconds
Started	Apr 28 12:52:01 PM PDT 24
Finished	Apr 28 12:53:08 PM PDT 24
Peak memory	250736 kb
Host	smart-01f8c140-d651-4ece-ba5c-86cb58cefe5d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589529240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.589529240
Directory	/workspace/1.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2158983022
Short name	T38
Test name
Test status
Simulation time	12305687 ps
CPU time	0.87 seconds
Started	Apr 28 12:52:01 PM PDT 24
Finished	Apr 28 12:52:02 PM PDT 24
Peak memory	208512 kb
Host	smart-b8e2877e-d024-4d1c-b713-f743ca5a01e5
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158983022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_volatile_unlock_smoke.2158983022
Directory	/workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_alert_test.2691967342
Short name	T488
Test name
Test status
Simulation time	48262723 ps
CPU time	1.29 seconds
Started	Apr 28 12:52:44 PM PDT 24
Finished	Apr 28 12:52:46 PM PDT 24
Peak memory	209364 kb
Host	smart-746eeed4-6294-4e60-8069-da964d0c0ca5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691967342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2691967342
Directory	/workspace/10.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.lc_ctrl_errors.13208262
Short name	T761
Test name
Test status
Simulation time	1720361649 ps
CPU time	15.12 seconds
Started	Apr 28 12:52:40 PM PDT 24
Finished	Apr 28 12:52:55 PM PDT 24
Peak memory	225908 kb
Host	smart-b1ed1cfd-581d-4ac5-898a-93c791d861d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13208262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.13208262
Directory	/workspace/10.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_access.1741781450
Short name	T537
Test name
Test status
Simulation time	674806042 ps
CPU time	5.92 seconds
Started	Apr 28 12:52:40 PM PDT 24
Finished	Apr 28 12:52:47 PM PDT 24
Peak memory	209404 kb
Host	smart-19c99a79-2c5a-4ad2-a05d-1231ce86eba0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741781450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1741781450
Directory	/workspace/10.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4216817745
Short name	T312
Test name
Test status
Simulation time	6177005988 ps
CPU time	11.75 seconds
Started	Apr 28 12:52:40 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	217864 kb
Host	smart-fe5258ee-2b3d-4664-a092-3c41b8eda99e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216817745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_prog_failure.4216817745
Directory	/workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_smoke.3139987857
Short name	T434
Test name
Test status
Simulation time	114223982 ps
CPU time	3.39 seconds
Started	Apr 28 12:52:39 PM PDT 24
Finished	Apr 28 12:52:43 PM PDT 24
Peak memory	212860 kb
Host	smart-23bbc774-0d75-4841-970a-e07af768e4fd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139987857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke .3139987857
Directory	/workspace/10.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3332609059
Short name	T734
Test name
Test status
Simulation time	16131061933 ps
CPU time	48.9 seconds
Started	Apr 28 12:52:39 PM PDT 24
Finished	Apr 28 12:53:29 PM PDT 24
Peak memory	273352 kb
Host	smart-35da88c7-39ea-43e8-bc11-4ceda985cfc4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332609059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt ag_state_failure.3332609059
Directory	/workspace/10.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2784205148
Short name	T270
Test name
Test status
Simulation time	4341619552 ps
CPU time	11.98 seconds
Started	Apr 28 12:52:39 PM PDT 24
Finished	Apr 28 12:52:51 PM PDT 24
Peak memory	250900 kb
Host	smart-ff237efb-fa38-4806-b922-57e40e5bfae4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784205148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl _jtag_state_post_trans.2784205148
Directory	/workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_prog_failure.2243487295
Short name	T516
Test name
Test status
Simulation time	187965003 ps
CPU time	4.63 seconds
Started	Apr 28 12:52:34 PM PDT 24
Finished	Apr 28 12:52:39 PM PDT 24
Peak memory	217868 kb
Host	smart-fdfa9440-5597-4d43-8c08-4e1b7c3d8642
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243487295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2243487295
Directory	/workspace/10.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_mubi.876175179
Short name	T721
Test name
Test status
Simulation time	391195551 ps
CPU time	13.72 seconds
Started	Apr 28 12:52:40 PM PDT 24
Finished	Apr 28 12:52:54 PM PDT 24
Peak memory	218496 kb
Host	smart-f9053a24-278e-457b-b0fe-30fbb56d392f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876175179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.876175179
Directory	/workspace/10.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_digest.1445587302
Short name	T554
Test name
Test status
Simulation time	1298817475 ps
CPU time	10.16 seconds
Started	Apr 28 12:52:41 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	217704 kb
Host	smart-ff40e43f-b990-4b2c-98df-b75e19c7e9a8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445587302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d igest.1445587302
Directory	/workspace/10.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_mux.721487230
Short name	T531
Test name
Test status
Simulation time	337152952 ps
CPU time	11.43 seconds
Started	Apr 28 12:52:39 PM PDT 24
Finished	Apr 28 12:52:51 PM PDT 24
Peak memory	217760 kb
Host	smart-4c3ff349-b95a-405f-882d-94b5b986239d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721487230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.721487230
Directory	/workspace/10.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/10.lc_ctrl_security_escalation.3654455707
Short name	T850
Test name
Test status
Simulation time	1285090078 ps
CPU time	12.03 seconds
Started	Apr 28 12:52:41 PM PDT 24
Finished	Apr 28 12:52:53 PM PDT 24
Peak memory	217868 kb
Host	smart-00853a8e-4ac4-48a5-9136-3dad51c314e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3654455707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3654455707
Directory	/workspace/10.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/10.lc_ctrl_smoke.1283552095
Short name	T382
Test name
Test status
Simulation time	291046423 ps
CPU time	2.89 seconds
Started	Apr 28 12:52:38 PM PDT 24
Finished	Apr 28 12:52:42 PM PDT 24
Peak memory	217728 kb
Host	smart-d07b2a83-f731-420e-b059-998ec5c606f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283552095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1283552095
Directory	/workspace/10.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_failure.4263287707
Short name	T539
Test name
Test status
Simulation time	818037372 ps
CPU time	22.92 seconds
Started	Apr 28 12:52:36 PM PDT 24
Finished	Apr 28 12:53:00 PM PDT 24
Peak memory	250736 kb
Host	smart-59b0f41a-b713-42c0-bc5d-c350945626a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263287707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4263287707
Directory	/workspace/10.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_post_trans.448621824
Short name	T777
Test name
Test status
Simulation time	151998670 ps
CPU time	3.34 seconds
Started	Apr 28 12:52:36 PM PDT 24
Finished	Apr 28 12:52:41 PM PDT 24
Peak memory	217696 kb
Host	smart-e640b841-cea4-4e5b-bc92-3d1a596d7de6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448621824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.448621824
Directory	/workspace/10.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all.1119012113
Short name	T176
Test name
Test status
Simulation time	9902531391 ps
CPU time	310.7 seconds
Started	Apr 28 12:52:40 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	283760 kb
Host	smart-307a62e3-aaa2-4ceb-be9e-98ece7f066d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119012113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.1119012113
Directory	/workspace/10.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3751406427
Short name	T367
Test name
Test status
Simulation time	46316866 ps
CPU time	0.9 seconds
Started	Apr 28 12:52:34 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	208612 kb
Host	smart-048f15d6-9c27-4323-8f79-276bac2e2a6c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751406427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_volatile_unlock_smoke.3751406427
Directory	/workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_alert_test.1841929610
Short name	T402
Test name
Test status
Simulation time	203488835 ps
CPU time	1.01 seconds
Started	Apr 28 12:52:43 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	209428 kb
Host	smart-e69b9fe6-c788-4154-88b5-92ca7bfe2115
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841929610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1841929610
Directory	/workspace/11.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.lc_ctrl_errors.3803063253
Short name	T252
Test name
Test status
Simulation time	3376696149 ps
CPU time	20.39 seconds
Started	Apr 28 12:52:44 PM PDT 24
Finished	Apr 28 12:53:04 PM PDT 24
Peak memory	217912 kb
Host	smart-97fbebe3-8599-4168-a937-37a78ec9db79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803063253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3803063253
Directory	/workspace/11.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_access.1638004839
Short name	T305
Test name
Test status
Simulation time	50616922 ps
CPU time	1.26 seconds
Started	Apr 28 12:52:44 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	209352 kb
Host	smart-4c9423a4-9ead-474a-a064-69aaf1a2f00f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638004839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1638004839
Directory	/workspace/11.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_errors.1261093066
Short name	T290
Test name
Test status
Simulation time	15201146216 ps
CPU time	38.21 seconds
Started	Apr 28 12:52:45 PM PDT 24
Finished	Apr 28 12:53:24 PM PDT 24
Peak memory	218300 kb
Host	smart-9592de5f-1a7a-4dc7-b86e-610e9227568e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261093066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e rrors.1261093066
Directory	/workspace/11.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3354293245
Short name	T318
Test name
Test status
Simulation time	52568407 ps
CPU time	2.5 seconds
Started	Apr 28 12:52:42 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	217828 kb
Host	smart-ba460097-93f0-4828-8622-aae914fe2bed
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354293245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta g_prog_failure.3354293245
Directory	/workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_smoke.211697097
Short name	T73
Test name
Test status
Simulation time	335895685 ps
CPU time	7.25 seconds
Started	Apr 28 12:52:44 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	213156 kb
Host	smart-6f60a6e1-2a4b-4f41-b86f-635b59cc1d6d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211697097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke. 211697097
Directory	/workspace/11.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1448675850
Short name	T715
Test name
Test status
Simulation time	11716821109 ps
CPU time	90.76 seconds
Started	Apr 28 12:52:43 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	283272 kb
Host	smart-e6c0239c-e72f-4b47-bdc9-d59c38525e73
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448675850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt ag_state_failure.1448675850
Directory	/workspace/11.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1847550562
Short name	T319
Test name
Test status
Simulation time	1791136051 ps
CPU time	16.24 seconds
Started	Apr 28 12:52:45 PM PDT 24
Finished	Apr 28 12:53:02 PM PDT 24
Peak memory	247068 kb
Host	smart-93cd0631-ad55-4d41-9c78-be948863467e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847550562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _jtag_state_post_trans.1847550562
Directory	/workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_prog_failure.1791304504
Short name	T691
Test name
Test status
Simulation time	22891956 ps
CPU time	1.95 seconds
Started	Apr 28 12:52:43 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	217724 kb
Host	smart-f5a08786-03bc-4931-a4fc-43cfff471654
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791304504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1791304504
Directory	/workspace/11.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_digest.4155346599
Short name	T642
Test name
Test status
Simulation time	378082743 ps
CPU time	14.97 seconds
Started	Apr 28 12:52:46 PM PDT 24
Finished	Apr 28 12:53:01 PM PDT 24
Peak memory	217916 kb
Host	smart-df463046-e0a0-41ca-8c2d-af61c84aeaa6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155346599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d igest.4155346599
Directory	/workspace/11.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_mux.3138685243
Short name	T368
Test name
Test status
Simulation time	905038835 ps
CPU time	8.04 seconds
Started	Apr 28 12:52:49 PM PDT 24
Finished	Apr 28 12:52:57 PM PDT 24
Peak memory	217804 kb
Host	smart-2ebe6d32-7c53-41a9-b99d-0bc00e00c7d7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138685243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux. 3138685243
Directory	/workspace/11.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/11.lc_ctrl_security_escalation.3881476248
Short name	T374
Test name
Test status
Simulation time	254617515 ps
CPU time	6.76 seconds
Started	Apr 28 12:52:47 PM PDT 24
Finished	Apr 28 12:52:55 PM PDT 24
Peak memory	224740 kb
Host	smart-72730006-3397-45ea-a771-b6b8b51e0863
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881476248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3881476248
Directory	/workspace/11.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/11.lc_ctrl_smoke.695205662
Short name	T737
Test name
Test status
Simulation time	85013554 ps
CPU time	1.99 seconds
Started	Apr 28 12:52:44 PM PDT 24
Finished	Apr 28 12:52:47 PM PDT 24
Peak memory	213888 kb
Host	smart-01d0f989-9519-48a1-9471-ec2baff25dd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695205662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.695205662
Directory	/workspace/11.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_failure.3251944936
Short name	T706
Test name
Test status
Simulation time	304060392 ps
CPU time	34.23 seconds
Started	Apr 28 12:52:41 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	248676 kb
Host	smart-a910bcd8-95df-41eb-844c-17c044e3a88a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251944936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3251944936
Directory	/workspace/11.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_post_trans.1550732946
Short name	T764
Test name
Test status
Simulation time	65197025 ps
CPU time	3.24 seconds
Started	Apr 28 12:52:48 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	222308 kb
Host	smart-66c69734-77c6-4de7-b2ef-f6f4c099e706
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550732946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1550732946
Directory	/workspace/11.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all.3349553159
Short name	T18
Test name
Test status
Simulation time	1045685680 ps
CPU time	21.04 seconds
Started	Apr 28 12:52:45 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	246864 kb
Host	smart-ae873a66-fff0-49b1-8806-5310204080dd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349553159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all.3349553159
Directory	/workspace/11.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.374633027
Short name	T150
Test name
Test status
Simulation time	13374172678 ps
CPU time	402.02 seconds
Started	Apr 28 12:52:45 PM PDT 24
Finished	Apr 28 12:59:28 PM PDT 24
Peak memory	316508 kb
Host	smart-5b01d88e-8a1e-4240-a61c-db8074143d47
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=374633027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.374633027
Directory	/workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1685586570
Short name	T769
Test name
Test status
Simulation time	13165702 ps
CPU time	0.92 seconds
Started	Apr 28 12:52:45 PM PDT 24
Finished	Apr 28 12:52:46 PM PDT 24
Peak memory	208492 kb
Host	smart-bc0f6abd-6280-4262-a7a3-d5c6412d3fb9
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685586570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c trl_volatile_unlock_smoke.1685586570
Directory	/workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_alert_test.2881047085
Short name	T185
Test name
Test status
Simulation time	18117447 ps
CPU time	1.17 seconds
Started	Apr 28 12:52:50 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	209464 kb
Host	smart-2f18563e-1e41-46f7-adb5-b38e7b6b2ae3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881047085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2881047085
Directory	/workspace/12.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.lc_ctrl_errors.1948644992
Short name	T717
Test name
Test status
Simulation time	2777837642 ps
CPU time	10.93 seconds
Started	Apr 28 12:52:48 PM PDT 24
Finished	Apr 28 12:52:59 PM PDT 24
Peak memory	217900 kb
Host	smart-7596c10f-767e-4382-bae7-c1e9d590d71a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948644992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1948644992
Directory	/workspace/12.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_access.2682263302
Short name	T462
Test name
Test status
Simulation time	1817899902 ps
CPU time	5.9 seconds
Started	Apr 28 12:52:49 PM PDT 24
Finished	Apr 28 12:52:55 PM PDT 24
Peak memory	209388 kb
Host	smart-f77068cf-d60a-4914-871a-6b6a04a1068b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682263302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2682263302
Directory	/workspace/12.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_errors.2946370042
Short name	T856
Test name
Test status
Simulation time	2065863880 ps
CPU time	28.35 seconds
Started	Apr 28 12:52:49 PM PDT 24
Finished	Apr 28 12:53:18 PM PDT 24
Peak memory	217824 kb
Host	smart-5c301535-127a-40e3-9254-575ec8da0afe
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946370042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e rrors.2946370042
Directory	/workspace/12.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2672556990
Short name	T816
Test name
Test status
Simulation time	1173834460 ps
CPU time	6.72 seconds
Started	Apr 28 12:52:54 PM PDT 24
Finished	Apr 28 12:53:01 PM PDT 24
Peak memory	217732 kb
Host	smart-295d8df9-701a-43c2-9a75-c726f257a559
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672556990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_prog_failure.2672556990
Directory	/workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_smoke.1809778721
Short name	T357
Test name
Test status
Simulation time	1048955595 ps
CPU time	10.97 seconds
Started	Apr 28 12:52:53 PM PDT 24
Finished	Apr 28 12:53:04 PM PDT 24
Peak memory	213636 kb
Host	smart-0e259dbd-346e-440d-aa8b-b137c73cb082
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809778721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke .1809778721
Directory	/workspace/12.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2541319396
Short name	T834
Test name
Test status
Simulation time	6782370671 ps
CPU time	58.14 seconds
Started	Apr 28 12:52:50 PM PDT 24
Finished	Apr 28 12:53:48 PM PDT 24
Peak memory	267264 kb
Host	smart-dc808c1a-5876-4a41-ba4d-f822571f268a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541319396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt ag_state_failure.2541319396
Directory	/workspace/12.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1167421477
Short name	T881
Test name
Test status
Simulation time	2728715919 ps
CPU time	12.66 seconds
Started	Apr 28 12:52:48 PM PDT 24
Finished	Apr 28 12:53:01 PM PDT 24
Peak memory	246468 kb
Host	smart-eef3059f-f6a9-4aea-aaac-6c1a6fca7bd6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167421477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_state_post_trans.1167421477
Directory	/workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_prog_failure.3556670739
Short name	T643
Test name
Test status
Simulation time	158893309 ps
CPU time	3.91 seconds
Started	Apr 28 12:52:48 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	217788 kb
Host	smart-cfcbba21-234e-4182-b393-0cf4393fcb37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556670739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3556670739
Directory	/workspace/12.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_mubi.381494519
Short name	T749
Test name
Test status
Simulation time	1185134770 ps
CPU time	18.36 seconds
Started	Apr 28 12:52:48 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	225952 kb
Host	smart-4e5305b8-709b-4798-ac10-d806bb699d98
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381494519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.381494519
Directory	/workspace/12.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_digest.2771340746
Short name	T168
Test name
Test status
Simulation time	226455103 ps
CPU time	9.54 seconds
Started	Apr 28 12:52:51 PM PDT 24
Finished	Apr 28 12:53:01 PM PDT 24
Peak memory	217896 kb
Host	smart-a54e07ff-7951-42cb-bf90-dd246b6dd305
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771340746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d igest.2771340746
Directory	/workspace/12.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_mux.156992531
Short name	T866
Test name
Test status
Simulation time	159330218 ps
CPU time	5.44 seconds
Started	Apr 28 12:52:49 PM PDT 24
Finished	Apr 28 12:52:55 PM PDT 24
Peak memory	217772 kb
Host	smart-7ab51164-beac-44b3-bba6-ffe9d54c5d90
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156992531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.156992531
Directory	/workspace/12.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/12.lc_ctrl_security_escalation.1531421481
Short name	T500
Test name
Test status
Simulation time	1455607009 ps
CPU time	8.86 seconds
Started	Apr 28 12:52:53 PM PDT 24
Finished	Apr 28 12:53:03 PM PDT 24
Peak memory	224680 kb
Host	smart-889e514b-a1ab-4388-b6c3-cfab5bf5612b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531421481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1531421481
Directory	/workspace/12.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/12.lc_ctrl_smoke.740701342
Short name	T780
Test name
Test status
Simulation time	42282702 ps
CPU time	1.57 seconds
Started	Apr 28 12:52:45 PM PDT 24
Finished	Apr 28 12:52:46 PM PDT 24
Peak memory	213556 kb
Host	smart-55cd8b50-0f2e-4ada-a4e9-46627d287e97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=740701342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.740701342
Directory	/workspace/12.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_failure.1616881325
Short name	T546
Test name
Test status
Simulation time	1207021465 ps
CPU time	26.14 seconds
Started	Apr 28 12:52:50 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	245552 kb
Host	smart-d48a8d4d-a41e-440f-9834-7e5d365ea1fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616881325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1616881325
Directory	/workspace/12.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_post_trans.1598585857
Short name	T99
Test name
Test status
Simulation time	80563976 ps
CPU time	3.25 seconds
Started	Apr 28 12:52:49 PM PDT 24
Finished	Apr 28 12:52:53 PM PDT 24
Peak memory	222128 kb
Host	smart-c76ae757-2851-42f5-b7bc-fa6a365950ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598585857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1598585857
Directory	/workspace/12.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_stress_all.4012525223
Short name	T59
Test name
Test status
Simulation time	15993435672 ps
CPU time	397.17 seconds
Started	Apr 28 12:52:51 PM PDT 24
Finished	Apr 28 12:59:29 PM PDT 24
Peak memory	250756 kb
Host	smart-34921cfa-291f-4e4c-a122-36906f599edf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012525223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.4012525223
Directory	/workspace/12.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1824806816
Short name	T855
Test name
Test status
Simulation time	12757638 ps
CPU time	1.07 seconds
Started	Apr 28 12:52:43 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	211448 kb
Host	smart-34db419d-0644-430c-9929-1157844c826b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824806816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_volatile_unlock_smoke.1824806816
Directory	/workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_alert_test.3934562463
Short name	T877
Test name
Test status
Simulation time	29940281 ps
CPU time	0.84 seconds
Started	Apr 28 12:52:54 PM PDT 24
Finished	Apr 28 12:52:55 PM PDT 24
Peak memory	209392 kb
Host	smart-9d22eb26-9a57-4d9a-960d-d5e7d710ee10
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934562463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3934562463
Directory	/workspace/13.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.lc_ctrl_errors.1017315238
Short name	T266
Test name
Test status
Simulation time	449346029 ps
CPU time	16.41 seconds
Started	Apr 28 12:52:51 PM PDT 24
Finished	Apr 28 12:53:08 PM PDT 24
Peak memory	217680 kb
Host	smart-3692a260-f4c2-4a98-bfbf-fe7e860048b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017315238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1017315238
Directory	/workspace/13.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_access.3174173277
Short name	T784
Test name
Test status
Simulation time	251358112 ps
CPU time	3.59 seconds
Started	Apr 28 12:52:54 PM PDT 24
Finished	Apr 28 12:52:58 PM PDT 24
Peak memory	216772 kb
Host	smart-61bafe84-937b-4ebb-bd37-7ec9afb2741e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174173277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3174173277
Directory	/workspace/13.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_errors.427537891
Short name	T664
Test name
Test status
Simulation time	9583854681 ps
CPU time	72.9 seconds
Started	Apr 28 12:52:54 PM PDT 24
Finished	Apr 28 12:54:08 PM PDT 24
Peak memory	218636 kb
Host	smart-097d80f9-924f-424f-8c4b-f79e41218b8d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427537891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er rors.427537891
Directory	/workspace/13.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.290941648
Short name	T760
Test name
Test status
Simulation time	638169948 ps
CPU time	10.61 seconds
Started	Apr 28 12:52:54 PM PDT 24
Finished	Apr 28 12:53:06 PM PDT 24
Peak memory	217692 kb
Host	smart-dc2211f3-7c14-4151-aba2-887f5d662762
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290941648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag _prog_failure.290941648
Directory	/workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_smoke.3519865225
Short name	T700
Test name
Test status
Simulation time	1483579840 ps
CPU time	5.88 seconds
Started	Apr 28 12:52:48 PM PDT 24
Finished	Apr 28 12:52:54 PM PDT 24
Peak memory	213584 kb
Host	smart-aa3e90e4-afdc-4967-8160-294c1ab28384
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519865225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke .3519865225
Directory	/workspace/13.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3633885343
Short name	T243
Test name
Test status
Simulation time	7358500703 ps
CPU time	40.27 seconds
Started	Apr 28 12:52:54 PM PDT 24
Finished	Apr 28 12:53:35 PM PDT 24
Peak memory	250816 kb
Host	smart-1a4c5816-ef97-4d11-9895-aaaf287e4244
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633885343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt ag_state_failure.3633885343
Directory	/workspace/13.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3669322226
Short name	T586
Test name
Test status
Simulation time	1047840895 ps
CPU time	17.12 seconds
Started	Apr 28 12:52:56 PM PDT 24
Finished	Apr 28 12:53:14 PM PDT 24
Peak memory	250536 kb
Host	smart-e072e9d2-9cc6-47f0-8ad2-269adf96e98d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669322226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _jtag_state_post_trans.3669322226
Directory	/workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_prog_failure.3525169963
Short name	T580
Test name
Test status
Simulation time	437772062 ps
CPU time	4.2 seconds
Started	Apr 28 12:52:50 PM PDT 24
Finished	Apr 28 12:52:55 PM PDT 24
Peak memory	217824 kb
Host	smart-2ccd010b-ed7b-46fd-ac9b-57e1e4b769db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3525169963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3525169963
Directory	/workspace/13.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_mubi.559737116
Short name	T323
Test name
Test status
Simulation time	750332484 ps
CPU time	11.7 seconds
Started	Apr 28 12:52:54 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	217816 kb
Host	smart-c15d0ff3-963e-4857-bea0-dd0bc7e30518
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559737116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.559737116
Directory	/workspace/13.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_digest.2471356152
Short name	T564
Test name
Test status
Simulation time	496099291 ps
CPU time	11.67 seconds
Started	Apr 28 12:52:55 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	217864 kb
Host	smart-b33b377b-f3c2-45f7-84bc-6d0922b943e6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471356152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d igest.2471356152
Directory	/workspace/13.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_mux.4173583907
Short name	T522
Test name
Test status
Simulation time	504383424 ps
CPU time	10.77 seconds
Started	Apr 28 12:52:55 PM PDT 24
Finished	Apr 28 12:53:06 PM PDT 24
Peak memory	217728 kb
Host	smart-1c470b40-d147-4eac-8891-1bd4fa099aae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173583907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux. 4173583907
Directory	/workspace/13.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/13.lc_ctrl_security_escalation.3664497280
Short name	T52
Test name
Test status
Simulation time	387189280 ps
CPU time	14.46 seconds
Started	Apr 28 12:52:51 PM PDT 24
Finished	Apr 28 12:53:05 PM PDT 24
Peak memory	217872 kb
Host	smart-33c5723f-e9a3-4b37-ba0e-996f96e48222
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664497280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3664497280
Directory	/workspace/13.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/13.lc_ctrl_smoke.3494001448
Short name	T619
Test name
Test status
Simulation time	581218035 ps
CPU time	2.54 seconds
Started	Apr 28 12:52:49 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	214024 kb
Host	smart-fe57c90a-d664-4b4c-aefa-f525c7687b5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494001448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3494001448
Directory	/workspace/13.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_failure.2195302327
Short name	T583
Test name
Test status
Simulation time	1384679132 ps
CPU time	28.5 seconds
Started	Apr 28 12:52:51 PM PDT 24
Finished	Apr 28 12:53:20 PM PDT 24
Peak memory	248328 kb
Host	smart-842fa5b2-ecd5-4e26-bc0e-f45d2f8edff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195302327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2195302327
Directory	/workspace/13.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_post_trans.2408336786
Short name	T794
Test name
Test status
Simulation time	354579387 ps
CPU time	8.08 seconds
Started	Apr 28 12:52:49 PM PDT 24
Finished	Apr 28 12:52:57 PM PDT 24
Peak memory	250772 kb
Host	smart-d45aa362-197c-452e-a7a0-a68415353f9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2408336786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2408336786
Directory	/workspace/13.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all.1711134858
Short name	T808
Test name
Test status
Simulation time	14355357372 ps
CPU time	107.38 seconds
Started	Apr 28 12:52:58 PM PDT 24
Finished	Apr 28 12:54:46 PM PDT 24
Peak memory	405068 kb
Host	smart-639537b7-a0ed-4aa2-99c3-b4a775e0ba12
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711134858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.1711134858
Directory	/workspace/13.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.801093965
Short name	T22
Test name
Test status
Simulation time	93525859 ps
CPU time	1.15 seconds
Started	Apr 28 12:52:49 PM PDT 24
Finished	Apr 28 12:52:51 PM PDT 24
Peak memory	212576 kb
Host	smart-d97edf4d-6785-4cbf-a6bf-4db30cbeb845
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801093965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct rl_volatile_unlock_smoke.801093965
Directory	/workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_alert_test.1256197317
Short name	T879
Test name
Test status
Simulation time	74903223 ps
CPU time	0.9 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:01 PM PDT 24
Peak memory	209416 kb
Host	smart-b46282e3-4864-4fe4-8f2a-1e45c481d917
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256197317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1256197317
Directory	/workspace/14.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.lc_ctrl_errors.1840668792
Short name	T552
Test name
Test status
Simulation time	1233440741 ps
CPU time	10.09 seconds
Started	Apr 28 12:52:57 PM PDT 24
Finished	Apr 28 12:53:08 PM PDT 24
Peak memory	225960 kb
Host	smart-a8200cc3-6f39-4058-a2d9-c6c84eeab227
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840668792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1840668792
Directory	/workspace/14.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_access.445831235
Short name	T26
Test name
Test status
Simulation time	932967012 ps
CPU time	3.72 seconds
Started	Apr 28 12:52:55 PM PDT 24
Finished	Apr 28 12:52:59 PM PDT 24
Peak memory	209436 kb
Host	smart-e35627ba-7ba2-4d9f-8664-dbfcc0a23cb1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445831235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.445831235
Directory	/workspace/14.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_errors.2681185164
Short name	T703
Test name
Test status
Simulation time	8948059414 ps
CPU time	58.48 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:58 PM PDT 24
Peak memory	217800 kb
Host	smart-14a2267f-0efe-4176-9d85-69c4ffa58bc7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681185164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e rrors.2681185164
Directory	/workspace/14.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.370220812
Short name	T426
Test name
Test status
Simulation time	375311167 ps
CPU time	10.46 seconds
Started	Apr 28 12:52:52 PM PDT 24
Finished	Apr 28 12:53:03 PM PDT 24
Peak memory	217856 kb
Host	smart-80444dd2-16e7-4015-bb33-5b83d05f03ce
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370220812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag _prog_failure.370220812
Directory	/workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_smoke.2165159006
Short name	T844
Test name
Test status
Simulation time	66668783 ps
CPU time	1.58 seconds
Started	Apr 28 12:52:56 PM PDT 24
Finished	Apr 28 12:52:58 PM PDT 24
Peak memory	212484 kb
Host	smart-cd3c61d8-6e3e-4d12-97d4-e07d6ccf0d86
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165159006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke .2165159006
Directory	/workspace/14.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1236258299
Short name	T309
Test name
Test status
Simulation time	5004364665 ps
CPU time	47.17 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:47 PM PDT 24
Peak memory	250880 kb
Host	smart-c1716d36-65d5-45f3-a364-dfbe5fbc810e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236258299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt ag_state_failure.1236258299
Directory	/workspace/14.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2256471597
Short name	T672
Test name
Test status
Simulation time	1956139427 ps
CPU time	19.4 seconds
Started	Apr 28 12:52:58 PM PDT 24
Finished	Apr 28 12:53:18 PM PDT 24
Peak memory	250732 kb
Host	smart-e52e0777-b5b0-441e-ba3c-ac2ec770c630
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256471597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _jtag_state_post_trans.2256471597
Directory	/workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_prog_failure.1682367716
Short name	T631
Test name
Test status
Simulation time	87293431 ps
CPU time	3.11 seconds
Started	Apr 28 12:52:55 PM PDT 24
Finished	Apr 28 12:52:59 PM PDT 24
Peak memory	217780 kb
Host	smart-e3d44d51-1cd3-47a2-83b5-3dfae8033b3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682367716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1682367716
Directory	/workspace/14.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_mubi.3941732170
Short name	T260
Test name
Test status
Simulation time	339735619 ps
CPU time	12.31 seconds
Started	Apr 28 12:53:00 PM PDT 24
Finished	Apr 28 12:53:13 PM PDT 24
Peak memory	225832 kb
Host	smart-221303db-c0f1-417d-bcf2-9b560bc3803f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941732170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3941732170
Directory	/workspace/14.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_digest.3464622214
Short name	T279
Test name
Test status
Simulation time	837177837 ps
CPU time	11.32 seconds
Started	Apr 28 12:52:58 PM PDT 24
Finished	Apr 28 12:53:10 PM PDT 24
Peak memory	217800 kb
Host	smart-0a6869be-b54e-4997-a38b-e2ef50f5b2d7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464622214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d igest.3464622214
Directory	/workspace/14.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_mux.3535017333
Short name	T740
Test name
Test status
Simulation time	362820261 ps
CPU time	9.15 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:09 PM PDT 24
Peak memory	217724 kb
Host	smart-ee910cea-0a23-4f8e-9e45-6e920a0c286a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535017333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux. 3535017333
Directory	/workspace/14.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/14.lc_ctrl_security_escalation.3199819046
Short name	T467
Test name
Test status
Simulation time	253591293 ps
CPU time	9.09 seconds
Started	Apr 28 12:52:55 PM PDT 24
Finished	Apr 28 12:53:05 PM PDT 24
Peak memory	217896 kb
Host	smart-5e9e0ed7-9ea1-4306-9b8c-4db9eedd56a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199819046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3199819046
Directory	/workspace/14.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/14.lc_ctrl_smoke.20657724
Short name	T86
Test name
Test status
Simulation time	205497112 ps
CPU time	3.71 seconds
Started	Apr 28 12:52:56 PM PDT 24
Finished	Apr 28 12:53:00 PM PDT 24
Peak memory	214048 kb
Host	smart-82b54693-7909-4bb6-8507-4332b809f0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20657724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.20657724
Directory	/workspace/14.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_failure.3507953382
Short name	T593
Test name
Test status
Simulation time	1572053538 ps
CPU time	30.32 seconds
Started	Apr 28 12:52:55 PM PDT 24
Finished	Apr 28 12:53:26 PM PDT 24
Peak memory	249264 kb
Host	smart-1c68c18b-b219-4274-ad3c-0e1da2ef427f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507953382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3507953382
Directory	/workspace/14.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_post_trans.2033017052
Short name	T240
Test name
Test status
Simulation time	90340152 ps
CPU time	7.7 seconds
Started	Apr 28 12:52:58 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	248188 kb
Host	smart-4ecb0114-5b26-46e0-9240-737807f95966
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033017052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2033017052
Directory	/workspace/14.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all.4104012195
Short name	T157
Test name
Test status
Simulation time	2960990792 ps
CPU time	55.97 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:56 PM PDT 24
Peak memory	223564 kb
Host	smart-bdbb657e-a4e2-4ea0-9ddf-d7757faf9c16
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104012195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.4104012195
Directory	/workspace/14.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.4266869522
Short name	T49
Test name
Test status
Simulation time	26501204651 ps
CPU time	673.98 seconds
Started	Apr 28 12:53:00 PM PDT 24
Finished	Apr 28 01:04:15 PM PDT 24
Peak memory	496864 kb
Host	smart-445b4d1d-d059-43d6-8545-941060bff925
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4266869522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.4266869522
Directory	/workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2119437910
Short name	T698
Test name
Test status
Simulation time	12569678 ps
CPU time	0.79 seconds
Started	Apr 28 12:52:55 PM PDT 24
Finished	Apr 28 12:52:56 PM PDT 24
Peak memory	208384 kb
Host	smart-f45ffad4-f792-4453-9019-dc061a13f7c1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119437910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_volatile_unlock_smoke.2119437910
Directory	/workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_alert_test.312909955
Short name	T504
Test name
Test status
Simulation time	75911366 ps
CPU time	0.89 seconds
Started	Apr 28 12:53:05 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	209344 kb
Host	smart-2364e1ea-64dd-44a6-9611-6c8877ae2cd5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312909955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.312909955
Directory	/workspace/15.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.lc_ctrl_errors.4158722697
Short name	T284
Test name
Test status
Simulation time	1039710753 ps
CPU time	11.04 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	217796 kb
Host	smart-c58b298e-4215-4c97-99b5-e24bc017cad6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158722697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4158722697
Directory	/workspace/15.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_access.3834653696
Short name	T647
Test name
Test status
Simulation time	347312774 ps
CPU time	1.8 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	216684 kb
Host	smart-cbce5925-5848-4549-9720-7c1e5e95ba17
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834653696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3834653696
Directory	/workspace/15.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_errors.1180806282
Short name	T809
Test name
Test status
Simulation time	12180223035 ps
CPU time	38.91 seconds
Started	Apr 28 12:52:57 PM PDT 24
Finished	Apr 28 12:53:37 PM PDT 24
Peak memory	218196 kb
Host	smart-d19b2c1f-a7db-4bd5-880b-b03d51683679
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180806282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e rrors.1180806282
Directory	/workspace/15.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3704884713
Short name	T569
Test name
Test status
Simulation time	238206275 ps
CPU time	4.34 seconds
Started	Apr 28 12:53:05 PM PDT 24
Finished	Apr 28 12:53:10 PM PDT 24
Peak memory	217708 kb
Host	smart-a638d738-2d2e-4564-ae90-326aa93a35c9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704884713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_prog_failure.3704884713
Directory	/workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_smoke.2637749252
Short name	T553
Test name
Test status
Simulation time	533985426 ps
CPU time	5.44 seconds
Started	Apr 28 12:52:57 PM PDT 24
Finished	Apr 28 12:53:03 PM PDT 24
Peak memory	213532 kb
Host	smart-63529102-5a12-41e1-9464-805cec931a38
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637749252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke .2637749252
Directory	/workspace/15.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3594921581
Short name	T103
Test name
Test status
Simulation time	8883649757 ps
CPU time	130.63 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:55:15 PM PDT 24
Peak memory	281040 kb
Host	smart-d39e383a-edfa-4a1c-b383-130c5344f2ed
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594921581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_state_failure.3594921581
Directory	/workspace/15.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_prog_failure.3667296958
Short name	T574
Test name
Test status
Simulation time	171575990 ps
CPU time	3.94 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:09 PM PDT 24
Peak memory	217768 kb
Host	smart-b7fa729e-6d77-40b7-8c06-461b043e64f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667296958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3667296958
Directory	/workspace/15.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_mubi.750795915
Short name	T358
Test name
Test status
Simulation time	242727527 ps
CPU time	9.61 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:10 PM PDT 24
Peak memory	218380 kb
Host	smart-8f68ec16-de11-439d-b5a3-7c4e7e108ae0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750795915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.750795915
Directory	/workspace/15.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_digest.4018808827
Short name	T254
Test name
Test status
Simulation time	2649614099 ps
CPU time	11.39 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:11 PM PDT 24
Peak memory	217972 kb
Host	smart-ad46ac27-3e97-4d4e-a7f1-760b100fbfe9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018808827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d igest.4018808827
Directory	/workspace/15.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_mux.1119942693
Short name	T815
Test name
Test status
Simulation time	645268517 ps
CPU time	8.26 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:13 PM PDT 24
Peak memory	217796 kb
Host	smart-4d1365c2-b8a7-4fce-b501-7b5c3f67a9ad
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119942693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux. 1119942693
Directory	/workspace/15.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/15.lc_ctrl_security_escalation.2622854311
Short name	T599
Test name
Test status
Simulation time	1478849118 ps
CPU time	13.73 seconds
Started	Apr 28 12:53:05 PM PDT 24
Finished	Apr 28 12:53:19 PM PDT 24
Peak memory	217836 kb
Host	smart-4ac9bb21-e46c-424f-9158-0583249db924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622854311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2622854311
Directory	/workspace/15.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/15.lc_ctrl_smoke.3739933484
Short name	T849
Test name
Test status
Simulation time	46111677 ps
CPU time	2.58 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:03 PM PDT 24
Peak memory	214048 kb
Host	smart-0027d30f-1ce8-4709-9a7f-c17181e7c880
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739933484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3739933484
Directory	/workspace/15.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_failure.585223349
Short name	T724
Test name
Test status
Simulation time	608378942 ps
CPU time	30.19 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:30 PM PDT 24
Peak memory	250796 kb
Host	smart-5e45a4bc-2189-4d28-9324-45c8c94e990f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585223349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.585223349
Directory	/workspace/15.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_post_trans.4106112527
Short name	T477
Test name
Test status
Simulation time	78250377 ps
CPU time	9.45 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:14 PM PDT 24
Peak memory	250780 kb
Host	smart-b8a35322-3b3d-4f28-ac3a-a1be8d86d949
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106112527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4106112527
Directory	/workspace/15.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all.4245187359
Short name	T94
Test name
Test status
Simulation time	22199430755 ps
CPU time	76.27 seconds
Started	Apr 28 12:52:58 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	267752 kb
Host	smart-39041dec-ecd6-48f0-8d3a-ce78a57fa667
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245187359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.4245187359
Directory	/workspace/15.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1521106566
Short name	T153
Test name
Test status
Simulation time	104840979034 ps
CPU time	934.63 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 01:08:35 PM PDT 24
Peak memory	389084 kb
Host	smart-286b1889-85e0-4b30-ad27-a3b8f7a72b57
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1521106566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1521106566
Directory	/workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1328160958
Short name	T236
Test name
Test status
Simulation time	20250427 ps
CPU time	0.99 seconds
Started	Apr 28 12:52:59 PM PDT 24
Finished	Apr 28 12:53:01 PM PDT 24
Peak memory	211444 kb
Host	smart-4040a658-f839-4db3-a85b-0bec0e0c967d
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328160958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_volatile_unlock_smoke.1328160958
Directory	/workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_alert_test.558365349
Short name	T92
Test name
Test status
Simulation time	89514649 ps
CPU time	0.94 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:06 PM PDT 24
Peak memory	209424 kb
Host	smart-70cba4e3-6625-47c1-baf6-488a786937a3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558365349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.558365349
Directory	/workspace/16.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.lc_ctrl_errors.109140031
Short name	T666
Test name
Test status
Simulation time	1094119817 ps
CPU time	8.9 seconds
Started	Apr 28 12:53:08 PM PDT 24
Finished	Apr 28 12:53:17 PM PDT 24
Peak memory	225864 kb
Host	smart-c51ec567-7570-40ea-88bd-31b9055d041b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109140031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.109140031
Directory	/workspace/16.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_access.4191607800
Short name	T451
Test name
Test status
Simulation time	118425234 ps
CPU time	3.19 seconds
Started	Apr 28 12:53:03 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	216764 kb
Host	smart-4d0ea9f2-aa15-4af1-a65a-a4bda0322302
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191607800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.4191607800
Directory	/workspace/16.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_errors.986197514
Short name	T521
Test name
Test status
Simulation time	8385748395 ps
CPU time	63.28 seconds
Started	Apr 28 12:53:06 PM PDT 24
Finished	Apr 28 12:54:10 PM PDT 24
Peak memory	218772 kb
Host	smart-10976111-879b-4dab-a80d-2e850ddb5b6e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986197514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er rors.986197514
Directory	/workspace/16.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4021478065
Short name	T259
Test name
Test status
Simulation time	290136832 ps
CPU time	9.02 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:14 PM PDT 24
Peak memory	217812 kb
Host	smart-cf2c6e25-ed84-4baa-9485-e88469a1a280
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021478065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_prog_failure.4021478065
Directory	/workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_smoke.2073808271
Short name	T328
Test name
Test status
Simulation time	1941626031 ps
CPU time	5.61 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:53:17 PM PDT 24
Peak memory	213504 kb
Host	smart-830453d7-e061-40ea-8668-4508303022b7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073808271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke .2073808271
Directory	/workspace/16.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_failure.762651834
Short name	T756
Test name
Test status
Simulation time	2011182965 ps
CPU time	43.78 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:49 PM PDT 24
Peak memory	274056 kb
Host	smart-627f7e65-6674-4240-abe1-18ec55cca827
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762651834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_state_failure.762651834
Directory	/workspace/16.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1963496427
Short name	T728
Test name
Test status
Simulation time	1838523648 ps
CPU time	14.48 seconds
Started	Apr 28 12:53:08 PM PDT 24
Finished	Apr 28 12:53:23 PM PDT 24
Peak memory	250704 kb
Host	smart-63ff026d-f288-477c-88da-4d3fba2755fd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963496427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_state_post_trans.1963496427
Directory	/workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_prog_failure.4141006207
Short name	T422
Test name
Test status
Simulation time	88134524 ps
CPU time	1.94 seconds
Started	Apr 28 12:53:05 PM PDT 24
Finished	Apr 28 12:53:08 PM PDT 24
Peak memory	217796 kb
Host	smart-47e578c6-01db-47ce-9866-8307ff6136e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141006207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.4141006207
Directory	/workspace/16.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_mubi.1554295244
Short name	T64
Test name
Test status
Simulation time	695562795 ps
CPU time	14.76 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:20 PM PDT 24
Peak memory	218800 kb
Host	smart-0c13ff54-6735-4f1d-8bf6-faa13c29e976
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554295244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1554295244
Directory	/workspace/16.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_digest.1639698246
Short name	T707
Test name
Test status
Simulation time	8257678720 ps
CPU time	19.13 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:24 PM PDT 24
Peak memory	217928 kb
Host	smart-742c604a-aedf-4dc0-bbda-ed6d9d5e45a5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639698246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d igest.1639698246
Directory	/workspace/16.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_mux.2662611326
Short name	T63
Test name
Test status
Simulation time	825550672 ps
CPU time	5.66 seconds
Started	Apr 28 12:53:07 PM PDT 24
Finished	Apr 28 12:53:13 PM PDT 24
Peak memory	217756 kb
Host	smart-4bec859e-d15c-4cc2-bf8b-0e6a0106a466
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662611326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux. 2662611326
Directory	/workspace/16.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/16.lc_ctrl_security_escalation.478479403
Short name	T536
Test name
Test status
Simulation time	828468997 ps
CPU time	9.11 seconds
Started	Apr 28 12:53:06 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	217880 kb
Host	smart-7d29b720-391d-42e9-8836-f6ae9b125c19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478479403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.478479403
Directory	/workspace/16.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/16.lc_ctrl_smoke.1716543842
Short name	T562
Test name
Test status
Simulation time	103275838 ps
CPU time	3.59 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:53:14 PM PDT 24
Peak memory	214276 kb
Host	smart-a8d76756-c344-4020-b9b1-7797b4ed1bb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716543842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1716543842
Directory	/workspace/16.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_failure.1807968701
Short name	T191
Test name
Test status
Simulation time	2078441749 ps
CPU time	24.27 seconds
Started	Apr 28 12:53:06 PM PDT 24
Finished	Apr 28 12:53:31 PM PDT 24
Peak memory	250432 kb
Host	smart-f8b39967-b6af-40d7-9a78-ae23064820f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807968701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1807968701
Directory	/workspace/16.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_post_trans.695046449
Short name	T696
Test name
Test status
Simulation time	62646951 ps
CPU time	6.44 seconds
Started	Apr 28 12:53:08 PM PDT 24
Finished	Apr 28 12:53:15 PM PDT 24
Peak memory	250260 kb
Host	smart-319701d4-9fce-40fe-8467-4e06a5d76108
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695046449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.695046449
Directory	/workspace/16.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all.3092403630
Short name	T298
Test name
Test status
Simulation time	905932440 ps
CPU time	25.09 seconds
Started	Apr 28 12:53:06 PM PDT 24
Finished	Apr 28 12:53:32 PM PDT 24
Peak memory	250776 kb
Host	smart-13de947c-e423-4490-80fa-3fd85bc50172
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092403630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.3092403630
Directory	/workspace/16.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3098477096
Short name	T220
Test name
Test status
Simulation time	23598553782 ps
CPU time	547.75 seconds
Started	Apr 28 12:53:08 PM PDT 24
Finished	Apr 28 01:02:16 PM PDT 24
Peak memory	332956 kb
Host	smart-420496ca-d1cc-4f9b-a08f-22b2a0fcb6ca
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3098477096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3098477096
Directory	/workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1960477159
Short name	T307
Test name
Test status
Simulation time	13644609 ps
CPU time	0.93 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:06 PM PDT 24
Peak memory	211380 kb
Host	smart-29b55204-3394-4ea8-9d28-646f5ace1061
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960477159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c trl_volatile_unlock_smoke.1960477159
Directory	/workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_alert_test.2406335934
Short name	T403
Test name
Test status
Simulation time	112796129 ps
CPU time	0.93 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:53:12 PM PDT 24
Peak memory	209436 kb
Host	smart-51678efe-aa73-4172-97ea-a51d7a9ced3f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406335934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2406335934
Directory	/workspace/17.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.lc_ctrl_errors.2383329830
Short name	T514
Test name
Test status
Simulation time	329951646 ps
CPU time	11.02 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	217772 kb
Host	smart-d1cd4dbf-b4f6-44e3-a3dd-4611825e19f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383329830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2383329830
Directory	/workspace/17.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_access.1394764321
Short name	T23
Test name
Test status
Simulation time	2460357094 ps
CPU time	16.15 seconds
Started	Apr 28 12:53:07 PM PDT 24
Finished	Apr 28 12:53:24 PM PDT 24
Peak memory	209468 kb
Host	smart-caf3d5df-dc1a-4938-9460-a2d23b5ee611
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394764321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1394764321
Directory	/workspace/17.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_errors.379688954
Short name	T731
Test name
Test status
Simulation time	1861009487 ps
CPU time	35.43 seconds
Started	Apr 28 12:53:05 PM PDT 24
Finished	Apr 28 12:53:41 PM PDT 24
Peak memory	217676 kb
Host	smart-70284fe0-6fe3-44e9-8141-4de1d464e757
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379688954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er rors.379688954
Directory	/workspace/17.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2896192265
Short name	T470
Test name
Test status
Simulation time	174397113 ps
CPU time	3.86 seconds
Started	Apr 28 12:53:05 PM PDT 24
Finished	Apr 28 12:53:09 PM PDT 24
Peak memory	217716 kb
Host	smart-fb66af4c-a5dd-497d-8e03-bae41d556dcc
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896192265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_prog_failure.2896192265
Directory	/workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_smoke.2429015679
Short name	T880
Test name
Test status
Simulation time	2386501417 ps
CPU time	4.78 seconds
Started	Apr 28 12:53:06 PM PDT 24
Finished	Apr 28 12:53:12 PM PDT 24
Peak memory	214020 kb
Host	smart-df335bd5-3b4a-4077-baa8-c8d761044d55
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429015679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke .2429015679
Directory	/workspace/17.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.638910696
Short name	T837
Test name
Test status
Simulation time	5802661904 ps
CPU time	53.97 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:54:05 PM PDT 24
Peak memory	270200 kb
Host	smart-22b72b8f-f1b7-42ba-8492-e160c4fd5c77
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638910696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_state_failure.638910696
Directory	/workspace/17.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1967876944
Short name	T692
Test name
Test status
Simulation time	2002368287 ps
CPU time	19.25 seconds
Started	Apr 28 12:53:06 PM PDT 24
Finished	Apr 28 12:53:26 PM PDT 24
Peak memory	248892 kb
Host	smart-bb5ff733-2fbe-4ffb-a667-97dede440d9c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967876944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_state_post_trans.1967876944
Directory	/workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_prog_failure.3249212476
Short name	T341
Test name
Test status
Simulation time	107730932 ps
CPU time	1.99 seconds
Started	Apr 28 12:53:19 PM PDT 24
Finished	Apr 28 12:53:21 PM PDT 24
Peak memory	217788 kb
Host	smart-06d2457d-7cb6-467f-b13f-df9bd44d4e19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249212476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3249212476
Directory	/workspace/17.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_mubi.2082826002
Short name	T330
Test name
Test status
Simulation time	1075624046 ps
CPU time	14.33 seconds
Started	Apr 28 12:53:11 PM PDT 24
Finished	Apr 28 12:53:26 PM PDT 24
Peak memory	218800 kb
Host	smart-4ffb9597-6f44-4593-b488-3a952edac8e4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082826002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2082826002
Directory	/workspace/17.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_digest.4129785087
Short name	T344
Test name
Test status
Simulation time	473746559 ps
CPU time	12.08 seconds
Started	Apr 28 12:53:09 PM PDT 24
Finished	Apr 28 12:53:21 PM PDT 24
Peak memory	217796 kb
Host	smart-909d4b0a-dfc5-4c12-8da4-f4c8655c705e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129785087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d igest.4129785087
Directory	/workspace/17.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_mux.1887039514
Short name	T457
Test name
Test status
Simulation time	629847404 ps
CPU time	12.86 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:53:24 PM PDT 24
Peak memory	217828 kb
Host	smart-ccfaafad-b0c5-4519-9743-7978a9bcfe0f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887039514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux. 1887039514
Directory	/workspace/17.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/17.lc_ctrl_security_escalation.2088732646
Short name	T54
Test name
Test status
Simulation time	1064062538 ps
CPU time	7.05 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:12 PM PDT 24
Peak memory	217860 kb
Host	smart-e4973d63-e325-4adb-917e-f58b055bc623
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088732646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2088732646
Directory	/workspace/17.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/17.lc_ctrl_smoke.1639129579
Short name	T436
Test name
Test status
Simulation time	59680470 ps
CPU time	3.32 seconds
Started	Apr 28 12:53:08 PM PDT 24
Finished	Apr 28 12:53:12 PM PDT 24
Peak memory	217788 kb
Host	smart-95927d1b-ebc8-4e3e-a4a9-625b02fadcd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639129579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1639129579
Directory	/workspace/17.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_failure.1341615775
Short name	T361
Test name
Test status
Simulation time	225940337 ps
CPU time	25.54 seconds
Started	Apr 28 12:53:06 PM PDT 24
Finished	Apr 28 12:53:33 PM PDT 24
Peak memory	248584 kb
Host	smart-6d7570e1-050a-49b4-9ce6-c357f329e7b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341615775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1341615775
Directory	/workspace/17.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_post_trans.4259007960
Short name	T517
Test name
Test status
Simulation time	74398423 ps
CPU time	8.3 seconds
Started	Apr 28 12:53:07 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	250596 kb
Host	smart-98d3101d-9dc2-4c87-bc92-1f708e1537b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259007960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4259007960
Directory	/workspace/17.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all.966923307
Short name	T194
Test name
Test status
Simulation time	5105695819 ps
CPU time	177.22 seconds
Started	Apr 28 12:53:14 PM PDT 24
Finished	Apr 28 12:56:12 PM PDT 24
Peak memory	250664 kb
Host	smart-1616405d-de65-4dbe-9268-91824dc35243
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966923307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all.966923307
Directory	/workspace/17.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2420239185
Short name	T219
Test name
Test status
Simulation time	58187243720 ps
CPU time	877.06 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 01:07:48 PM PDT 24
Peak memory	496584 kb
Host	smart-d8592cee-1a41-4e8f-82db-e82b61283434
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2420239185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2420239185
Directory	/workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3543166585
Short name	T684
Test name
Test status
Simulation time	24157704 ps
CPU time	0.78 seconds
Started	Apr 28 12:53:04 PM PDT 24
Finished	Apr 28 12:53:06 PM PDT 24
Peak memory	208536 kb
Host	smart-e2869d3f-87eb-4d3c-95ba-039952d1c380
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543166585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_volatile_unlock_smoke.3543166585
Directory	/workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_alert_test.3204527233
Short name	T76
Test name
Test status
Simulation time	83744169 ps
CPU time	1.03 seconds
Started	Apr 28 12:53:09 PM PDT 24
Finished	Apr 28 12:53:11 PM PDT 24
Peak memory	209296 kb
Host	smart-546ca4d8-21bc-41fe-80b4-057acb3b3fdf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204527233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3204527233
Directory	/workspace/18.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.lc_ctrl_errors.2115973889
Short name	T45
Test name
Test status
Simulation time	579859985 ps
CPU time	17.01 seconds
Started	Apr 28 12:53:11 PM PDT 24
Finished	Apr 28 12:53:28 PM PDT 24
Peak memory	217820 kb
Host	smart-317981a8-97b7-4827-ac81-635923e5f4fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115973889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2115973889
Directory	/workspace/18.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_access.3211614115
Short name	T8
Test name
Test status
Simulation time	423255853 ps
CPU time	4.32 seconds
Started	Apr 28 12:53:11 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	216832 kb
Host	smart-df3a9c2a-47ca-4456-8e9b-1704fec9ff9d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211614115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3211614115
Directory	/workspace/18.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_errors.464787356
Short name	T41
Test name
Test status
Simulation time	1386232408 ps
CPU time	26.48 seconds
Started	Apr 28 12:53:11 PM PDT 24
Finished	Apr 28 12:53:38 PM PDT 24
Peak memory	217788 kb
Host	smart-c0680d10-c243-433a-a6ba-3450d4aef0e5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464787356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er rors.464787356
Directory	/workspace/18.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.28911
Short name	T591
Test name
Test status
Simulation time	537789277 ps
CPU time	8.17 seconds
Started	Apr 28 12:53:13 PM PDT 24
Finished	Apr 28 12:53:22 PM PDT 24
Peak memory	217648 kb
Host	smart-a7185f0a-2970-4755-8dbd-ed2bbdb7bb29
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog _failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_pro g_failure.28911
Directory	/workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_smoke.3665135933
Short name	T695
Test name
Test status
Simulation time	433799615 ps
CPU time	5.49 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	213300 kb
Host	smart-7a40fd93-07f8-4eee-8630-ed1acaaf28f4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665135933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke .3665135933
Directory	/workspace/18.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2747826841
Short name	T838
Test name
Test status
Simulation time	1705311486 ps
CPU time	41.59 seconds
Started	Apr 28 12:53:09 PM PDT 24
Finished	Apr 28 12:53:52 PM PDT 24
Peak memory	276708 kb
Host	smart-d165f7b7-a069-41d6-a7bb-5aed10c9a724
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747826841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt ag_state_failure.2747826841
Directory	/workspace/18.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1199449610
Short name	T377
Test name
Test status
Simulation time	904256119 ps
CPU time	17.54 seconds
Started	Apr 28 12:53:09 PM PDT 24
Finished	Apr 28 12:53:27 PM PDT 24
Peak memory	246972 kb
Host	smart-fc6de510-4c79-4ff7-9eef-3f443dea5f61
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199449610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_state_post_trans.1199449610
Directory	/workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_prog_failure.3651645938
Short name	T287
Test name
Test status
Simulation time	50808773 ps
CPU time	2.91 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:20 PM PDT 24
Peak memory	217784 kb
Host	smart-03941acf-d31a-4981-8394-6ee9ae5ca51c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651645938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3651645938
Directory	/workspace/18.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_mubi.634236358
Short name	T180
Test name
Test status
Simulation time	293780402 ps
CPU time	10.29 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:27 PM PDT 24
Peak memory	225952 kb
Host	smart-bb5cc20d-8094-41e0-9ff5-e11afee3c7ca
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634236358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.634236358
Directory	/workspace/18.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_digest.4284570863
Short name	T393
Test name
Test status
Simulation time	2221923057 ps
CPU time	12.28 seconds
Started	Apr 28 12:53:34 PM PDT 24
Finished	Apr 28 12:53:47 PM PDT 24
Peak memory	217840 kb
Host	smart-aff14712-c118-46b6-be3f-b763957fcb54
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284570863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d igest.4284570863
Directory	/workspace/18.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_mux.729399845
Short name	T579
Test name
Test status
Simulation time	259909537 ps
CPU time	9.82 seconds
Started	Apr 28 12:53:14 PM PDT 24
Finished	Apr 28 12:53:24 PM PDT 24
Peak memory	217716 kb
Host	smart-f98e2dc6-461b-4eb2-8c17-14684bff6361
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729399845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.729399845
Directory	/workspace/18.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/18.lc_ctrl_security_escalation.3343099283
Short name	T229
Test name
Test status
Simulation time	409250845 ps
CPU time	7.35 seconds
Started	Apr 28 12:53:14 PM PDT 24
Finished	Apr 28 12:53:22 PM PDT 24
Peak memory	225216 kb
Host	smart-3d27afc6-c0b5-4105-936d-b2d5b878dfea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3343099283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3343099283
Directory	/workspace/18.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/18.lc_ctrl_smoke.240539123
Short name	T36
Test name
Test status
Simulation time	167993160 ps
CPU time	1.68 seconds
Started	Apr 28 12:53:18 PM PDT 24
Finished	Apr 28 12:53:20 PM PDT 24
Peak memory	213376 kb
Host	smart-93fca3b9-c9e4-4dcc-b5f7-829ac4952eb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240539123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.240539123
Directory	/workspace/18.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_failure.2930563906
Short name	T461
Test name
Test status
Simulation time	1011155274 ps
CPU time	24.87 seconds
Started	Apr 28 12:53:09 PM PDT 24
Finished	Apr 28 12:53:35 PM PDT 24
Peak memory	250728 kb
Host	smart-20120a2d-785a-41c8-8c8b-de314bb58707
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930563906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2930563906
Directory	/workspace/18.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_post_trans.4218760077
Short name	T772
Test name
Test status
Simulation time	172796135 ps
CPU time	10.05 seconds
Started	Apr 28 12:53:13 PM PDT 24
Finished	Apr 28 12:53:23 PM PDT 24
Peak memory	246736 kb
Host	smart-9c81241e-006c-440f-ad81-bce3834b4b55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218760077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.4218760077
Directory	/workspace/18.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all.3773092098
Short name	T688
Test name
Test status
Simulation time	118762399965 ps
CPU time	239.54 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	282380 kb
Host	smart-d6640146-9664-4df4-9f18-ec8b47202953
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773092098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.3773092098
Directory	/workspace/18.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.171258217
Short name	T371
Test name
Test status
Simulation time	19942095 ps
CPU time	0.97 seconds
Started	Apr 28 12:53:09 PM PDT 24
Finished	Apr 28 12:53:10 PM PDT 24
Peak memory	212380 kb
Host	smart-ece67c80-c72c-486e-816d-68e04f4f2b64
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171258217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct rl_volatile_unlock_smoke.171258217
Directory	/workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_alert_test.1128756300
Short name	T590
Test name
Test status
Simulation time	15322507 ps
CPU time	1.04 seconds
Started	Apr 28 12:53:15 PM PDT 24
Finished	Apr 28 12:53:17 PM PDT 24
Peak memory	209388 kb
Host	smart-f48014f0-1600-4335-b20b-089549d5240b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128756300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1128756300
Directory	/workspace/19.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.lc_ctrl_errors.1988420838
Short name	T47
Test name
Test status
Simulation time	241915898 ps
CPU time	11.92 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:53:23 PM PDT 24
Peak memory	217704 kb
Host	smart-cfe7736e-1307-42ff-8a8b-251c121e7e89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988420838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1988420838
Directory	/workspace/19.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_access.1500375361
Short name	T802
Test name
Test status
Simulation time	33043418 ps
CPU time	1.54 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:19 PM PDT 24
Peak memory	216664 kb
Host	smart-528194c1-9038-43da-921c-e535289d629e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500375361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1500375361
Directory	/workspace/19.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_errors.2214120381
Short name	T432
Test name
Test status
Simulation time	5277535540 ps
CPU time	38.83 seconds
Started	Apr 28 12:53:18 PM PDT 24
Finished	Apr 28 12:53:57 PM PDT 24
Peak memory	217860 kb
Host	smart-a1d246bc-851c-4849-8bba-2d55694177f7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214120381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e rrors.2214120381
Directory	/workspace/19.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3856109214
Short name	T840
Test name
Test status
Simulation time	2827342563 ps
CPU time	13.07 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:29 PM PDT 24
Peak memory	217884 kb
Host	smart-2e600505-e2d0-4a64-ac27-41e5adb4bdca
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856109214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_prog_failure.3856109214
Directory	/workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_smoke.3232147259
Short name	T84
Test name
Test status
Simulation time	177539278 ps
CPU time	1.69 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:19 PM PDT 24
Peak memory	212752 kb
Host	smart-1a142c7c-5d60-404e-8b44-10b1313d0b5c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232147259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke .3232147259
Directory	/workspace/19.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2884649888
Short name	T342
Test name
Test status
Simulation time	920736984 ps
CPU time	27.13 seconds
Started	Apr 28 12:53:12 PM PDT 24
Finished	Apr 28 12:53:40 PM PDT 24
Peak memory	250776 kb
Host	smart-890897b6-70f6-4d0f-b769-a235a2586f04
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884649888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt ag_state_failure.2884649888
Directory	/workspace/19.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1556473170
Short name	T822
Test name
Test status
Simulation time	2060813970 ps
CPU time	10.08 seconds
Started	Apr 28 12:53:11 PM PDT 24
Finished	Apr 28 12:53:22 PM PDT 24
Peak memory	222708 kb
Host	smart-e64226a1-26ba-4adf-93cb-eb6f5b9fc211
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556473170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_state_post_trans.1556473170
Directory	/workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_prog_failure.1465162108
Short name	T563
Test name
Test status
Simulation time	72998415 ps
CPU time	3.19 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:53:14 PM PDT 24
Peak memory	217916 kb
Host	smart-381ead87-4b61-4077-8bd7-1d8cedd5b69e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465162108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1465162108
Directory	/workspace/19.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_mubi.1716843716
Short name	T269
Test name
Test status
Simulation time	249718719 ps
CPU time	11.99 seconds
Started	Apr 28 12:53:17 PM PDT 24
Finished	Apr 28 12:53:29 PM PDT 24
Peak memory	225572 kb
Host	smart-d52d0622-5d2d-483b-8d17-05a7c00a16c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716843716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1716843716
Directory	/workspace/19.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_digest.1555625518
Short name	T351
Test name
Test status
Simulation time	1005065627 ps
CPU time	10.93 seconds
Started	Apr 28 12:53:15 PM PDT 24
Finished	Apr 28 12:53:26 PM PDT 24
Peak memory	217796 kb
Host	smart-6a5844ef-c502-400a-b663-cd1f9d6bcdfc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555625518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d igest.1555625518
Directory	/workspace/19.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_mux.4011953252
Short name	T519
Test name
Test status
Simulation time	893677714 ps
CPU time	9.82 seconds
Started	Apr 28 12:53:17 PM PDT 24
Finished	Apr 28 12:53:28 PM PDT 24
Peak memory	217844 kb
Host	smart-c2615b1f-c8da-407f-95a8-7d242c41d8fa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011953252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux. 4011953252
Directory	/workspace/19.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/19.lc_ctrl_security_escalation.2368291353
Short name	T226
Test name
Test status
Simulation time	5825233118 ps
CPU time	12.21 seconds
Started	Apr 28 12:53:13 PM PDT 24
Finished	Apr 28 12:53:25 PM PDT 24
Peak memory	226044 kb
Host	smart-60e57450-8d77-4618-92b3-3009eb5ddd3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368291353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2368291353
Directory	/workspace/19.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/19.lc_ctrl_smoke.2245293693
Short name	T683
Test name
Test status
Simulation time	39429468 ps
CPU time	2.02 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:19 PM PDT 24
Peak memory	213612 kb
Host	smart-50b7bfd2-3438-430b-88f1-22875c238169
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245293693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2245293693
Directory	/workspace/19.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_failure.3393984684
Short name	T757
Test name
Test status
Simulation time	219392170 ps
CPU time	31.04 seconds
Started	Apr 28 12:53:09 PM PDT 24
Finished	Apr 28 12:53:41 PM PDT 24
Peak memory	250796 kb
Host	smart-6ed4953c-cbcf-4137-9b93-fc04383d8e82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393984684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3393984684
Directory	/workspace/19.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_post_trans.3729836590
Short name	T800
Test name
Test status
Simulation time	81299037 ps
CPU time	6.33 seconds
Started	Apr 28 12:53:10 PM PDT 24
Finished	Apr 28 12:53:17 PM PDT 24
Peak memory	250300 kb
Host	smart-add23ef1-cd5d-4119-a4ba-80c6509b69fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729836590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3729836590
Directory	/workspace/19.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all.3354538022
Short name	T489
Test name
Test status
Simulation time	44397830273 ps
CPU time	241.92 seconds
Started	Apr 28 12:53:18 PM PDT 24
Finished	Apr 28 12:57:21 PM PDT 24
Peak memory	249796 kb
Host	smart-53256116-2444-471d-af36-e24ba0a6bb68
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354538022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.3354538022
Directory	/workspace/19.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1562624807
Short name	T862
Test name
Test status
Simulation time	13938318 ps
CPU time	0.81 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:18 PM PDT 24
Peak memory	208412 kb
Host	smart-430c331c-5d01-4e59-ae48-c90551db8607
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562624807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c trl_volatile_unlock_smoke.1562624807
Directory	/workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_alert_test.2030513560
Short name	T468
Test name
Test status
Simulation time	17410716 ps
CPU time	1.11 seconds
Started	Apr 28 12:52:06 PM PDT 24
Finished	Apr 28 12:52:08 PM PDT 24
Peak memory	209432 kb
Host	smart-21ae1be9-c5ba-41ef-86a5-18caa1073060
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030513560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2030513560
Directory	/workspace/2.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.lc_ctrl_claim_transition_if.150596439
Short name	T486
Test name
Test status
Simulation time	11728099 ps
CPU time	0.8 seconds
Started	Apr 28 12:52:05 PM PDT 24
Finished	Apr 28 12:52:07 PM PDT 24
Peak memory	209228 kb
Host	smart-aaf9d41f-e6a0-41e6-bff3-94d2954ed9ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=150596439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.150596439
Directory	/workspace/2.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/2.lc_ctrl_errors.2244397418
Short name	T571
Test name
Test status
Simulation time	972118790 ps
CPU time	8.85 seconds
Started	Apr 28 12:52:05 PM PDT 24
Finished	Apr 28 12:52:15 PM PDT 24
Peak memory	217764 kb
Host	smart-099f6d1e-80a9-4d0b-811b-bc636223a0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244397418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2244397418
Directory	/workspace/2.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_access.1150340816
Short name	T873
Test name
Test status
Simulation time	1627117080 ps
CPU time	6.09 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:16 PM PDT 24
Peak memory	217020 kb
Host	smart-81da6411-66d4-4180-a74c-8eeb51e6ac62
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150340816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1150340816
Directory	/workspace/2.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_errors.773947388
Short name	T690
Test name
Test status
Simulation time	11563553276 ps
CPU time	35.61 seconds
Started	Apr 28 12:52:14 PM PDT 24
Finished	Apr 28 12:52:51 PM PDT 24
Peak memory	218056 kb
Host	smart-8268f95e-f33b-4a0d-aa31-a7d1aa35bd98
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773947388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err ors.773947388
Directory	/workspace/2.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_priority.1857242950
Short name	T412
Test name
Test status
Simulation time	1403834615 ps
CPU time	9.29 seconds
Started	Apr 28 12:52:09 PM PDT 24
Finished	Apr 28 12:52:19 PM PDT 24
Peak memory	217624 kb
Host	smart-ea8ac2c2-bea8-4c9a-b388-56f6c9454e11
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857242950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1 857242950
Directory	/workspace/2.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3278382415
Short name	T6
Test name
Test status
Simulation time	2577009166 ps
CPU time	19.34 seconds
Started	Apr 28 12:52:08 PM PDT 24
Finished	Apr 28 12:52:28 PM PDT 24
Peak memory	217864 kb
Host	smart-a7fda121-0ac2-4dd0-8361-a6e7c4a845e1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278382415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _prog_failure.3278382415
Directory	/workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3400548788
Short name	T339
Test name
Test status
Simulation time	1291781924 ps
CPU time	37.11 seconds
Started	Apr 28 12:52:05 PM PDT 24
Finished	Apr 28 12:52:44 PM PDT 24
Peak memory	213236 kb
Host	smart-c2672766-b290-4dab-b0c6-5a16c8402626
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400548788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_regwen_during_op.3400548788
Directory	/workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_smoke.924616484
Short name	T830
Test name
Test status
Simulation time	3631271358 ps
CPU time	20.98 seconds
Started	Apr 28 12:52:05 PM PDT 24
Finished	Apr 28 12:52:26 PM PDT 24
Peak memory	214328 kb
Host	smart-b5d85260-0ef6-44f3-bcf2-e240625ce3ed
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924616484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.924616484
Directory	/workspace/2.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4202889271
Short name	T652
Test name
Test status
Simulation time	8339410304 ps
CPU time	130.12 seconds
Started	Apr 28 12:52:04 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	283600 kb
Host	smart-40e699cc-56b0-4c38-8771-8e710e95d028
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202889271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta g_state_failure.4202889271
Directory	/workspace/2.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3776723448
Short name	T720
Test name
Test status
Simulation time	515280186 ps
CPU time	13.63 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:24 PM PDT 24
Peak memory	250772 kb
Host	smart-b4bb17da-6502-4c87-b4b5-ef3cd20dced6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776723448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_state_post_trans.3776723448
Directory	/workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_prog_failure.611625828
Short name	T188
Test name
Test status
Simulation time	175383799 ps
CPU time	3.38 seconds
Started	Apr 28 12:52:06 PM PDT 24
Finished	Apr 28 12:52:11 PM PDT 24
Peak memory	217860 kb
Host	smart-a3730bf7-f7a6-4d25-9e66-92af5490660b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611625828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.611625828
Directory	/workspace/2.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_regwen_during_op.1601355790
Short name	T67
Test name
Test status
Simulation time	1140717219 ps
CPU time	18.46 seconds
Started	Apr 28 12:52:11 PM PDT 24
Finished	Apr 28 12:52:30 PM PDT 24
Peak memory	214236 kb
Host	smart-f54469a3-b3b6-4afb-9e73-c638abaa7f99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601355790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1601355790
Directory	/workspace/2.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_cm.376437275
Short name	T105
Test name
Test status
Simulation time	749946110 ps
CPU time	24.07 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:40 PM PDT 24
Peak memory	268732 kb
Host	smart-2121b7fb-4422-4d42-8712-d09af6308110
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376437275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.376437275
Directory	/workspace/2.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_mubi.1629802414
Short name	T347
Test name
Test status
Simulation time	758933264 ps
CPU time	16.71 seconds
Started	Apr 28 12:52:09 PM PDT 24
Finished	Apr 28 12:52:26 PM PDT 24
Peak memory	218740 kb
Host	smart-80318895-05bb-4b5a-8f1f-7e626787767f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629802414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1629802414
Directory	/workspace/2.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_digest.1700865829
Short name	T763
Test name
Test status
Simulation time	575581110 ps
CPU time	11.37 seconds
Started	Apr 28 12:52:09 PM PDT 24
Finished	Apr 28 12:52:21 PM PDT 24
Peak memory	217944 kb
Host	smart-420bc0c2-f7fc-4876-8179-3a544329461f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700865829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di gest.1700865829
Directory	/workspace/2.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_mux.2275227235
Short name	T843
Test name
Test status
Simulation time	3844238385 ps
CPU time	8.51 seconds
Started	Apr 28 12:52:07 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	217948 kb
Host	smart-65da8bad-40e4-4e92-b28b-0d4d0b717627
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275227235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2 275227235
Directory	/workspace/2.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/2.lc_ctrl_security_escalation.3621310420
Short name	T508
Test name
Test status
Simulation time	1753002068 ps
CPU time	9.33 seconds
Started	Apr 28 12:52:07 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	224924 kb
Host	smart-97fd3249-fca7-4896-9898-1fb096114cf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621310420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3621310420
Directory	/workspace/2.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/2.lc_ctrl_smoke.1288779118
Short name	T736
Test name
Test status
Simulation time	198280753 ps
CPU time	5.46 seconds
Started	Apr 28 12:52:07 PM PDT 24
Finished	Apr 28 12:52:13 PM PDT 24
Peak memory	217544 kb
Host	smart-6dea5666-619a-444b-b43a-1bc043775cdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1288779118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1288779118
Directory	/workspace/2.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_failure.1012849158
Short name	T676
Test name
Test status
Simulation time	260011782 ps
CPU time	33.53 seconds
Started	Apr 28 12:52:07 PM PDT 24
Finished	Apr 28 12:52:41 PM PDT 24
Peak memory	250776 kb
Host	smart-71c3e35c-87d8-4f83-a93a-ca1a7c6f9bfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012849158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1012849158
Directory	/workspace/2.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_post_trans.1561014717
Short name	T697
Test name
Test status
Simulation time	116131359 ps
CPU time	8.26 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:24 PM PDT 24
Peak memory	246772 kb
Host	smart-87fd1d9d-38ae-420f-acc3-6033ae720ad5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561014717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1561014717
Directory	/workspace/2.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_stress_all.3945437093
Short name	T742
Test name
Test status
Simulation time	19017554946 ps
CPU time	617.16 seconds
Started	Apr 28 12:52:06 PM PDT 24
Finished	Apr 28 01:02:24 PM PDT 24
Peak memory	277420 kb
Host	smart-dcd266ab-4d3f-4195-a79d-6958a827eaf5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945437093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.3945437093
Directory	/workspace/2.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.230265124
Short name	T21
Test name
Test status
Simulation time	47760816 ps
CPU time	1.14 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	212492 kb
Host	smart-5aa23ec3-3ecb-4c17-a867-e371b15a040c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230265124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr l_volatile_unlock_smoke.230265124
Directory	/workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_alert_test.889333815
Short name	T478
Test name
Test status
Simulation time	13905411 ps
CPU time	0.91 seconds
Started	Apr 28 12:53:17 PM PDT 24
Finished	Apr 28 12:53:19 PM PDT 24
Peak memory	209312 kb
Host	smart-c6471542-0ccb-4860-a2f9-fc6b9cc7f75c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889333815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.889333815
Directory	/workspace/20.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.lc_ctrl_errors.792268327
Short name	T792
Test name
Test status
Simulation time	906060461 ps
CPU time	10.83 seconds
Started	Apr 28 12:53:22 PM PDT 24
Finished	Apr 28 12:53:34 PM PDT 24
Peak memory	217832 kb
Host	smart-285b0e6d-5f66-46a8-836e-a0c2cc3fc132
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792268327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.792268327
Directory	/workspace/20.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/20.lc_ctrl_jtag_access.176310405
Short name	T326
Test name
Test status
Simulation time	648247690 ps
CPU time	5.62 seconds
Started	Apr 28 12:53:14 PM PDT 24
Finished	Apr 28 12:53:20 PM PDT 24
Peak memory	217040 kb
Host	smart-c766a24b-dfa8-4f49-bb63-0889b39551ae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176310405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.176310405
Directory	/workspace/20.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/20.lc_ctrl_prog_failure.1461913012
Short name	T485
Test name
Test status
Simulation time	27238129 ps
CPU time	1.75 seconds
Started	Apr 28 12:53:13 PM PDT 24
Finished	Apr 28 12:53:16 PM PDT 24
Peak memory	217804 kb
Host	smart-e5cff1a5-407b-4268-b499-da16df1519e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461913012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1461913012
Directory	/workspace/20.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_mubi.2741504627
Short name	T818
Test name
Test status
Simulation time	1205611524 ps
CPU time	15.62 seconds
Started	Apr 28 12:53:17 PM PDT 24
Finished	Apr 28 12:53:33 PM PDT 24
Peak memory	225912 kb
Host	smart-007f8bd2-e931-4db8-80d6-219a67ac0d87
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741504627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2741504627
Directory	/workspace/20.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_digest.920642096
Short name	T594
Test name
Test status
Simulation time	583097401 ps
CPU time	11.89 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:28 PM PDT 24
Peak memory	217808 kb
Host	smart-6ec0a533-a194-4df9-b56c-d02f36f2e23b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920642096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di gest.920642096
Directory	/workspace/20.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_mux.4145325616
Short name	T725
Test name
Test status
Simulation time	792189030 ps
CPU time	7.68 seconds
Started	Apr 28 12:53:17 PM PDT 24
Finished	Apr 28 12:53:25 PM PDT 24
Peak memory	217700 kb
Host	smart-19522bbf-69ff-45f6-8f54-50f1ae5b1d76
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145325616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux. 4145325616
Directory	/workspace/20.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/20.lc_ctrl_security_escalation.3232470052
Short name	T600
Test name
Test status
Simulation time	730874495 ps
CPU time	8.97 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:26 PM PDT 24
Peak memory	217820 kb
Host	smart-4c65bb82-9571-474f-a2e8-fda1f548e514
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232470052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3232470052
Directory	/workspace/20.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/20.lc_ctrl_smoke.3714000205
Short name	T65
Test name
Test status
Simulation time	25054500 ps
CPU time	1.25 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:18 PM PDT 24
Peak memory	213256 kb
Host	smart-a89af070-68af-411b-bbe8-b9c99e1c6179
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714000205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3714000205
Directory	/workspace/20.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_failure.3648869777
Short name	T296
Test name
Test status
Simulation time	236770072 ps
CPU time	29.12 seconds
Started	Apr 28 12:53:14 PM PDT 24
Finished	Apr 28 12:53:44 PM PDT 24
Peak memory	250776 kb
Host	smart-b29f2703-0dec-4e43-868a-689a17c8315b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648869777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3648869777
Directory	/workspace/20.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_post_trans.2067619027
Short name	T336
Test name
Test status
Simulation time	285598518 ps
CPU time	8.07 seconds
Started	Apr 28 12:53:18 PM PDT 24
Finished	Apr 28 12:53:26 PM PDT 24
Peak memory	250836 kb
Host	smart-1b922705-730f-4600-8c86-52d9ade0a988
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067619027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2067619027
Directory	/workspace/20.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all.4185923777
Short name	T71
Test name
Test status
Simulation time	2358844170 ps
CPU time	36.49 seconds
Started	Apr 28 12:53:18 PM PDT 24
Finished	Apr 28 12:53:55 PM PDT 24
Peak memory	245596 kb
Host	smart-697772da-3c84-4447-a1f0-203421ca1977
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185923777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.4185923777
Directory	/workspace/20.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2271062846
Short name	T37
Test name
Test status
Simulation time	48359588 ps
CPU time	0.79 seconds
Started	Apr 28 12:53:16 PM PDT 24
Finished	Apr 28 12:53:17 PM PDT 24
Peak memory	208420 kb
Host	smart-bd2220cc-2b11-41eb-9664-b8a969a5f803
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271062846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c trl_volatile_unlock_smoke.2271062846
Directory	/workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_alert_test.1346663606
Short name	T649
Test name
Test status
Simulation time	16019217 ps
CPU time	0.83 seconds
Started	Apr 28 12:53:21 PM PDT 24
Finished	Apr 28 12:53:22 PM PDT 24
Peak memory	209388 kb
Host	smart-aebfcc45-92a4-489f-ac59-b0f8478f6319
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346663606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1346663606
Directory	/workspace/21.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.lc_ctrl_errors.2504637477
Short name	T435
Test name
Test status
Simulation time	1412113587 ps
CPU time	12.04 seconds
Started	Apr 28 12:53:21 PM PDT 24
Finished	Apr 28 12:53:34 PM PDT 24
Peak memory	217724 kb
Host	smart-2d9eb67a-a28e-4238-8a6a-fec073df254b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504637477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2504637477
Directory	/workspace/21.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/21.lc_ctrl_jtag_access.1463776990
Short name	T770
Test name
Test status
Simulation time	1413094433 ps
CPU time	6.05 seconds
Started	Apr 28 12:53:20 PM PDT 24
Finished	Apr 28 12:53:27 PM PDT 24
Peak memory	209432 kb
Host	smart-95f5d17b-ec09-4341-bd9f-749ccb3f140f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463776990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1463776990
Directory	/workspace/21.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/21.lc_ctrl_prog_failure.3279609775
Short name	T640
Test name
Test status
Simulation time	34993272 ps
CPU time	1.61 seconds
Started	Apr 28 12:53:21 PM PDT 24
Finished	Apr 28 12:53:23 PM PDT 24
Peak memory	217848 kb
Host	smart-7fe70b4a-af4b-44eb-974e-4ad036c50c22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279609775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3279609775
Directory	/workspace/21.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_mubi.503022364
Short name	T645
Test name
Test status
Simulation time	1294955171 ps
CPU time	11.29 seconds
Started	Apr 28 12:53:26 PM PDT 24
Finished	Apr 28 12:53:38 PM PDT 24
Peak memory	225820 kb
Host	smart-048b9b5d-1b3f-4ef8-826c-4582d12f2ec3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503022364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.503022364
Directory	/workspace/21.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_digest.3729225949
Short name	T469
Test name
Test status
Simulation time	388789345 ps
CPU time	14.55 seconds
Started	Apr 28 12:53:25 PM PDT 24
Finished	Apr 28 12:53:40 PM PDT 24
Peak memory	217848 kb
Host	smart-77bd2a3b-5520-4ec1-afff-410afe6fe82a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729225949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d igest.3729225949
Directory	/workspace/21.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_mux.3724287147
Short name	T183
Test name
Test status
Simulation time	315287866 ps
CPU time	7.98 seconds
Started	Apr 28 12:53:19 PM PDT 24
Finished	Apr 28 12:53:28 PM PDT 24
Peak memory	217772 kb
Host	smart-9782a228-b22a-42b8-960f-949abe34dbe2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724287147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux. 3724287147
Directory	/workspace/21.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/21.lc_ctrl_security_escalation.3574850581
Short name	T512
Test name
Test status
Simulation time	734950267 ps
CPU time	13.78 seconds
Started	Apr 28 12:53:20 PM PDT 24
Finished	Apr 28 12:53:35 PM PDT 24
Peak memory	226008 kb
Host	smart-06881436-195c-49da-b47b-17814cdf96bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574850581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3574850581
Directory	/workspace/21.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/21.lc_ctrl_smoke.3994356301
Short name	T874
Test name
Test status
Simulation time	1237148913 ps
CPU time	3.43 seconds
Started	Apr 28 12:53:19 PM PDT 24
Finished	Apr 28 12:53:23 PM PDT 24
Peak memory	217592 kb
Host	smart-f53b3cb6-2e6d-4e31-8e30-6c00bee52af8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994356301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3994356301
Directory	/workspace/21.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_failure.1115652501
Short name	T391
Test name
Test status
Simulation time	1100674959 ps
CPU time	19.88 seconds
Started	Apr 28 12:53:24 PM PDT 24
Finished	Apr 28 12:53:44 PM PDT 24
Peak memory	249544 kb
Host	smart-70fa0cfc-1272-4023-a06e-cb72850b6700
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115652501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1115652501
Directory	/workspace/21.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_post_trans.2629259453
Short name	T876
Test name
Test status
Simulation time	199550918 ps
CPU time	7.9 seconds
Started	Apr 28 12:53:22 PM PDT 24
Finished	Apr 28 12:53:31 PM PDT 24
Peak memory	250868 kb
Host	smart-d2e16ae7-b588-4920-816f-7dd865ffaf25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629259453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2629259453
Directory	/workspace/21.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all.3348604611
Short name	T545
Test name
Test status
Simulation time	2427739750 ps
CPU time	65.88 seconds
Started	Apr 28 12:53:25 PM PDT 24
Finished	Apr 28 12:54:32 PM PDT 24
Peak memory	250944 kb
Host	smart-cc6a709c-e86c-44fe-9964-69bb010a1085
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348604611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.3348604611
Directory	/workspace/21.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2872547696
Short name	T620
Test name
Test status
Simulation time	18939866 ps
CPU time	0.77 seconds
Started	Apr 28 12:53:17 PM PDT 24
Finished	Apr 28 12:53:19 PM PDT 24
Peak memory	208412 kb
Host	smart-453e6571-a929-4324-a728-ffdbc37406a6
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872547696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c trl_volatile_unlock_smoke.2872547696
Directory	/workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_alert_test.3837517883
Short name	T557
Test name
Test status
Simulation time	14771065 ps
CPU time	1.07 seconds
Started	Apr 28 12:53:22 PM PDT 24
Finished	Apr 28 12:53:23 PM PDT 24
Peak memory	209436 kb
Host	smart-83f2a8d6-4649-44a4-a2c2-4a792cb8b04f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837517883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3837517883
Directory	/workspace/22.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.lc_ctrl_errors.2311666981
Short name	T677
Test name
Test status
Simulation time	2620813676 ps
CPU time	10.75 seconds
Started	Apr 28 12:53:24 PM PDT 24
Finished	Apr 28 12:53:35 PM PDT 24
Peak memory	217972 kb
Host	smart-236be8ca-4d6d-4e17-9540-aad0b803884c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311666981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2311666981
Directory	/workspace/22.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/22.lc_ctrl_jtag_access.1482012175
Short name	T859
Test name
Test status
Simulation time	7515493143 ps
CPU time	5.46 seconds
Started	Apr 28 12:53:20 PM PDT 24
Finished	Apr 28 12:53:27 PM PDT 24
Peak memory	217492 kb
Host	smart-1779fd82-ee01-463b-ba82-489a5a06e52d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482012175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1482012175
Directory	/workspace/22.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/22.lc_ctrl_prog_failure.87516987
Short name	T421
Test name
Test status
Simulation time	371594998 ps
CPU time	3.17 seconds
Started	Apr 28 12:53:21 PM PDT 24
Finished	Apr 28 12:53:24 PM PDT 24
Peak memory	217652 kb
Host	smart-62856a5d-e7c5-4db9-a594-c3532c81322e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87516987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.87516987
Directory	/workspace/22.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_mubi.199175220
Short name	T433
Test name
Test status
Simulation time	2238089443 ps
CPU time	13.77 seconds
Started	Apr 28 12:53:28 PM PDT 24
Finished	Apr 28 12:53:43 PM PDT 24
Peak memory	218788 kb
Host	smart-cd6935ed-6e4c-4a8c-be90-9a5d6962d986
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199175220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.199175220
Directory	/workspace/22.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_digest.4065218088
Short name	T3
Test name
Test status
Simulation time	1343822328 ps
CPU time	9.18 seconds
Started	Apr 28 12:53:22 PM PDT 24
Finished	Apr 28 12:53:32 PM PDT 24
Peak memory	217872 kb
Host	smart-f778f803-777d-4df6-9b42-2fba32c814b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065218088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d igest.4065218088
Directory	/workspace/22.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_mux.2905220280
Short name	T573
Test name
Test status
Simulation time	752068106 ps
CPU time	10.06 seconds
Started	Apr 28 12:53:20 PM PDT 24
Finished	Apr 28 12:53:31 PM PDT 24
Peak memory	217948 kb
Host	smart-6c9b5a6e-4d70-4fbe-9974-863497bbff2b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905220280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux. 2905220280
Directory	/workspace/22.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/22.lc_ctrl_security_escalation.2836536945
Short name	T267
Test name
Test status
Simulation time	2763256691 ps
CPU time	15.32 seconds
Started	Apr 28 12:53:21 PM PDT 24
Finished	Apr 28 12:53:37 PM PDT 24
Peak memory	225976 kb
Host	smart-16da4114-5cba-4be7-af05-f807aad29696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836536945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2836536945
Directory	/workspace/22.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/22.lc_ctrl_smoke.183822431
Short name	T860
Test name
Test status
Simulation time	64399446 ps
CPU time	1.37 seconds
Started	Apr 28 12:53:24 PM PDT 24
Finished	Apr 28 12:53:26 PM PDT 24
Peak memory	213460 kb
Host	smart-2cae4728-3f08-4033-956f-820bc9311994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183822431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.183822431
Directory	/workspace/22.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_failure.431247729
Short name	T294
Test name
Test status
Simulation time	1365391611 ps
CPU time	29.06 seconds
Started	Apr 28 12:53:20 PM PDT 24
Finished	Apr 28 12:53:50 PM PDT 24
Peak memory	250728 kb
Host	smart-9e9f2b16-2215-478a-82bd-f32bfe2102ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431247729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.431247729
Directory	/workspace/22.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_post_trans.1000003875
Short name	T352
Test name
Test status
Simulation time	133537218 ps
CPU time	6.93 seconds
Started	Apr 28 12:53:20 PM PDT 24
Finished	Apr 28 12:53:27 PM PDT 24
Peak memory	250832 kb
Host	smart-98d3513d-c21f-4d29-a7ce-21c534a2c3b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000003875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1000003875
Directory	/workspace/22.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all.4116048700
Short name	T506
Test name
Test status
Simulation time	3459850283 ps
CPU time	68.21 seconds
Started	Apr 28 12:53:20 PM PDT 24
Finished	Apr 28 12:54:29 PM PDT 24
Peak memory	246400 kb
Host	smart-c4831f9e-64fe-4d56-b84c-331c782c6203
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116048700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.4116048700
Directory	/workspace/22.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.462263991
Short name	T723
Test name
Test status
Simulation time	17913455471 ps
CPU time	338.5 seconds
Started	Apr 28 12:53:25 PM PDT 24
Finished	Apr 28 12:59:03 PM PDT 24
Peak memory	283696 kb
Host	smart-6f8efef8-a3d2-4e7d-87fb-e24a6ca52f65
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=462263991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.462263991
Directory	/workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.776675015
Short name	T437
Test name
Test status
Simulation time	51105312 ps
CPU time	0.88 seconds
Started	Apr 28 12:53:28 PM PDT 24
Finished	Apr 28 12:53:30 PM PDT 24
Peak memory	211392 kb
Host	smart-614d3f61-87e6-473e-8788-a2e4990b2db3
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776675015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct rl_volatile_unlock_smoke.776675015
Directory	/workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_alert_test.2970296550
Short name	T765
Test name
Test status
Simulation time	56000649 ps
CPU time	0.85 seconds
Started	Apr 28 12:53:26 PM PDT 24
Finished	Apr 28 12:53:28 PM PDT 24
Peak memory	209328 kb
Host	smart-48002332-a791-4cd9-86d7-2fde8f01503d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970296550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2970296550
Directory	/workspace/23.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.lc_ctrl_errors.1503358030
Short name	T448
Test name
Test status
Simulation time	2408366540 ps
CPU time	13.61 seconds
Started	Apr 28 12:53:20 PM PDT 24
Finished	Apr 28 12:53:34 PM PDT 24
Peak memory	226072 kb
Host	smart-a66726f6-9b94-4733-89d8-04cc2ccc11dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503358030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1503358030
Directory	/workspace/23.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/23.lc_ctrl_jtag_access.2916194898
Short name	T430
Test name
Test status
Simulation time	2644112526 ps
CPU time	15.73 seconds
Started	Apr 28 12:53:25 PM PDT 24
Finished	Apr 28 12:53:41 PM PDT 24
Peak memory	217540 kb
Host	smart-3e306ed0-3272-4a80-a7f6-187dcbd65e99
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916194898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2916194898
Directory	/workspace/23.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/23.lc_ctrl_prog_failure.1231685576
Short name	T745
Test name
Test status
Simulation time	91281617 ps
CPU time	4.48 seconds
Started	Apr 28 12:53:23 PM PDT 24
Finished	Apr 28 12:53:28 PM PDT 24
Peak memory	217904 kb
Host	smart-3a11d063-2f38-4081-a029-f3a135127f02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231685576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1231685576
Directory	/workspace/23.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_mubi.1953179752
Short name	T576
Test name
Test status
Simulation time	387894017 ps
CPU time	14.85 seconds
Started	Apr 28 12:53:28 PM PDT 24
Finished	Apr 28 12:53:43 PM PDT 24
Peak memory	218748 kb
Host	smart-9fb5ff65-a157-40a3-8853-d6025e5546f0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953179752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1953179752
Directory	/workspace/23.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_digest.1428235920
Short name	T397
Test name
Test status
Simulation time	416142474 ps
CPU time	14.1 seconds
Started	Apr 28 12:53:28 PM PDT 24
Finished	Apr 28 12:53:43 PM PDT 24
Peak memory	217752 kb
Host	smart-f0558217-04a4-43ed-985f-c24b108ffd88
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428235920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d igest.1428235920
Directory	/workspace/23.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_mux.1539803714
Short name	T453
Test name
Test status
Simulation time	543324338 ps
CPU time	9.07 seconds
Started	Apr 28 12:53:26 PM PDT 24
Finished	Apr 28 12:53:36 PM PDT 24
Peak memory	217764 kb
Host	smart-637f2194-ad2f-4b76-af2c-66bcd48bd84a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539803714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux. 1539803714
Directory	/workspace/23.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/23.lc_ctrl_security_escalation.1820330997
Short name	T475
Test name
Test status
Simulation time	398685948 ps
CPU time	14.39 seconds
Started	Apr 28 12:53:27 PM PDT 24
Finished	Apr 28 12:53:42 PM PDT 24
Peak memory	217828 kb
Host	smart-e8990048-4329-4212-b2dd-35691e24720a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820330997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1820330997
Directory	/workspace/23.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_failure.1994512317
Short name	T831
Test name
Test status
Simulation time	467413607 ps
CPU time	18.9 seconds
Started	Apr 28 12:53:27 PM PDT 24
Finished	Apr 28 12:53:47 PM PDT 24
Peak memory	248432 kb
Host	smart-9d13d266-d687-4597-bd06-df61132a78a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994512317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1994512317
Directory	/workspace/23.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_post_trans.2300774815
Short name	T395
Test name
Test status
Simulation time	89269609 ps
CPU time	6.15 seconds
Started	Apr 28 12:53:21 PM PDT 24
Finished	Apr 28 12:53:27 PM PDT 24
Peak memory	242604 kb
Host	smart-124d576a-2dd9-4bd1-bbf4-ece0c72de123
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300774815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2300774815
Directory	/workspace/23.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all.603175326
Short name	T60
Test name
Test status
Simulation time	4168665447 ps
CPU time	161.64 seconds
Started	Apr 28 12:53:27 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	283464 kb
Host	smart-8d915350-632e-4f72-9880-f62334d4ca74
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603175326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.603175326
Directory	/workspace/23.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1146702397
Short name	T372
Test name
Test status
Simulation time	41040116 ps
CPU time	0.93 seconds
Started	Apr 28 12:53:28 PM PDT 24
Finished	Apr 28 12:53:30 PM PDT 24
Peak memory	211508 kb
Host	smart-148ec65f-a350-4488-8c6e-b8b1234a752f
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146702397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c trl_volatile_unlock_smoke.1146702397
Directory	/workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_alert_test.1602077864
Short name	T681
Test name
Test status
Simulation time	36766418 ps
CPU time	1.16 seconds
Started	Apr 28 12:53:31 PM PDT 24
Finished	Apr 28 12:53:33 PM PDT 24
Peak memory	209392 kb
Host	smart-577f28db-baec-43bb-a47c-1949136a84a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602077864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1602077864
Directory	/workspace/24.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.lc_ctrl_errors.3166963680
Short name	T708
Test name
Test status
Simulation time	262388678 ps
CPU time	11.8 seconds
Started	Apr 28 12:53:27 PM PDT 24
Finished	Apr 28 12:53:40 PM PDT 24
Peak memory	217792 kb
Host	smart-a5b0bd6b-995f-43d2-a540-c36d0225e2ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166963680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3166963680
Directory	/workspace/24.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/24.lc_ctrl_jtag_access.396441330
Short name	T551
Test name
Test status
Simulation time	379547963 ps
CPU time	9.72 seconds
Started	Apr 28 12:53:26 PM PDT 24
Finished	Apr 28 12:53:37 PM PDT 24
Peak memory	209424 kb
Host	smart-3891b971-0dc6-4005-9532-c0b6339ae0b5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396441330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.396441330
Directory	/workspace/24.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/24.lc_ctrl_prog_failure.4119436016
Short name	T820
Test name
Test status
Simulation time	62223437 ps
CPU time	2.39 seconds
Started	Apr 28 12:53:26 PM PDT 24
Finished	Apr 28 12:53:29 PM PDT 24
Peak memory	217772 kb
Host	smart-1aba6e8c-9859-4d23-a3a8-6725e138d65d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119436016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.4119436016
Directory	/workspace/24.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_mubi.1503897688
Short name	T282
Test name
Test status
Simulation time	1039553042 ps
CPU time	11.41 seconds
Started	Apr 28 12:53:26 PM PDT 24
Finished	Apr 28 12:53:38 PM PDT 24
Peak memory	225940 kb
Host	smart-1f930aee-d7be-4beb-a02e-ead557da66a3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503897688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1503897688
Directory	/workspace/24.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_digest.499602797
Short name	T237
Test name
Test status
Simulation time	1006034365 ps
CPU time	11.81 seconds
Started	Apr 28 12:53:26 PM PDT 24
Finished	Apr 28 12:53:39 PM PDT 24
Peak memory	217820 kb
Host	smart-06daf655-07c4-4ac8-8c44-950ab5f05dee
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499602797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di gest.499602797
Directory	/workspace/24.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_mux.1467878138
Short name	T378
Test name
Test status
Simulation time	1339706568 ps
CPU time	8.38 seconds
Started	Apr 28 12:53:28 PM PDT 24
Finished	Apr 28 12:53:37 PM PDT 24
Peak memory	217848 kb
Host	smart-c5a7a238-afd5-47a6-9e58-55500b40572b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467878138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux. 1467878138
Directory	/workspace/24.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/24.lc_ctrl_security_escalation.1927325884
Short name	T527
Test name
Test status
Simulation time	1221024575 ps
CPU time	11.16 seconds
Started	Apr 28 12:53:27 PM PDT 24
Finished	Apr 28 12:53:39 PM PDT 24
Peak memory	225872 kb
Host	smart-c9989ee9-0eed-499f-8901-32d556150d38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927325884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1927325884
Directory	/workspace/24.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/24.lc_ctrl_smoke.257942250
Short name	T61
Test name
Test status
Simulation time	30753370 ps
CPU time	2.22 seconds
Started	Apr 28 12:53:28 PM PDT 24
Finished	Apr 28 12:53:31 PM PDT 24
Peak memory	213952 kb
Host	smart-818438ff-b868-4d75-b1e6-1197f9e4482c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257942250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.257942250
Directory	/workspace/24.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_failure.1967378033
Short name	T659
Test name
Test status
Simulation time	371522999 ps
CPU time	17.71 seconds
Started	Apr 28 12:53:29 PM PDT 24
Finished	Apr 28 12:53:47 PM PDT 24
Peak memory	250800 kb
Host	smart-8de39995-2e1e-4581-997c-8b8f7a4001f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967378033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1967378033
Directory	/workspace/24.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_post_trans.1609950564
Short name	T496
Test name
Test status
Simulation time	136776680 ps
CPU time	3.42 seconds
Started	Apr 28 12:53:25 PM PDT 24
Finished	Apr 28 12:53:29 PM PDT 24
Peak memory	220944 kb
Host	smart-2aba4c4a-3bdf-40c5-8232-b655bb2670d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609950564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1609950564
Directory	/workspace/24.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all.1551125528
Short name	T4
Test name
Test status
Simulation time	11168552305 ps
CPU time	346.78 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:59:23 PM PDT 24
Peak memory	283600 kb
Host	smart-942592ed-593e-4ad8-b340-153b5b2eebde
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551125528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all.1551125528
Directory	/workspace/24.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2357589097
Short name	T535
Test name
Test status
Simulation time	16081384 ps
CPU time	1.01 seconds
Started	Apr 28 12:53:26 PM PDT 24
Finished	Apr 28 12:53:27 PM PDT 24
Peak memory	208516 kb
Host	smart-113113d4-ef50-439e-bc01-3656e21193b5
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357589097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c trl_volatile_unlock_smoke.2357589097
Directory	/workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_errors.2656324220
Short name	T313
Test name
Test status
Simulation time	543058470 ps
CPU time	23.8 seconds
Started	Apr 28 12:53:31 PM PDT 24
Finished	Apr 28 12:53:55 PM PDT 24
Peak memory	217756 kb
Host	smart-27a5c651-4dfe-42b1-a0e8-9e3fd2c10426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656324220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2656324220
Directory	/workspace/25.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/25.lc_ctrl_jtag_access.2000890731
Short name	T293
Test name
Test status
Simulation time	159851183 ps
CPU time	1.59 seconds
Started	Apr 28 12:53:34 PM PDT 24
Finished	Apr 28 12:53:36 PM PDT 24
Peak memory	216712 kb
Host	smart-73f25219-427e-4a94-b4aa-c43e852fc202
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000890731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2000890731
Directory	/workspace/25.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/25.lc_ctrl_prog_failure.671128790
Short name	T598
Test name
Test status
Simulation time	86252980 ps
CPU time	2.71 seconds
Started	Apr 28 12:53:30 PM PDT 24
Finished	Apr 28 12:53:34 PM PDT 24
Peak memory	217916 kb
Host	smart-e89732fa-743e-4387-8c06-552f8a21afa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671128790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.671128790
Directory	/workspace/25.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_mubi.1681480075
Short name	T446
Test name
Test status
Simulation time	619528437 ps
CPU time	15.97 seconds
Started	Apr 28 12:53:35 PM PDT 24
Finished	Apr 28 12:53:52 PM PDT 24
Peak memory	225876 kb
Host	smart-f7e24b56-b883-4ca3-8880-1315b986324b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681480075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1681480075
Directory	/workspace/25.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_digest.1988452215
Short name	T842
Test name
Test status
Simulation time	3056469884 ps
CPU time	9.46 seconds
Started	Apr 28 12:53:33 PM PDT 24
Finished	Apr 28 12:53:43 PM PDT 24
Peak memory	217792 kb
Host	smart-25403905-3416-47c7-baf2-8ad9240dc8b8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988452215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d igest.1988452215
Directory	/workspace/25.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_mux.2202127633
Short name	T523
Test name
Test status
Simulation time	2086608947 ps
CPU time	8.22 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:53:45 PM PDT 24
Peak memory	217716 kb
Host	smart-193edef4-f716-4883-abde-0e0851219291
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202127633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux. 2202127633
Directory	/workspace/25.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/25.lc_ctrl_security_escalation.954090598
Short name	T300
Test name
Test status
Simulation time	302570325 ps
CPU time	7.7 seconds
Started	Apr 28 12:53:34 PM PDT 24
Finished	Apr 28 12:53:42 PM PDT 24
Peak memory	224704 kb
Host	smart-bb208a09-1ca9-4c3e-9b75-ff602919ad30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954090598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.954090598
Directory	/workspace/25.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/25.lc_ctrl_smoke.3248865856
Short name	T616
Test name
Test status
Simulation time	353662150 ps
CPU time	3.01 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 12:53:43 PM PDT 24
Peak memory	214160 kb
Host	smart-2848eecd-236e-4287-9ba9-093641c1b637
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248865856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3248865856
Directory	/workspace/25.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_failure.166645041
Short name	T35
Test name
Test status
Simulation time	494423776 ps
CPU time	34.88 seconds
Started	Apr 28 12:53:34 PM PDT 24
Finished	Apr 28 12:54:10 PM PDT 24
Peak memory	248884 kb
Host	smart-49febf36-9754-448d-9747-98284ab80c62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=166645041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.166645041
Directory	/workspace/25.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_post_trans.761558178
Short name	T273
Test name
Test status
Simulation time	63329258 ps
CPU time	2.91 seconds
Started	Apr 28 12:53:35 PM PDT 24
Finished	Apr 28 12:53:39 PM PDT 24
Peak memory	222264 kb
Host	smart-480b92a3-2e87-41eb-b8b8-734b3a955fc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761558178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.761558178
Directory	/workspace/25.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all.129557934
Short name	T799
Test name
Test status
Simulation time	1910661022 ps
CPU time	43.28 seconds
Started	Apr 28 12:53:34 PM PDT 24
Finished	Apr 28 12:54:18 PM PDT 24
Peak memory	249864 kb
Host	smart-d8de159b-8292-4ad1-b3c1-72a3aa0361a8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129557934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.129557934
Directory	/workspace/25.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3651682069
Short name	T315
Test name
Test status
Simulation time	123896649 ps
CPU time	0.77 seconds
Started	Apr 28 12:53:37 PM PDT 24
Finished	Apr 28 12:53:38 PM PDT 24
Peak memory	208552 kb
Host	smart-dcaee664-0e43-44c8-9bc8-cecc9f17bb57
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651682069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c trl_volatile_unlock_smoke.3651682069
Directory	/workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_alert_test.1229785015
Short name	T97
Test name
Test status
Simulation time	14742542 ps
CPU time	0.84 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 12:53:40 PM PDT 24
Peak memory	209360 kb
Host	smart-1b700eea-0be9-4834-84a3-6d6fe98b8b1c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229785015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1229785015
Directory	/workspace/26.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.lc_ctrl_errors.1399310723
Short name	T597
Test name
Test status
Simulation time	1180602847 ps
CPU time	11.38 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:53:49 PM PDT 24
Peak memory	217672 kb
Host	smart-e22c4a9a-82a6-4d2c-bea2-16955dc75f96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399310723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1399310723
Directory	/workspace/26.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/26.lc_ctrl_jtag_access.3436800879
Short name	T588
Test name
Test status
Simulation time	586290003 ps
CPU time	3.89 seconds
Started	Apr 28 12:53:37 PM PDT 24
Finished	Apr 28 12:53:42 PM PDT 24
Peak memory	209316 kb
Host	smart-c4488559-9317-44fa-965b-d488aaa889fe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436800879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3436800879
Directory	/workspace/26.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/26.lc_ctrl_prog_failure.2916380251
Short name	T383
Test name
Test status
Simulation time	174151242 ps
CPU time	2.54 seconds
Started	Apr 28 12:53:35 PM PDT 24
Finished	Apr 28 12:53:38 PM PDT 24
Peak memory	217840 kb
Host	smart-b3f49cf5-57ac-4c4f-a19f-75628d363653
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916380251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2916380251
Directory	/workspace/26.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_mubi.2381019360
Short name	T158
Test name
Test status
Simulation time	1448315769 ps
CPU time	12.96 seconds
Started	Apr 28 12:53:33 PM PDT 24
Finished	Apr 28 12:53:47 PM PDT 24
Peak memory	218736 kb
Host	smart-ff79232c-2f36-4201-931b-6fff6b091d42
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381019360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2381019360
Directory	/workspace/26.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_digest.3998642392
Short name	T615
Test name
Test status
Simulation time	1623275698 ps
CPU time	20.36 seconds
Started	Apr 28 12:53:37 PM PDT 24
Finished	Apr 28 12:53:58 PM PDT 24
Peak memory	217876 kb
Host	smart-5283f056-8d98-41b0-8c07-dc8a6cb1318c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998642392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d igest.3998642392
Directory	/workspace/26.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_mux.1956772304
Short name	T366
Test name
Test status
Simulation time	370061922 ps
CPU time	7.94 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:53:45 PM PDT 24
Peak memory	217792 kb
Host	smart-2d5ffde1-0acf-4cf7-94ad-3e838b8624c3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956772304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux. 1956772304
Directory	/workspace/26.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/26.lc_ctrl_security_escalation.398405156
Short name	T627
Test name
Test status
Simulation time	836819505 ps
CPU time	15.06 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:53:51 PM PDT 24
Peak memory	217852 kb
Host	smart-86c77a9b-efeb-4b70-9aef-04a1cfb9cd95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398405156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.398405156
Directory	/workspace/26.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/26.lc_ctrl_smoke.1504854817
Short name	T804
Test name
Test status
Simulation time	44369522 ps
CPU time	2.07 seconds
Started	Apr 28 12:53:35 PM PDT 24
Finished	Apr 28 12:53:38 PM PDT 24
Peak memory	213952 kb
Host	smart-67f2cec8-c3e4-4998-b4d5-080f92f18785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504854817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1504854817
Directory	/workspace/26.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_failure.3962994697
Short name	T693
Test name
Test status
Simulation time	188001517 ps
CPU time	27.91 seconds
Started	Apr 28 12:53:30 PM PDT 24
Finished	Apr 28 12:53:59 PM PDT 24
Peak memory	250776 kb
Host	smart-a2955780-6e14-458d-8809-ec47f2f82c7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962994697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3962994697
Directory	/workspace/26.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_post_trans.2441947896
Short name	T680
Test name
Test status
Simulation time	214271779 ps
CPU time	6.91 seconds
Started	Apr 28 12:53:35 PM PDT 24
Finished	Apr 28 12:53:42 PM PDT 24
Peak memory	250708 kb
Host	smart-4b84c44f-28ff-4994-af6f-70f0c97df389
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441947896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2441947896
Directory	/workspace/26.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all.1012203644
Short name	T867
Test name
Test status
Simulation time	19234929119 ps
CPU time	157.23 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	273680 kb
Host	smart-dd4b58ce-a7cb-493b-b240-2cc9674b161e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012203644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all.1012203644
Directory	/workspace/26.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2716283318
Short name	T85
Test name
Test status
Simulation time	75292053158 ps
CPU time	775.35 seconds
Started	Apr 28 12:53:43 PM PDT 24
Finished	Apr 28 01:06:39 PM PDT 24
Peak memory	513132 kb
Host	smart-cb0bc419-47c4-40db-aaa7-1b5ddbfaf383
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2716283318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2716283318
Directory	/workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2626541825
Short name	T841
Test name
Test status
Simulation time	43000498 ps
CPU time	1.05 seconds
Started	Apr 28 12:53:34 PM PDT 24
Finished	Apr 28 12:53:35 PM PDT 24
Peak memory	211452 kb
Host	smart-55244eed-020e-4501-a610-5642e782e76a
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626541825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c trl_volatile_unlock_smoke.2626541825
Directory	/workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_alert_test.785790691
Short name	T310
Test name
Test status
Simulation time	33471700 ps
CPU time	0.91 seconds
Started	Apr 28 12:53:41 PM PDT 24
Finished	Apr 28 12:53:43 PM PDT 24
Peak memory	209360 kb
Host	smart-3d971bb7-6f82-44c1-af5c-af0d08621ef1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785790691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.785790691
Directory	/workspace/27.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.lc_ctrl_errors.2087753131
Short name	T817
Test name
Test status
Simulation time	766098697 ps
CPU time	15.92 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:53:52 PM PDT 24
Peak memory	217856 kb
Host	smart-bcc86ab0-17f0-454e-a7ca-cae3f9a11ebb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087753131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2087753131
Directory	/workspace/27.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/27.lc_ctrl_jtag_access.2764598695
Short name	T609
Test name
Test status
Simulation time	5645598039 ps
CPU time	5.71 seconds
Started	Apr 28 12:53:38 PM PDT 24
Finished	Apr 28 12:53:44 PM PDT 24
Peak memory	209596 kb
Host	smart-a7779f91-40ac-4ba9-a439-f14ffdf4bd1a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764598695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2764598695
Directory	/workspace/27.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/27.lc_ctrl_prog_failure.3980369541
Short name	T595
Test name
Test status
Simulation time	727505023 ps
CPU time	2.96 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 12:53:42 PM PDT 24
Peak memory	217736 kb
Host	smart-31880d89-eba8-4b81-a8ba-ed98767e6e20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980369541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3980369541
Directory	/workspace/27.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_mubi.3425590555
Short name	T687
Test name
Test status
Simulation time	6804664230 ps
CPU time	16.95 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 12:53:57 PM PDT 24
Peak memory	225964 kb
Host	smart-6585c303-f275-4ad0-bedd-1c2f0be225ed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425590555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3425590555
Directory	/workspace/27.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_digest.899003764
Short name	T441
Test name
Test status
Simulation time	1728238174 ps
CPU time	11.09 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:53:48 PM PDT 24
Peak memory	217848 kb
Host	smart-60aa43f2-1956-4a0a-8b18-64f995f2465c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899003764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di gest.899003764
Directory	/workspace/27.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_mux.365576384
Short name	T498
Test name
Test status
Simulation time	1064764071 ps
CPU time	9.62 seconds
Started	Apr 28 12:53:38 PM PDT 24
Finished	Apr 28 12:53:48 PM PDT 24
Peak memory	217832 kb
Host	smart-9d88f086-4d7c-4b4c-aaba-690b600836a9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365576384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.365576384
Directory	/workspace/27.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/27.lc_ctrl_security_escalation.1600931022
Short name	T179
Test name
Test status
Simulation time	848520573 ps
CPU time	8.4 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 12:53:48 PM PDT 24
Peak memory	217880 kb
Host	smart-d479a7a4-d383-4778-b79f-2e37451e40f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600931022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1600931022
Directory	/workspace/27.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/27.lc_ctrl_smoke.2330905947
Short name	T79
Test name
Test status
Simulation time	144745061 ps
CPU time	1.87 seconds
Started	Apr 28 12:53:37 PM PDT 24
Finished	Apr 28 12:53:39 PM PDT 24
Peak memory	213836 kb
Host	smart-2c8adbc3-292a-4dad-be53-66b3c6e881e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330905947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2330905947
Directory	/workspace/27.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_failure.3326816704
Short name	T447
Test name
Test status
Simulation time	228912640 ps
CPU time	22.36 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 12:54:02 PM PDT 24
Peak memory	250704 kb
Host	smart-2daf0f46-c867-4a5e-a2be-1c04d952870d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326816704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3326816704
Directory	/workspace/27.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_post_trans.2826698811
Short name	T520
Test name
Test status
Simulation time	306021676 ps
CPU time	7.12 seconds
Started	Apr 28 12:53:38 PM PDT 24
Finished	Apr 28 12:53:46 PM PDT 24
Peak memory	250732 kb
Host	smart-fa186a02-3621-4a93-9f20-f47de77e8c1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826698811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2826698811
Directory	/workspace/27.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all.49296591
Short name	T385
Test name
Test status
Simulation time	4771113402 ps
CPU time	48.18 seconds
Started	Apr 28 12:53:36 PM PDT 24
Finished	Apr 28 12:54:25 PM PDT 24
Peak memory	250644 kb
Host	smart-dd02f3bd-f48c-406a-ae87-9833705d2504
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49296591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.lc_ctrl_stress_all.49296591
Directory	/workspace/27.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3419652816
Short name	T829
Test name
Test status
Simulation time	16316483 ps
CPU time	0.97 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 12:53:40 PM PDT 24
Peak memory	211500 kb
Host	smart-d69f2c65-ed48-454b-8110-57cc3c214b95
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419652816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c trl_volatile_unlock_smoke.3419652816
Directory	/workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_alert_test.573264141
Short name	T425
Test name
Test status
Simulation time	12746195 ps
CPU time	1 seconds
Started	Apr 28 12:53:42 PM PDT 24
Finished	Apr 28 12:53:43 PM PDT 24
Peak memory	209404 kb
Host	smart-fd6e9a84-acf5-4a6d-96ec-1baacd3ef4d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573264141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.573264141
Directory	/workspace/28.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.lc_ctrl_errors.3965225083
Short name	T458
Test name
Test status
Simulation time	268523508 ps
CPU time	13.15 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:54:01 PM PDT 24
Peak memory	217792 kb
Host	smart-61582baf-d6bc-48c1-a602-dd6c31f39aec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965225083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3965225083
Directory	/workspace/28.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/28.lc_ctrl_jtag_access.1086031944
Short name	T584
Test name
Test status
Simulation time	696795274 ps
CPU time	5.03 seconds
Started	Apr 28 12:53:43 PM PDT 24
Finished	Apr 28 12:53:48 PM PDT 24
Peak memory	217216 kb
Host	smart-44d07ace-dc8c-4015-a49b-887b8a7842d0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086031944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1086031944
Directory	/workspace/28.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/28.lc_ctrl_prog_failure.1312638844
Short name	T308
Test name
Test status
Simulation time	135396723 ps
CPU time	1.83 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:53:50 PM PDT 24
Peak memory	217916 kb
Host	smart-b5802af2-b0ef-4b6b-b516-d459d36a8825
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312638844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1312638844
Directory	/workspace/28.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_mubi.1209066077
Short name	T262
Test name
Test status
Simulation time	337442869 ps
CPU time	12.31 seconds
Started	Apr 28 12:53:42 PM PDT 24
Finished	Apr 28 12:53:55 PM PDT 24
Peak memory	225880 kb
Host	smart-c2a1e339-5864-412a-8686-8ba9741715c3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209066077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1209066077
Directory	/workspace/28.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_digest.2097432341
Short name	T718
Test name
Test status
Simulation time	2901653960 ps
CPU time	18.58 seconds
Started	Apr 28 12:53:41 PM PDT 24
Finished	Apr 28 12:53:59 PM PDT 24
Peak memory	218160 kb
Host	smart-698edc0a-4984-418c-8ac6-0b34cfcff09a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097432341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d igest.2097432341
Directory	/workspace/28.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_mux.1811830438
Short name	T744
Test name
Test status
Simulation time	342946366 ps
CPU time	11.9 seconds
Started	Apr 28 12:53:46 PM PDT 24
Finished	Apr 28 12:53:59 PM PDT 24
Peak memory	217880 kb
Host	smart-f6d225b6-72ab-4f30-abdb-fc14ac5f28eb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811830438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux. 1811830438
Directory	/workspace/28.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/28.lc_ctrl_security_escalation.4029674586
Short name	T741
Test name
Test status
Simulation time	401708678 ps
CPU time	10.47 seconds
Started	Apr 28 12:53:41 PM PDT 24
Finished	Apr 28 12:53:52 PM PDT 24
Peak memory	224524 kb
Host	smart-e376d0d6-553d-4c3f-9c93-0c864fffe4f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029674586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4029674586
Directory	/workspace/28.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/28.lc_ctrl_smoke.482743682
Short name	T505
Test name
Test status
Simulation time	180756066 ps
CPU time	3.41 seconds
Started	Apr 28 12:53:40 PM PDT 24
Finished	Apr 28 12:53:44 PM PDT 24
Peak memory	214376 kb
Host	smart-d2ad7fba-b075-42cd-9ef1-ca97edbba898
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482743682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.482743682
Directory	/workspace/28.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_failure.857215461
Short name	T776
Test name
Test status
Simulation time	1057698440 ps
CPU time	24.37 seconds
Started	Apr 28 12:53:41 PM PDT 24
Finished	Apr 28 12:54:06 PM PDT 24
Peak memory	250664 kb
Host	smart-2d08b19c-c2d9-4a20-9e5e-2c30218a70d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857215461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.857215461
Directory	/workspace/28.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_post_trans.4257045468
Short name	T618
Test name
Test status
Simulation time	102382974 ps
CPU time	6.84 seconds
Started	Apr 28 12:53:41 PM PDT 24
Finished	Apr 28 12:53:48 PM PDT 24
Peak memory	246780 kb
Host	smart-27a50f04-71e7-4ba3-ab4d-a9054243511a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257045468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4257045468
Directory	/workspace/28.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all.1402956602
Short name	T291
Test name
Test status
Simulation time	1964824684 ps
CPU time	56.62 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:54:45 PM PDT 24
Peak memory	219820 kb
Host	smart-cdd35aed-f093-45b8-9357-d435b958dd96
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402956602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.1402956602
Directory	/workspace/28.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1163697524
Short name	T93
Test name
Test status
Simulation time	62283466200 ps
CPU time	445.29 seconds
Started	Apr 28 12:53:39 PM PDT 24
Finished	Apr 28 01:01:05 PM PDT 24
Peak memory	311160 kb
Host	smart-601d8582-5bb2-493b-a72e-9dbe11d1cee8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1163697524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1163697524
Directory	/workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2774626375
Short name	T851
Test name
Test status
Simulation time	24890610 ps
CPU time	0.98 seconds
Started	Apr 28 12:53:40 PM PDT 24
Finished	Apr 28 12:53:41 PM PDT 24
Peak memory	208456 kb
Host	smart-2f12d230-791e-4ae3-a8cf-12f559ac4362
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774626375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c trl_volatile_unlock_smoke.2774626375
Directory	/workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_alert_test.591957417
Short name	T450
Test name
Test status
Simulation time	21874805 ps
CPU time	0.94 seconds
Started	Apr 28 12:53:46 PM PDT 24
Finished	Apr 28 12:53:48 PM PDT 24
Peak memory	209364 kb
Host	smart-187306f9-79eb-4c18-83a7-ff04e48c70ae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591957417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.591957417
Directory	/workspace/29.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.lc_ctrl_errors.1263156305
Short name	T733
Test name
Test status
Simulation time	242409163 ps
CPU time	8.02 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:53:57 PM PDT 24
Peak memory	217848 kb
Host	smart-c41b09cf-9532-4be2-9e9c-9eb012faff12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263156305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1263156305
Directory	/workspace/29.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/29.lc_ctrl_jtag_access.167879478
Short name	T868
Test name
Test status
Simulation time	454309888 ps
CPU time	3.46 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:53:51 PM PDT 24
Peak memory	216720 kb
Host	smart-95bbc5ae-124a-40e5-9284-b261f5ff92b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167879478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.167879478
Directory	/workspace/29.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/29.lc_ctrl_prog_failure.662627920
Short name	T192
Test name
Test status
Simulation time	226332457 ps
CPU time	2.58 seconds
Started	Apr 28 12:53:41 PM PDT 24
Finished	Apr 28 12:53:44 PM PDT 24
Peak memory	217844 kb
Host	smart-eac0205b-7292-4bb6-b0ff-17559af1e619
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662627920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.662627920
Directory	/workspace/29.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_mubi.3214778008
Short name	T575
Test name
Test status
Simulation time	1056250818 ps
CPU time	12.94 seconds
Started	Apr 28 12:53:46 PM PDT 24
Finished	Apr 28 12:54:00 PM PDT 24
Peak memory	225976 kb
Host	smart-825b6279-ef95-4a4d-85f9-7167ec24a6c7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214778008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3214778008
Directory	/workspace/29.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_digest.257164836
Short name	T235
Test name
Test status
Simulation time	1284888357 ps
CPU time	10.16 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:53:58 PM PDT 24
Peak memory	217780 kb
Host	smart-c6c3c9e9-1671-4dab-85e0-405ba82205dd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257164836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di gest.257164836
Directory	/workspace/29.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_mux.3513828679
Short name	T62
Test name
Test status
Simulation time	534052580 ps
CPU time	7.81 seconds
Started	Apr 28 12:53:42 PM PDT 24
Finished	Apr 28 12:53:50 PM PDT 24
Peak memory	217756 kb
Host	smart-bbaa5f4c-3acc-4b61-9b75-8e517a09709f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513828679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux. 3513828679
Directory	/workspace/29.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/29.lc_ctrl_security_escalation.2630771738
Short name	T349
Test name
Test status
Simulation time	747349598 ps
CPU time	12.31 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:54:00 PM PDT 24
Peak memory	217840 kb
Host	smart-1e9da667-3c51-483d-aab4-c84aad40d269
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630771738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2630771738
Directory	/workspace/29.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/29.lc_ctrl_smoke.2663432824
Short name	T775
Test name
Test status
Simulation time	21827765 ps
CPU time	1.12 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:53:49 PM PDT 24
Peak memory	217644 kb
Host	smart-16102619-7760-47fb-8b12-b1f14b88af0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663432824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2663432824
Directory	/workspace/29.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_failure.3390805933
Short name	T251
Test name
Test status
Simulation time	1573163667 ps
CPU time	19.35 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:54:08 PM PDT 24
Peak memory	250812 kb
Host	smart-48db225d-a3fb-458e-b88f-dba255bcb3b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390805933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3390805933
Directory	/workspace/29.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_post_trans.1945314659
Short name	T833
Test name
Test status
Simulation time	62155187 ps
CPU time	6.96 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:53:56 PM PDT 24
Peak memory	250228 kb
Host	smart-683e8c75-ea73-4890-80fc-40e6fc86752c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945314659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1945314659
Directory	/workspace/29.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all.2845884299
Short name	T288
Test name
Test status
Simulation time	34636320958 ps
CPU time	252.88 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:58:01 PM PDT 24
Peak memory	226024 kb
Host	smart-e1cf7737-68c7-4957-9dd7-5dffe56b9632
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845884299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.2845884299
Directory	/workspace/29.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.764374313
Short name	T152
Test name
Test status
Simulation time	67097731369 ps
CPU time	222.32 seconds
Started	Apr 28 12:53:46 PM PDT 24
Finished	Apr 28 12:57:30 PM PDT 24
Peak memory	291276 kb
Host	smart-501e9b48-6e11-4ec1-b6e3-549ed5387f64
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=764374313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.764374313
Directory	/workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4182456158
Short name	T787
Test name
Test status
Simulation time	12692362 ps
CPU time	0.87 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:53:49 PM PDT 24
Peak memory	208464 kb
Host	smart-d94965f6-2266-4ae7-8692-176ce7b3a62e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182456158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c trl_volatile_unlock_smoke.4182456158
Directory	/workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_alert_test.1061288734
Short name	T181
Test name
Test status
Simulation time	23032362 ps
CPU time	0.99 seconds
Started	Apr 28 12:52:08 PM PDT 24
Finished	Apr 28 12:52:10 PM PDT 24
Peak memory	209424 kb
Host	smart-992c2cb3-ff88-41dd-b843-447183fa26ba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061288734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1061288734
Directory	/workspace/3.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.lc_ctrl_claim_transition_if.2612396688
Short name	T726
Test name
Test status
Simulation time	37773633 ps
CPU time	0.93 seconds
Started	Apr 28 12:52:12 PM PDT 24
Finished	Apr 28 12:52:13 PM PDT 24
Peak memory	209368 kb
Host	smart-a937f849-3a2e-4b32-b087-73ef127151a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612396688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2612396688
Directory	/workspace/3.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/3.lc_ctrl_errors.2634172981
Short name	T456
Test name
Test status
Simulation time	735312028 ps
CPU time	18.13 seconds
Started	Apr 28 12:52:09 PM PDT 24
Finished	Apr 28 12:52:27 PM PDT 24
Peak memory	217784 kb
Host	smart-219adc1d-aa6e-43fb-9540-3b86d4e6c5e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634172981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2634172981
Directory	/workspace/3.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_access.3410467126
Short name	T460
Test name
Test status
Simulation time	106712380 ps
CPU time	1.75 seconds
Started	Apr 28 12:52:13 PM PDT 24
Finished	Apr 28 12:52:15 PM PDT 24
Peak memory	216656 kb
Host	smart-316a3088-fa5e-4806-96ff-11a6476f079d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410467126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3410467126
Directory	/workspace/3.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_errors.1634998380
Short name	T621
Test name
Test status
Simulation time	8599150643 ps
CPU time	52.87 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:53:04 PM PDT 24
Peak memory	219900 kb
Host	smart-fdbe9365-ed74-46c4-86af-01946c2d0deb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634998380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er rors.1634998380
Directory	/workspace/3.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_priority.3984571934
Short name	T408
Test name
Test status
Simulation time	747020091 ps
CPU time	4.04 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:15 PM PDT 24
Peak memory	216892 kb
Host	smart-401a0e87-a430-4d59-806b-ad6e8eb66213
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984571934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3 984571934
Directory	/workspace/3.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.655605936
Short name	T533
Test name
Test status
Simulation time	471410823 ps
CPU time	3.8 seconds
Started	Apr 28 12:52:09 PM PDT 24
Finished	Apr 28 12:52:13 PM PDT 24
Peak memory	217848 kb
Host	smart-616870db-c65f-466f-87e9-f8bb9c775bf0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655605936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ prog_failure.655605936
Directory	/workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2939337567
Short name	T15
Test name
Test status
Simulation time	9931606316 ps
CPU time	16.06 seconds
Started	Apr 28 12:52:08 PM PDT 24
Finished	Apr 28 12:52:25 PM PDT 24
Peak memory	213756 kb
Host	smart-22c1d07d-aba4-458f-8893-5405449c7b2f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939337567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_regwen_during_op.2939337567
Directory	/workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_smoke.3050576886
Short name	T813
Test name
Test status
Simulation time	495692407 ps
CPU time	3.97 seconds
Started	Apr 28 12:52:06 PM PDT 24
Finished	Apr 28 12:52:11 PM PDT 24
Peak memory	213156 kb
Host	smart-2fb89f16-6714-4741-a919-f9829337b0e1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050576886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke. 3050576886
Directory	/workspace/3.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2599880395
Short name	T864
Test name
Test status
Simulation time	5768129398 ps
CPU time	53.36 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:53:09 PM PDT 24
Peak memory	254884 kb
Host	smart-8b4b2d5b-08fa-410e-ae5d-5d3a12c0d93e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599880395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_state_failure.2599880395
Directory	/workspace/3.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1509435713
Short name	T565
Test name
Test status
Simulation time	3647393441 ps
CPU time	23.9 seconds
Started	Apr 28 12:52:06 PM PDT 24
Finished	Apr 28 12:52:31 PM PDT 24
Peak memory	250748 kb
Host	smart-b5e15a09-eabc-41c9-94ab-6ded619aec5e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509435713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_state_post_trans.1509435713
Directory	/workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_prog_failure.2621122426
Short name	T234
Test name
Test status
Simulation time	313200287 ps
CPU time	2.33 seconds
Started	Apr 28 12:52:07 PM PDT 24
Finished	Apr 28 12:52:10 PM PDT 24
Peak memory	217824 kb
Host	smart-9bfec372-bd01-4e6f-815d-260b62dd917a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2621122426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2621122426
Directory	/workspace/3.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_regwen_during_op.3899674814
Short name	T77
Test name
Test status
Simulation time	828787273 ps
CPU time	6.01 seconds
Started	Apr 28 12:52:06 PM PDT 24
Finished	Apr 28 12:52:13 PM PDT 24
Peak memory	214032 kb
Host	smart-123350ae-c951-41e2-8f89-11bff9872f3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899674814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3899674814
Directory	/workspace/3.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_mubi.3962738579
Short name	T811
Test name
Test status
Simulation time	3741676614 ps
CPU time	17.8 seconds
Started	Apr 28 12:52:11 PM PDT 24
Finished	Apr 28 12:52:30 PM PDT 24
Peak memory	226080 kb
Host	smart-49db711b-21c1-4ac3-bc27-efbb2cf01269
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962738579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3962738579
Directory	/workspace/3.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_digest.9231661
Short name	T317
Test name
Test status
Simulation time	607000385 ps
CPU time	14.25 seconds
Started	Apr 28 12:52:12 PM PDT 24
Finished	Apr 28 12:52:26 PM PDT 24
Peak memory	217780 kb
Host	smart-407fb94e-1645-47b0-b345-4819e4220110
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9231661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_diges t.9231661
Directory	/workspace/3.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_mux.3287004937
Short name	T324
Test name
Test status
Simulation time	3838978982 ps
CPU time	15.23 seconds
Started	Apr 28 12:52:11 PM PDT 24
Finished	Apr 28 12:52:27 PM PDT 24
Peak memory	217996 kb
Host	smart-044c4f89-825b-4819-b6b4-b5d6e8f3ea4b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287004937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3 287004937
Directory	/workspace/3.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/3.lc_ctrl_security_escalation.3490014608
Short name	T858
Test name
Test status
Simulation time	278710662 ps
CPU time	8.01 seconds
Started	Apr 28 12:52:14 PM PDT 24
Finished	Apr 28 12:52:23 PM PDT 24
Peak memory	217792 kb
Host	smart-0975ace7-b604-447e-a25a-7d8bc00d9455
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490014608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3490014608
Directory	/workspace/3.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/3.lc_ctrl_smoke.2986778359
Short name	T503
Test name
Test status
Simulation time	72451187 ps
CPU time	2.18 seconds
Started	Apr 28 12:52:06 PM PDT 24
Finished	Apr 28 12:52:09 PM PDT 24
Peak memory	213912 kb
Host	smart-1d88b861-db0b-4334-9296-a168aa13bea0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986778359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2986778359
Directory	/workspace/3.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_failure.3845482658
Short name	T429
Test name
Test status
Simulation time	273898367 ps
CPU time	26.67 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:43 PM PDT 24
Peak memory	250716 kb
Host	smart-0f8a9e54-1560-467f-8db2-62bfa1b800d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3845482658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3845482658
Directory	/workspace/3.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_post_trans.2050578852
Short name	T322
Test name
Test status
Simulation time	385731388 ps
CPU time	8.97 seconds
Started	Apr 28 12:52:08 PM PDT 24
Finished	Apr 28 12:52:18 PM PDT 24
Peak memory	250840 kb
Host	smart-0e6e3b79-9e21-4c1a-91e1-4688d64c920e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050578852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2050578852
Directory	/workspace/3.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all.2038747460
Short name	T159
Test name
Test status
Simulation time	2194122771 ps
CPU time	59.25 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:53:10 PM PDT 24
Peak memory	272808 kb
Host	smart-f86dc1b7-b940-4549-b48d-91bae0150775
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038747460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.2038747460
Directory	/workspace/3.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.13170962
Short name	T390
Test name
Test status
Simulation time	14360096 ps
CPU time	0.81 seconds
Started	Apr 28 12:52:07 PM PDT 24
Finished	Apr 28 12:52:08 PM PDT 24
Peak memory	208376 kb
Host	smart-322288eb-ff5d-4b76-9bf2-bb53a6eba4a0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13170962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _volatile_unlock_smoke.13170962
Directory	/workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_alert_test.2025408721
Short name	T375
Test name
Test status
Simulation time	21821261 ps
CPU time	0.91 seconds
Started	Apr 28 12:53:44 PM PDT 24
Finished	Apr 28 12:53:46 PM PDT 24
Peak memory	209432 kb
Host	smart-1ac3dbd9-a048-4975-ad69-0c85db9fc97f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025408721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2025408721
Directory	/workspace/30.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.lc_ctrl_errors.3221779803
Short name	T605
Test name
Test status
Simulation time	425555159 ps
CPU time	10.12 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:53:59 PM PDT 24
Peak memory	217648 kb
Host	smart-cb50e041-7a84-4a7e-9ee3-30f9ce023c4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221779803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3221779803
Directory	/workspace/30.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/30.lc_ctrl_jtag_access.1576665643
Short name	T644
Test name
Test status
Simulation time	344836664 ps
CPU time	2.28 seconds
Started	Apr 28 12:53:44 PM PDT 24
Finished	Apr 28 12:53:46 PM PDT 24
Peak memory	209368 kb
Host	smart-75149241-0511-4fad-9390-4b6fc4ee08b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576665643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1576665643
Directory	/workspace/30.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/30.lc_ctrl_prog_failure.581986550
Short name	T814
Test name
Test status
Simulation time	59573751 ps
CPU time	2.48 seconds
Started	Apr 28 12:53:45 PM PDT 24
Finished	Apr 28 12:53:48 PM PDT 24
Peak memory	217840 kb
Host	smart-6bff47d0-2ee9-4f6c-ae00-3d248c4ebaf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581986550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.581986550
Directory	/workspace/30.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_mubi.457049442
Short name	T233
Test name
Test status
Simulation time	334468579 ps
CPU time	14.99 seconds
Started	Apr 28 12:53:44 PM PDT 24
Finished	Apr 28 12:53:59 PM PDT 24
Peak memory	218744 kb
Host	smart-06da280a-2728-4828-8a05-ba814bc8df8b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457049442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.457049442
Directory	/workspace/30.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_digest.2563000936
Short name	T327
Test name
Test status
Simulation time	1694757932 ps
CPU time	15.64 seconds
Started	Apr 28 12:53:46 PM PDT 24
Finished	Apr 28 12:54:02 PM PDT 24
Peak memory	217796 kb
Host	smart-104abb81-3e06-4ecf-a9b7-717c5576b531
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563000936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d igest.2563000936
Directory	/workspace/30.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_mux.227679623
Short name	T739
Test name
Test status
Simulation time	1574170597 ps
CPU time	12.94 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	217884 kb
Host	smart-c98e8f65-8ba3-461b-a695-167275a0ff5c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227679623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.227679623
Directory	/workspace/30.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/30.lc_ctrl_security_escalation.3164764447
Short name	T228
Test name
Test status
Simulation time	1481649501 ps
CPU time	8.39 seconds
Started	Apr 28 12:53:50 PM PDT 24
Finished	Apr 28 12:53:59 PM PDT 24
Peak memory	217788 kb
Host	smart-0e94b0d0-1170-42cb-863d-624650943c5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164764447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3164764447
Directory	/workspace/30.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/30.lc_ctrl_smoke.3079226524
Short name	T544
Test name
Test status
Simulation time	31727720 ps
CPU time	2.32 seconds
Started	Apr 28 12:53:46 PM PDT 24
Finished	Apr 28 12:53:49 PM PDT 24
Peak memory	213876 kb
Host	smart-6595f775-bbc9-4fe8-8a1e-bfcab654cf46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079226524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3079226524
Directory	/workspace/30.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_post_trans.3718768692
Short name	T682
Test name
Test status
Simulation time	159648936 ps
CPU time	7.81 seconds
Started	Apr 28 12:53:53 PM PDT 24
Finished	Apr 28 12:54:02 PM PDT 24
Peak memory	250872 kb
Host	smart-7ac17308-da1d-49b6-8394-e5e670d057ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718768692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3718768692
Directory	/workspace/30.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all.2297294820
Short name	T331
Test name
Test status
Simulation time	6122996871 ps
CPU time	141.01 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	365336 kb
Host	smart-ddfcd5fb-e18f-499f-8ea9-20e1ffb4560b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297294820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.2297294820
Directory	/workspace/30.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.255747984
Short name	T147
Test name
Test status
Simulation time	160449360951 ps
CPU time	1428.05 seconds
Started	Apr 28 12:53:45 PM PDT 24
Finished	Apr 28 01:17:34 PM PDT 24
Peak memory	496648 kb
Host	smart-d6680736-66b8-46e9-9c02-e3c35f9c76ed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=255747984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.255747984
Directory	/workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.439655789
Short name	T83
Test name
Test status
Simulation time	13016484 ps
CPU time	1.04 seconds
Started	Apr 28 12:53:46 PM PDT 24
Finished	Apr 28 12:53:47 PM PDT 24
Peak memory	211376 kb
Host	smart-300904f0-21f9-469f-94af-35e20ff3827e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439655789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct rl_volatile_unlock_smoke.439655789
Directory	/workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_alert_test.297764014
Short name	T604
Test name
Test status
Simulation time	57482293 ps
CPU time	1.33 seconds
Started	Apr 28 12:53:57 PM PDT 24
Finished	Apr 28 12:54:00 PM PDT 24
Peak memory	209468 kb
Host	smart-790ebfde-1691-4ef9-808a-3798be9ec72e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297764014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.297764014
Directory	/workspace/31.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.lc_ctrl_errors.4275612578
Short name	T493
Test name
Test status
Simulation time	874141544 ps
CPU time	8.22 seconds
Started	Apr 28 12:53:46 PM PDT 24
Finished	Apr 28 12:53:55 PM PDT 24
Peak memory	225868 kb
Host	smart-bda4f6f0-df4c-400e-9d5f-d2c77213c371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275612578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.4275612578
Directory	/workspace/31.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/31.lc_ctrl_jtag_access.3077944327
Short name	T196
Test name
Test status
Simulation time	482915673 ps
CPU time	3.34 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:53:52 PM PDT 24
Peak memory	216732 kb
Host	smart-f3948414-3ae6-42e1-8e1f-1959b90592a5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077944327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3077944327
Directory	/workspace/31.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/31.lc_ctrl_prog_failure.2949958414
Short name	T722
Test name
Test status
Simulation time	147915111 ps
CPU time	2.5 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:53:51 PM PDT 24
Peak memory	217732 kb
Host	smart-43df1b78-7169-4b1b-8201-817e8554a628
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949958414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2949958414
Directory	/workspace/31.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_mubi.4264124355
Short name	T567
Test name
Test status
Simulation time	1452570023 ps
CPU time	13.41 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:54:03 PM PDT 24
Peak memory	225732 kb
Host	smart-fc3ebf12-37a3-4b1b-ae28-b701b1e792f1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264124355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4264124355
Directory	/workspace/31.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_digest.3349083496
Short name	T376
Test name
Test status
Simulation time	1711969650 ps
CPU time	9.42 seconds
Started	Apr 28 12:53:49 PM PDT 24
Finished	Apr 28 12:53:59 PM PDT 24
Peak memory	217796 kb
Host	smart-e768f1d4-4a7e-4399-8580-5a52e12e691c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349083496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d igest.3349083496
Directory	/workspace/31.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_mux.799474785
Short name	T364
Test name
Test status
Simulation time	396204048 ps
CPU time	9.66 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:53:58 PM PDT 24
Peak memory	217832 kb
Host	smart-c2809abb-725a-454b-b46a-4dd082b296cc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799474785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.799474785
Directory	/workspace/31.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/31.lc_ctrl_security_escalation.3673910798
Short name	T190
Test name
Test status
Simulation time	365010155 ps
CPU time	8.78 seconds
Started	Apr 28 12:53:54 PM PDT 24
Finished	Apr 28 12:54:03 PM PDT 24
Peak memory	224620 kb
Host	smart-535f9052-eeaf-4946-8a72-63bdc36f0a6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673910798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3673910798
Directory	/workspace/31.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/31.lc_ctrl_smoke.807075754
Short name	T637
Test name
Test status
Simulation time	65606378 ps
CPU time	1.02 seconds
Started	Apr 28 12:53:47 PM PDT 24
Finished	Apr 28 12:53:49 PM PDT 24
Peak memory	212568 kb
Host	smart-861a5923-e316-4eb7-9e26-a1b9e74d50c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807075754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.807075754
Directory	/workspace/31.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_failure.2979768197
Short name	T826
Test name
Test status
Simulation time	531919864 ps
CPU time	25.53 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	249316 kb
Host	smart-f73805cd-00e1-4b1d-8d96-20cdaebeedf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979768197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2979768197
Directory	/workspace/31.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_post_trans.473753851
Short name	T752
Test name
Test status
Simulation time	136736659 ps
CPU time	8.82 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:53:58 PM PDT 24
Peak memory	250716 kb
Host	smart-0364746a-b047-4500-9f54-d888a2886bef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473753851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.473753851
Directory	/workspace/31.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all.2294573030
Short name	T20
Test name
Test status
Simulation time	7894045397 ps
CPU time	57.69 seconds
Started	Apr 28 12:53:48 PM PDT 24
Finished	Apr 28 12:54:47 PM PDT 24
Peak memory	250712 kb
Host	smart-95db82f2-6579-4d3f-8017-9cfc33c86f55
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294573030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.2294573030
Directory	/workspace/31.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2254679194
Short name	T31
Test name
Test status
Simulation time	60154556 ps
CPU time	0.9 seconds
Started	Apr 28 12:53:44 PM PDT 24
Finished	Apr 28 12:53:46 PM PDT 24
Peak memory	211392 kb
Host	smart-a61517b3-2084-457d-bc3a-f212895301bb
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254679194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c trl_volatile_unlock_smoke.2254679194
Directory	/workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_alert_test.3031935908
Short name	T343
Test name
Test status
Simulation time	25011717 ps
CPU time	1.01 seconds
Started	Apr 28 12:53:51 PM PDT 24
Finished	Apr 28 12:53:53 PM PDT 24
Peak memory	209364 kb
Host	smart-6fa529e1-b6b0-456d-98a0-98c8d154cf9d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031935908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3031935908
Directory	/workspace/32.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.lc_ctrl_errors.2872853862
Short name	T186
Test name
Test status
Simulation time	203950646 ps
CPU time	10.37 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	225952 kb
Host	smart-66574f38-70ff-40c6-9d22-8ed6411cd0b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872853862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2872853862
Directory	/workspace/32.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/32.lc_ctrl_jtag_access.2216469745
Short name	T513
Test name
Test status
Simulation time	2489826683 ps
CPU time	7.05 seconds
Started	Apr 28 12:53:49 PM PDT 24
Finished	Apr 28 12:53:57 PM PDT 24
Peak memory	209544 kb
Host	smart-5a7cfd18-eb80-4f2b-baae-7aacf9e519cb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216469745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2216469745
Directory	/workspace/32.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/32.lc_ctrl_prog_failure.632922068
Short name	T635
Test name
Test status
Simulation time	118181041 ps
CPU time	1.91 seconds
Started	Apr 28 12:53:51 PM PDT 24
Finished	Apr 28 12:53:54 PM PDT 24
Peak memory	217720 kb
Host	smart-f0f9fed3-be2f-4739-85f8-ac4763ebe346
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632922068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.632922068
Directory	/workspace/32.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_mubi.3372245527
Short name	T668
Test name
Test status
Simulation time	2509730227 ps
CPU time	15.61 seconds
Started	Apr 28 12:53:53 PM PDT 24
Finished	Apr 28 12:54:10 PM PDT 24
Peak memory	219140 kb
Host	smart-2bf33118-3f28-46e5-8e05-c5b1e3893930
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372245527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3372245527
Directory	/workspace/32.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_digest.3781560939
Short name	T550
Test name
Test status
Simulation time	305477238 ps
CPU time	12.38 seconds
Started	Apr 28 12:53:51 PM PDT 24
Finished	Apr 28 12:54:04 PM PDT 24
Peak memory	217840 kb
Host	smart-f84f1906-6596-43f4-8810-701425986d65
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781560939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d igest.3781560939
Directory	/workspace/32.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_mux.3143753260
Short name	T524
Test name
Test status
Simulation time	288497345 ps
CPU time	9.69 seconds
Started	Apr 28 12:53:51 PM PDT 24
Finished	Apr 28 12:54:02 PM PDT 24
Peak memory	217752 kb
Host	smart-a841baaf-690e-49f2-914f-942e3c047fe9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143753260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux. 3143753260
Directory	/workspace/32.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/32.lc_ctrl_smoke.2502938401
Short name	T30
Test name
Test status
Simulation time	178271853 ps
CPU time	4.82 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	217600 kb
Host	smart-cc52fa58-1ae1-4898-8ee0-fa7d8c2096d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502938401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2502938401
Directory	/workspace/32.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_failure.529804155
Short name	T321
Test name
Test status
Simulation time	241738514 ps
CPU time	22.81 seconds
Started	Apr 28 12:53:50 PM PDT 24
Finished	Apr 28 12:54:14 PM PDT 24
Peak memory	250748 kb
Host	smart-6f59fc4b-4b52-42ca-a7d5-b23704978618
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=529804155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.529804155
Directory	/workspace/32.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_post_trans.226865041
Short name	T716
Test name
Test status
Simulation time	389363188 ps
CPU time	3.53 seconds
Started	Apr 28 12:53:50 PM PDT 24
Finished	Apr 28 12:53:55 PM PDT 24
Peak memory	226252 kb
Host	smart-f6847746-9c0c-4434-a632-ba6f65e51391
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226865041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.226865041
Directory	/workspace/32.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all.2270177166
Short name	T58
Test name
Test status
Simulation time	21746261413 ps
CPU time	161.18 seconds
Started	Apr 28 12:53:51 PM PDT 24
Finished	Apr 28 12:56:33 PM PDT 24
Peak memory	274632 kb
Host	smart-d0b7657e-f850-430f-aed5-0f194db1c935
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270177166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.2270177166
Directory	/workspace/32.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2431287627
Short name	T795
Test name
Test status
Simulation time	49909703 ps
CPU time	0.95 seconds
Started	Apr 28 12:53:50 PM PDT 24
Finished	Apr 28 12:53:52 PM PDT 24
Peak memory	208412 kb
Host	smart-50633d2a-20a6-4245-89a4-6c4ff48ec2b8
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431287627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c trl_volatile_unlock_smoke.2431287627
Directory	/workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_alert_test.2383185141
Short name	T865
Test name
Test status
Simulation time	29125020 ps
CPU time	1.16 seconds
Started	Apr 28 12:54:03 PM PDT 24
Finished	Apr 28 12:54:06 PM PDT 24
Peak memory	209132 kb
Host	smart-d2f894f4-4f3a-442a-818c-9de30f9d3207
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383185141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2383185141
Directory	/workspace/33.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.lc_ctrl_errors.1019309810
Short name	T107
Test name
Test status
Simulation time	460591152 ps
CPU time	13.67 seconds
Started	Apr 28 12:53:51 PM PDT 24
Finished	Apr 28 12:54:05 PM PDT 24
Peak memory	217788 kb
Host	smart-bb75a1eb-f323-4502-887d-47f4c9a592c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019309810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1019309810
Directory	/workspace/33.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/33.lc_ctrl_jtag_access.3116662192
Short name	T622
Test name
Test status
Simulation time	58650201 ps
CPU time	1.26 seconds
Started	Apr 28 12:53:50 PM PDT 24
Finished	Apr 28 12:53:52 PM PDT 24
Peak memory	209428 kb
Host	smart-76e269c2-cb96-49c1-ad2d-a0e91f8fddff
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116662192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3116662192
Directory	/workspace/33.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/33.lc_ctrl_prog_failure.567729569
Short name	T656
Test name
Test status
Simulation time	87866414 ps
CPU time	3.73 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:07 PM PDT 24
Peak memory	217804 kb
Host	smart-91f04a1b-c886-43bc-9d95-af09383585f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567729569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.567729569
Directory	/workspace/33.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_mubi.2818558880
Short name	T250
Test name
Test status
Simulation time	322858957 ps
CPU time	16.07 seconds
Started	Apr 28 12:53:50 PM PDT 24
Finished	Apr 28 12:54:07 PM PDT 24
Peak memory	225952 kb
Host	smart-f40ee310-6d34-4c62-9b85-5269af55ab33
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818558880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2818558880
Directory	/workspace/33.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_digest.2519057520
Short name	T39
Test name
Test status
Simulation time	407170953 ps
CPU time	15.24 seconds
Started	Apr 28 12:54:03 PM PDT 24
Finished	Apr 28 12:54:20 PM PDT 24
Peak memory	217824 kb
Host	smart-e128241d-e166-4119-a3ab-18635216d900
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519057520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d igest.2519057520
Directory	/workspace/33.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_mux.2451362328
Short name	T827
Test name
Test status
Simulation time	987032832 ps
CPU time	9.46 seconds
Started	Apr 28 12:54:03 PM PDT 24
Finished	Apr 28 12:54:14 PM PDT 24
Peak memory	217888 kb
Host	smart-bac9f2cf-1197-476b-9c1e-5c3e64bb3583
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451362328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux. 2451362328
Directory	/workspace/33.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/33.lc_ctrl_security_escalation.1623274613
Short name	T484
Test name
Test status
Simulation time	550811193 ps
CPU time	7.04 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:11 PM PDT 24
Peak memory	217876 kb
Host	smart-ceb8b1be-3611-4849-9acf-b4d86ea6e5bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623274613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1623274613
Directory	/workspace/33.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/33.lc_ctrl_smoke.3788916332
Short name	T409
Test name
Test status
Simulation time	435920617 ps
CPU time	3.4 seconds
Started	Apr 28 12:53:57 PM PDT 24
Finished	Apr 28 12:54:01 PM PDT 24
Peak memory	214108 kb
Host	smart-024e6cee-08b8-4766-b520-8b46bfb12cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788916332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3788916332
Directory	/workspace/33.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_failure.534626613
Short name	T743
Test name
Test status
Simulation time	1105483456 ps
CPU time	30.06 seconds
Started	Apr 28 12:53:52 PM PDT 24
Finished	Apr 28 12:54:22 PM PDT 24
Peak memory	246156 kb
Host	smart-42e2b4e7-b840-40b0-963b-27c695c1aeda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534626613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.534626613
Directory	/workspace/33.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_post_trans.1372170310
Short name	T379
Test name
Test status
Simulation time	881359279 ps
CPU time	3.96 seconds
Started	Apr 28 12:54:03 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	226232 kb
Host	smart-24bf5233-141c-4f80-a489-b6989df289c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372170310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1372170310
Directory	/workspace/33.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all.4144933087
Short name	T101
Test name
Test status
Simulation time	35517074611 ps
CPU time	160.95 seconds
Started	Apr 28 12:53:51 PM PDT 24
Finished	Apr 28 12:56:32 PM PDT 24
Peak memory	269680 kb
Host	smart-ccfa7957-6e79-4fd5-b4a9-bb048012e8fc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144933087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.4144933087
Directory	/workspace/33.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1930617550
Short name	T332
Test name
Test status
Simulation time	13289847 ps
CPU time	1.05 seconds
Started	Apr 28 12:53:50 PM PDT 24
Finished	Apr 28 12:53:52 PM PDT 24
Peak memory	211516 kb
Host	smart-e644c8b6-6b85-47a3-a91a-428ef62d4acf
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930617550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c trl_volatile_unlock_smoke.1930617550
Directory	/workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_alert_test.907113007
Short name	T386
Test name
Test status
Simulation time	35321760 ps
CPU time	0.91 seconds
Started	Apr 28 12:54:01 PM PDT 24
Finished	Apr 28 12:54:02 PM PDT 24
Peak memory	209312 kb
Host	smart-d8b5003e-adc8-42c1-93f6-30ba808e157f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907113007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.907113007
Directory	/workspace/34.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.lc_ctrl_errors.4186774513
Short name	T852
Test name
Test status
Simulation time	353948658 ps
CPU time	7.58 seconds
Started	Apr 28 12:53:57 PM PDT 24
Finished	Apr 28 12:54:05 PM PDT 24
Peak memory	225908 kb
Host	smart-876c4a8a-c413-4f17-a9ea-e49a09f51c69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186774513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.4186774513
Directory	/workspace/34.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/34.lc_ctrl_prog_failure.1426950703
Short name	T748
Test name
Test status
Simulation time	60886886 ps
CPU time	3.06 seconds
Started	Apr 28 12:53:59 PM PDT 24
Finished	Apr 28 12:54:03 PM PDT 24
Peak memory	217788 kb
Host	smart-4f639bd7-4834-4fda-941a-49627f28b5e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426950703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1426950703
Directory	/workspace/34.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_mubi.2499836665
Short name	T316
Test name
Test status
Simulation time	589173234 ps
CPU time	15.72 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:20 PM PDT 24
Peak memory	218716 kb
Host	smart-75c192d0-1396-49f0-9e21-0f334acb94c4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499836665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2499836665
Directory	/workspace/34.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_digest.1264904729
Short name	T398
Test name
Test status
Simulation time	247186302 ps
CPU time	8.72 seconds
Started	Apr 28 12:54:01 PM PDT 24
Finished	Apr 28 12:54:10 PM PDT 24
Peak memory	217880 kb
Host	smart-850230a3-519d-4935-a930-8ddc3b71cc2a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264904729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d igest.1264904729
Directory	/workspace/34.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_mux.3970223404
Short name	T755
Test name
Test status
Simulation time	262842140 ps
CPU time	9.63 seconds
Started	Apr 28 12:54:04 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	217772 kb
Host	smart-a8f5a021-d3a4-4854-bf32-95d72d26e4ca
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970223404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux. 3970223404
Directory	/workspace/34.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/34.lc_ctrl_security_escalation.3413414459
Short name	T660
Test name
Test status
Simulation time	1289135310 ps
CPU time	11.54 seconds
Started	Apr 28 12:53:54 PM PDT 24
Finished	Apr 28 12:54:06 PM PDT 24
Peak memory	225880 kb
Host	smart-c9b270fa-a2e3-431e-adf8-42367eede842
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413414459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3413414459
Directory	/workspace/34.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/34.lc_ctrl_smoke.2335325584
Short name	T277
Test name
Test status
Simulation time	1020908229 ps
CPU time	6.29 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:54:02 PM PDT 24
Peak memory	217804 kb
Host	smart-1bf8d215-4cc2-4e1b-9b07-f14861163fd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335325584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2335325584
Directory	/workspace/34.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_failure.1912653836
Short name	T665
Test name
Test status
Simulation time	505368186 ps
CPU time	30.28 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:34 PM PDT 24
Peak memory	247224 kb
Host	smart-f0ed5a41-febe-4043-93d2-65a2771a8ed5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912653836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1912653836
Directory	/workspace/34.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_post_trans.1777050850
Short name	T268
Test name
Test status
Simulation time	63765589 ps
CPU time	7.88 seconds
Started	Apr 28 12:53:57 PM PDT 24
Finished	Apr 28 12:54:06 PM PDT 24
Peak memory	250588 kb
Host	smart-ef650021-7505-413e-aa7a-51bec127d103
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777050850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1777050850
Directory	/workspace/34.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all.1486973888
Short name	T261
Test name
Test status
Simulation time	10471225525 ps
CPU time	22.57 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:54:18 PM PDT 24
Peak memory	248704 kb
Host	smart-06e02da0-e5f8-4e71-8901-74baa5e95153
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486973888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.1486973888
Directory	/workspace/34.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1074294813
Short name	T694
Test name
Test status
Simulation time	20721013 ps
CPU time	0.84 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:53:57 PM PDT 24
Peak memory	208360 kb
Host	smart-72349f55-e3f3-4624-b441-67dc3073a19b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074294813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c trl_volatile_unlock_smoke.1074294813
Directory	/workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_alert_test.3182050178
Short name	T256
Test name
Test status
Simulation time	50462759 ps
CPU time	0.91 seconds
Started	Apr 28 12:53:56 PM PDT 24
Finished	Apr 28 12:53:57 PM PDT 24
Peak memory	209332 kb
Host	smart-f9640091-7efa-4a65-938e-fbffe1ebc101
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182050178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3182050178
Directory	/workspace/35.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.lc_ctrl_errors.2493511083
Short name	T175
Test name
Test status
Simulation time	434010547 ps
CPU time	12.03 seconds
Started	Apr 28 12:53:56 PM PDT 24
Finished	Apr 28 12:54:08 PM PDT 24
Peak memory	217788 kb
Host	smart-012019c2-8f32-4049-958b-35c68b7fe78a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493511083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2493511083
Directory	/workspace/35.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/35.lc_ctrl_jtag_access.2491003372
Short name	T863
Test name
Test status
Simulation time	94323365 ps
CPU time	1.5 seconds
Started	Apr 28 12:53:58 PM PDT 24
Finished	Apr 28 12:54:00 PM PDT 24
Peak memory	209444 kb
Host	smart-38e053d8-c216-4b15-a771-6fb26ddf243b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491003372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2491003372
Directory	/workspace/35.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/35.lc_ctrl_prog_failure.2634163690
Short name	T585
Test name
Test status
Simulation time	127828330 ps
CPU time	2.66 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:53:58 PM PDT 24
Peak memory	217848 kb
Host	smart-9000ddb5-9043-40c5-b6b3-2aa1feffe7e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634163690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2634163690
Directory	/workspace/35.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_mubi.3153779255
Short name	T730
Test name
Test status
Simulation time	554997348 ps
CPU time	11.51 seconds
Started	Apr 28 12:53:57 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	225852 kb
Host	smart-34cfd388-b039-4a3e-9929-26e5d80369b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153779255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3153779255
Directory	/workspace/35.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_digest.835403620
Short name	T661
Test name
Test status
Simulation time	972469172 ps
CPU time	9.43 seconds
Started	Apr 28 12:53:54 PM PDT 24
Finished	Apr 28 12:54:05 PM PDT 24
Peak memory	217740 kb
Host	smart-770ad786-3469-48f6-a9d6-ac7630ac021d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835403620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di gest.835403620
Directory	/workspace/35.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_mux.4278996932
Short name	T350
Test name
Test status
Simulation time	1463666600 ps
CPU time	13.79 seconds
Started	Apr 28 12:53:56 PM PDT 24
Finished	Apr 28 12:54:10 PM PDT 24
Peak memory	217856 kb
Host	smart-92f34f12-af55-477d-bd9b-b12996953420
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278996932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux. 4278996932
Directory	/workspace/35.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/35.lc_ctrl_security_escalation.715927055
Short name	T463
Test name
Test status
Simulation time	611380170 ps
CPU time	8.94 seconds
Started	Apr 28 12:53:57 PM PDT 24
Finished	Apr 28 12:54:07 PM PDT 24
Peak memory	217904 kb
Host	smart-182647d4-cfd4-4cd6-beba-7e833f4412ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715927055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.715927055
Directory	/workspace/35.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/35.lc_ctrl_smoke.1344741277
Short name	T738
Test name
Test status
Simulation time	34762472 ps
CPU time	1.63 seconds
Started	Apr 28 12:54:03 PM PDT 24
Finished	Apr 28 12:54:07 PM PDT 24
Peak memory	213116 kb
Host	smart-3da81f16-167e-4bd7-a8f4-820d2ea3ff28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344741277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1344741277
Directory	/workspace/35.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_failure.3684028868
Short name	T793
Test name
Test status
Simulation time	1100559932 ps
CPU time	21.2 seconds
Started	Apr 28 12:53:59 PM PDT 24
Finished	Apr 28 12:54:21 PM PDT 24
Peak memory	248428 kb
Host	smart-11d07f1a-54d8-443a-954d-1ca4b013c350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3684028868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3684028868
Directory	/workspace/35.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_post_trans.2287601996
Short name	T759
Test name
Test status
Simulation time	956850333 ps
CPU time	6.13 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:54:02 PM PDT 24
Peak memory	242560 kb
Host	smart-f6f73e32-9924-4d04-800b-60aec0983db4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287601996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2287601996
Directory	/workspace/35.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all.569545639
Short name	T821
Test name
Test status
Simulation time	11654648467 ps
CPU time	158.86 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:56:35 PM PDT 24
Peak memory	220268 kb
Host	smart-adee62b2-336e-4382-8d09-34d180a3b015
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569545639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.569545639
Directory	/workspace/35.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.204609861
Short name	T654
Test name
Test status
Simulation time	89828676 ps
CPU time	0.84 seconds
Started	Apr 28 12:53:55 PM PDT 24
Finished	Apr 28 12:53:57 PM PDT 24
Peak memory	211360 kb
Host	smart-c0ac8c31-1fe1-4862-a33a-f7985e1aec07
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204609861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct rl_volatile_unlock_smoke.204609861
Directory	/workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_alert_test.1117315242
Short name	T869
Test name
Test status
Simulation time	76659193 ps
CPU time	1.12 seconds
Started	Apr 28 12:54:04 PM PDT 24
Finished	Apr 28 12:54:07 PM PDT 24
Peak memory	209376 kb
Host	smart-2d8ed1bb-ccbd-4300-8c6b-5638fa807b22
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117315242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1117315242
Directory	/workspace/36.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.lc_ctrl_errors.4291717960
Short name	T853
Test name
Test status
Simulation time	220846890 ps
CPU time	7.55 seconds
Started	Apr 28 12:54:00 PM PDT 24
Finished	Apr 28 12:54:08 PM PDT 24
Peak memory	225896 kb
Host	smart-0e9b6ea6-42be-4980-8370-493446639af2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291717960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.4291717960
Directory	/workspace/36.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/36.lc_ctrl_jtag_access.1476789765
Short name	T29
Test name
Test status
Simulation time	524246019 ps
CPU time	4.14 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:08 PM PDT 24
Peak memory	216856 kb
Host	smart-469f2bb2-901e-4b1f-9004-de9b2a71e589
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476789765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1476789765
Directory	/workspace/36.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/36.lc_ctrl_prog_failure.2148333880
Short name	T370
Test name
Test status
Simulation time	37746485 ps
CPU time	2.17 seconds
Started	Apr 28 12:54:01 PM PDT 24
Finished	Apr 28 12:54:04 PM PDT 24
Peak memory	217804 kb
Host	smart-0126ee28-d3b8-43d8-8b3f-473ada6f2d54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148333880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2148333880
Directory	/workspace/36.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_mubi.1459523282
Short name	T459
Test name
Test status
Simulation time	901076574 ps
CPU time	14.31 seconds
Started	Apr 28 12:54:03 PM PDT 24
Finished	Apr 28 12:54:19 PM PDT 24
Peak memory	218872 kb
Host	smart-5fd14b60-da63-4818-b67f-3a873eef6275
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459523282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1459523282
Directory	/workspace/36.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_digest.544584962
Short name	T669
Test name
Test status
Simulation time	1331349053 ps
CPU time	14.1 seconds
Started	Apr 28 12:54:04 PM PDT 24
Finished	Apr 28 12:54:20 PM PDT 24
Peak memory	217804 kb
Host	smart-fa4bfa38-45e7-4861-8766-1b00d99a8a9f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544584962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di gest.544584962
Directory	/workspace/36.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/36.lc_ctrl_security_escalation.1507023296
Short name	T483
Test name
Test status
Simulation time	319048579 ps
CPU time	8.19 seconds
Started	Apr 28 12:54:03 PM PDT 24
Finished	Apr 28 12:54:13 PM PDT 24
Peak memory	225800 kb
Host	smart-25238c28-ce90-474c-8fea-f1435610756b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507023296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1507023296
Directory	/workspace/36.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/36.lc_ctrl_smoke.2819191211
Short name	T82
Test name
Test status
Simulation time	69703170 ps
CPU time	3.09 seconds
Started	Apr 28 12:53:57 PM PDT 24
Finished	Apr 28 12:54:00 PM PDT 24
Peak memory	213920 kb
Host	smart-e0133f59-7499-4498-bca5-65bfe98054d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819191211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2819191211
Directory	/workspace/36.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_failure.3468725514
Short name	T499
Test name
Test status
Simulation time	209509933 ps
CPU time	22.65 seconds
Started	Apr 28 12:54:01 PM PDT 24
Finished	Apr 28 12:54:25 PM PDT 24
Peak memory	250788 kb
Host	smart-43c8819f-57c5-40e4-8a56-eda1e19a8447
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468725514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3468725514
Directory	/workspace/36.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_post_trans.4254324749
Short name	T304
Test name
Test status
Simulation time	103383927 ps
CPU time	7.44 seconds
Started	Apr 28 12:54:04 PM PDT 24
Finished	Apr 28 12:54:13 PM PDT 24
Peak memory	244948 kb
Host	smart-319daf64-0b42-4225-929c-75d4a04e1a8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254324749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4254324749
Directory	/workspace/36.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all.1425198914
Short name	T247
Test name
Test status
Simulation time	5138463685 ps
CPU time	127.29 seconds
Started	Apr 28 12:54:01 PM PDT 24
Finished	Apr 28 12:56:08 PM PDT 24
Peak memory	250832 kb
Host	smart-c13d4937-f4bf-4f67-ae7d-8f3b68257c46
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425198914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.1425198914
Directory	/workspace/36.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2462001670
Short name	T548
Test name
Test status
Simulation time	65623290672 ps
CPU time	369.78 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 01:00:14 PM PDT 24
Peak memory	276292 kb
Host	smart-db42316f-f7c6-47be-8ac7-a8a0f73189d9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2462001670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2462001670
Directory	/workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3939238100
Short name	T265
Test name
Test status
Simulation time	37939902 ps
CPU time	0.85 seconds
Started	Apr 28 12:53:56 PM PDT 24
Finished	Apr 28 12:53:58 PM PDT 24
Peak memory	207824 kb
Host	smart-2659d5d6-6a3e-45cf-acde-7e2816e77af2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939238100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c trl_volatile_unlock_smoke.3939238100
Directory	/workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_alert_test.848284790
Short name	T547
Test name
Test status
Simulation time	56182698 ps
CPU time	1.53 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:06 PM PDT 24
Peak memory	209428 kb
Host	smart-ae56ae10-8022-4fd6-9c39-327366446a8e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848284790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.848284790
Directory	/workspace/37.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.lc_ctrl_errors.3387385118
Short name	T518
Test name
Test status
Simulation time	1124999641 ps
CPU time	15.01 seconds
Started	Apr 28 12:54:04 PM PDT 24
Finished	Apr 28 12:54:21 PM PDT 24
Peak memory	217764 kb
Host	smart-00800015-291f-4cdc-8317-af895f85ce7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3387385118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3387385118
Directory	/workspace/37.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/37.lc_ctrl_jtag_access.1194910450
Short name	T419
Test name
Test status
Simulation time	2089221847 ps
CPU time	5.02 seconds
Started	Apr 28 12:54:00 PM PDT 24
Finished	Apr 28 12:54:05 PM PDT 24
Peak memory	209324 kb
Host	smart-3dbb527c-3829-4ef5-914a-458683bc2d06
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194910450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1194910450
Directory	/workspace/37.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/37.lc_ctrl_prog_failure.273634785
Short name	T428
Test name
Test status
Simulation time	102974900 ps
CPU time	2.94 seconds
Started	Apr 28 12:54:03 PM PDT 24
Finished	Apr 28 12:54:08 PM PDT 24
Peak memory	217860 kb
Host	smart-3b8911bf-7a64-4ac5-aa6c-e9ddd5d1e53f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273634785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.273634785
Directory	/workspace/37.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_mubi.3752235943
Short name	T348
Test name
Test status
Simulation time	486940868 ps
CPU time	13.36 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:17 PM PDT 24
Peak memory	217372 kb
Host	smart-a8600564-f396-4f1c-a36a-e7d60d3717d5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752235943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3752235943
Directory	/workspace/37.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_digest.3398290388
Short name	T231
Test name
Test status
Simulation time	349677067 ps
CPU time	10.04 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:14 PM PDT 24
Peak memory	217916 kb
Host	smart-169920a8-3ed4-407b-b0ff-8901ad3d3b14
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398290388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d igest.3398290388
Directory	/workspace/37.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_mux.1292240140
Short name	T803
Test name
Test status
Simulation time	480553813 ps
CPU time	8.87 seconds
Started	Apr 28 12:54:04 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	217852 kb
Host	smart-f792ca43-dfc5-4fb7-987c-aa608f082b11
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292240140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux. 1292240140
Directory	/workspace/37.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/37.lc_ctrl_security_escalation.3003748893
Short name	T418
Test name
Test status
Simulation time	442170168 ps
CPU time	10.58 seconds
Started	Apr 28 12:54:06 PM PDT 24
Finished	Apr 28 12:54:18 PM PDT 24
Peak memory	217916 kb
Host	smart-5760f2c8-0008-471d-9644-26d90611054b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003748893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3003748893
Directory	/workspace/37.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/37.lc_ctrl_smoke.4141414074
Short name	T75
Test name
Test status
Simulation time	62580103 ps
CPU time	3.21 seconds
Started	Apr 28 12:54:05 PM PDT 24
Finished	Apr 28 12:54:10 PM PDT 24
Peak memory	217768 kb
Host	smart-bbd723f7-e3d4-474d-b21f-826aca6c6340
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141414074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.4141414074
Directory	/workspace/37.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_failure.626477566
Short name	T238
Test name
Test status
Simulation time	3482375519 ps
CPU time	25.27 seconds
Started	Apr 28 12:54:05 PM PDT 24
Finished	Apr 28 12:54:32 PM PDT 24
Peak memory	250956 kb
Host	smart-7b2bff80-d9cd-40bd-b854-3c11137be2f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=626477566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.626477566
Directory	/workspace/37.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_post_trans.1844310650
Short name	T401
Test name
Test status
Simulation time	294166970 ps
CPU time	8.7 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:13 PM PDT 24
Peak memory	250756 kb
Host	smart-69b92764-af80-41bb-ae83-82e0b786da28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844310650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1844310650
Directory	/workspace/37.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all.566830930
Short name	T411
Test name
Test status
Simulation time	10993396527 ps
CPU time	49.1 seconds
Started	Apr 28 12:54:07 PM PDT 24
Finished	Apr 28 12:54:57 PM PDT 24
Peak memory	259020 kb
Host	smart-10189b63-f3df-4a7a-9e8b-71fb36871057
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566830930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.566830930
Directory	/workspace/37.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1931359724
Short name	T320
Test name
Test status
Simulation time	22905905 ps
CPU time	0.93 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:04 PM PDT 24
Peak memory	212496 kb
Host	smart-93b02dae-7a7a-44e3-89b7-8c82fef05111
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931359724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c trl_volatile_unlock_smoke.1931359724
Directory	/workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_alert_test.356521986
Short name	T91
Test name
Test status
Simulation time	58978501 ps
CPU time	0.92 seconds
Started	Apr 28 12:54:07 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	209420 kb
Host	smart-5e1f81b2-af34-4429-9bb6-ad4ab98cb3bb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356521986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.356521986
Directory	/workspace/38.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.lc_ctrl_errors.416013125
Short name	T490
Test name
Test status
Simulation time	1281140559 ps
CPU time	10.73 seconds
Started	Apr 28 12:54:07 PM PDT 24
Finished	Apr 28 12:54:19 PM PDT 24
Peak memory	225900 kb
Host	smart-9caa465c-a32a-4854-ad39-e93b58afce32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416013125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.416013125
Directory	/workspace/38.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/38.lc_ctrl_jtag_access.2131606785
Short name	T710
Test name
Test status
Simulation time	3236965132 ps
CPU time	14.98 seconds
Started	Apr 28 12:54:05 PM PDT 24
Finished	Apr 28 12:54:21 PM PDT 24
Peak memory	217488 kb
Host	smart-36a5e920-f9b6-4580-8440-db75d832529b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131606785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2131606785
Directory	/workspace/38.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/38.lc_ctrl_prog_failure.1204630971
Short name	T487
Test name
Test status
Simulation time	118136707 ps
CPU time	1.52 seconds
Started	Apr 28 12:54:06 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	217916 kb
Host	smart-5efc4ad6-d8df-444d-8cfc-53c2abbc953a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204630971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1204630971
Directory	/workspace/38.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_mubi.4208445873
Short name	T845
Test name
Test status
Simulation time	824677121 ps
CPU time	8.39 seconds
Started	Apr 28 12:54:06 PM PDT 24
Finished	Apr 28 12:54:16 PM PDT 24
Peak memory	217820 kb
Host	smart-c787ca26-fe8b-4e4a-aa15-1f6ccc8e28e5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208445873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4208445873
Directory	/workspace/38.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_digest.1833408285
Short name	T245
Test name
Test status
Simulation time	726061729 ps
CPU time	18.96 seconds
Started	Apr 28 12:54:05 PM PDT 24
Finished	Apr 28 12:54:26 PM PDT 24
Peak memory	217808 kb
Host	smart-82925e6c-39d8-47b4-8a8d-867d146fca03
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833408285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d igest.1833408285
Directory	/workspace/38.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_mux.1324676388
Short name	T719
Test name
Test status
Simulation time	4343804343 ps
CPU time	13.04 seconds
Started	Apr 28 12:54:07 PM PDT 24
Finished	Apr 28 12:54:21 PM PDT 24
Peak memory	217912 kb
Host	smart-6290dd0a-b13d-4453-9e75-5bc2c32e50b1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324676388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux. 1324676388
Directory	/workspace/38.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/38.lc_ctrl_security_escalation.3318708894
Short name	T577
Test name
Test status
Simulation time	937510448 ps
CPU time	8.34 seconds
Started	Apr 28 12:54:09 PM PDT 24
Finished	Apr 28 12:54:18 PM PDT 24
Peak memory	217828 kb
Host	smart-909cb898-7978-4482-bb4a-eae416e5cc8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3318708894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3318708894
Directory	/workspace/38.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/38.lc_ctrl_smoke.1444113184
Short name	T685
Test name
Test status
Simulation time	45687256 ps
CPU time	1.8 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:05 PM PDT 24
Peak memory	217752 kb
Host	smart-d155ab18-8eb3-4e6f-a7cb-1b49390d567f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444113184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1444113184
Directory	/workspace/38.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_failure.3621785637
Short name	T454
Test name
Test status
Simulation time	312873622 ps
CPU time	15.25 seconds
Started	Apr 28 12:54:08 PM PDT 24
Finished	Apr 28 12:54:24 PM PDT 24
Peak memory	248344 kb
Host	smart-dfaa358f-de9f-4a2c-a481-a9eb9618a84b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621785637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3621785637
Directory	/workspace/38.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_post_trans.2038700732
Short name	T634
Test name
Test status
Simulation time	194441664 ps
CPU time	6.65 seconds
Started	Apr 28 12:54:08 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	248080 kb
Host	smart-86a27e42-5dfe-4da6-9ae5-3c514640fff6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038700732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2038700732
Directory	/workspace/38.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all.1210601080
Short name	T413
Test name
Test status
Simulation time	13633054296 ps
CPU time	161.82 seconds
Started	Apr 28 12:54:06 PM PDT 24
Finished	Apr 28 12:56:49 PM PDT 24
Peak memory	250876 kb
Host	smart-440fae7c-a8d0-4015-9d00-1f605b2c0384
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210601080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.1210601080
Directory	/workspace/38.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2672954487
Short name	T416
Test name
Test status
Simulation time	14002476 ps
CPU time	0.98 seconds
Started	Apr 28 12:54:02 PM PDT 24
Finished	Apr 28 12:54:05 PM PDT 24
Peak memory	211412 kb
Host	smart-2eba2ce8-f4e8-43c6-bfc7-0d76984a893c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672954487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c trl_volatile_unlock_smoke.2672954487
Directory	/workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_alert_test.3300834679
Short name	T538
Test name
Test status
Simulation time	44589246 ps
CPU time	0.85 seconds
Started	Apr 28 12:54:13 PM PDT 24
Finished	Apr 28 12:54:14 PM PDT 24
Peak memory	209320 kb
Host	smart-915a2951-013d-4d44-ba55-18d3919bf9d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300834679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3300834679
Directory	/workspace/39.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.lc_ctrl_errors.2372889114
Short name	T102
Test name
Test status
Simulation time	1592997730 ps
CPU time	15.81 seconds
Started	Apr 28 12:54:06 PM PDT 24
Finished	Apr 28 12:54:24 PM PDT 24
Peak memory	217832 kb
Host	smart-e562c8f5-c1c7-4fae-85b3-e18129e22d59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372889114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2372889114
Directory	/workspace/39.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/39.lc_ctrl_jtag_access.3215305008
Short name	T373
Test name
Test status
Simulation time	857937238 ps
CPU time	4.29 seconds
Started	Apr 28 12:54:07 PM PDT 24
Finished	Apr 28 12:54:12 PM PDT 24
Peak memory	216828 kb
Host	smart-640b6120-fc42-4419-bf5e-a59d78ba3615
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215305008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3215305008
Directory	/workspace/39.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/39.lc_ctrl_prog_failure.3978256006
Short name	T796
Test name
Test status
Simulation time	62149226 ps
CPU time	2.59 seconds
Started	Apr 28 12:54:06 PM PDT 24
Finished	Apr 28 12:54:10 PM PDT 24
Peak memory	217844 kb
Host	smart-a4f1f53c-a636-40e3-b21e-e441b7470032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978256006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3978256006
Directory	/workspace/39.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_mubi.2910724789
Short name	T473
Test name
Test status
Simulation time	355643996 ps
CPU time	12.31 seconds
Started	Apr 28 12:54:07 PM PDT 24
Finished	Apr 28 12:54:21 PM PDT 24
Peak memory	225920 kb
Host	smart-783607d7-ff3d-49a2-bbad-0d832443afe0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910724789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2910724789
Directory	/workspace/39.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_digest.795212650
Short name	T444
Test name
Test status
Simulation time	191056234 ps
CPU time	8.42 seconds
Started	Apr 28 12:54:10 PM PDT 24
Finished	Apr 28 12:54:19 PM PDT 24
Peak memory	217864 kb
Host	smart-589dff9f-8e35-4355-bd2a-7aaef3606192
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795212650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di gest.795212650
Directory	/workspace/39.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_mux.673017556
Short name	T560
Test name
Test status
Simulation time	1352076505 ps
CPU time	12.28 seconds
Started	Apr 28 12:54:05 PM PDT 24
Finished	Apr 28 12:54:19 PM PDT 24
Peak memory	217812 kb
Host	smart-bfd7dc7e-f00c-4289-bb6e-006d11053c45
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673017556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.673017556
Directory	/workspace/39.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/39.lc_ctrl_security_escalation.2875689099
Short name	T791
Test name
Test status
Simulation time	752289076 ps
CPU time	8.73 seconds
Started	Apr 28 12:54:06 PM PDT 24
Finished	Apr 28 12:54:16 PM PDT 24
Peak memory	217860 kb
Host	smart-73bb4765-5af9-4619-ab8e-61ab10d8a514
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875689099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2875689099
Directory	/workspace/39.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/39.lc_ctrl_smoke.2615799346
Short name	T614
Test name
Test status
Simulation time	29608514 ps
CPU time	2.31 seconds
Started	Apr 28 12:54:05 PM PDT 24
Finished	Apr 28 12:54:09 PM PDT 24
Peak memory	214072 kb
Host	smart-faf63971-88c4-4d40-b041-1db26a813e0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615799346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2615799346
Directory	/workspace/39.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_failure.215422763
Short name	T658
Test name
Test status
Simulation time	231443991 ps
CPU time	21.83 seconds
Started	Apr 28 12:54:06 PM PDT 24
Finished	Apr 28 12:54:30 PM PDT 24
Peak memory	250748 kb
Host	smart-0bdf6768-1df1-4e49-9519-7889cbd40c1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215422763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.215422763
Directory	/workspace/39.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_post_trans.1850157516
Short name	T751
Test name
Test status
Simulation time	117235968 ps
CPU time	6.82 seconds
Started	Apr 28 12:54:07 PM PDT 24
Finished	Apr 28 12:54:15 PM PDT 24
Peak memory	250740 kb
Host	smart-bcc719b5-f72f-48b9-a63d-c2ce458ea7a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850157516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1850157516
Directory	/workspace/39.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all.3554679588
Short name	T773
Test name
Test status
Simulation time	10284840497 ps
CPU time	77.51 seconds
Started	Apr 28 12:54:15 PM PDT 24
Finished	Apr 28 12:55:33 PM PDT 24
Peak memory	259084 kb
Host	smart-62b614f0-ad3f-4f9d-8b4f-0a101ea374fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554679588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.3554679588
Directory	/workspace/39.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2161978249
Short name	T297
Test name
Test status
Simulation time	12543114 ps
CPU time	0.8 seconds
Started	Apr 28 12:54:11 PM PDT 24
Finished	Apr 28 12:54:13 PM PDT 24
Peak memory	208580 kb
Host	smart-241437b0-6a0f-4238-a99a-4bf725a4c340
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161978249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c trl_volatile_unlock_smoke.2161978249
Directory	/workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_alert_test.3792617281
Short name	T314
Test name
Test status
Simulation time	31400203 ps
CPU time	0.97 seconds
Started	Apr 28 12:52:18 PM PDT 24
Finished	Apr 28 12:52:20 PM PDT 24
Peak memory	209308 kb
Host	smart-756054b2-685c-41a5-b56b-f5c8cb565398
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792617281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3792617281
Directory	/workspace/4.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.lc_ctrl_claim_transition_if.2532091937
Short name	T633
Test name
Test status
Simulation time	59462044 ps
CPU time	0.98 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:11 PM PDT 24
Peak memory	209428 kb
Host	smart-339a1247-e21c-4397-a8ff-d7814d3bd056
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532091937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2532091937
Directory	/workspace/4.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/4.lc_ctrl_errors.3177812970
Short name	T406
Test name
Test status
Simulation time	669844179 ps
CPU time	12.37 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:23 PM PDT 24
Peak memory	217760 kb
Host	smart-5fcd5423-8019-4888-8ef4-7daaf557c42f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177812970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3177812970
Directory	/workspace/4.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_access.2769279677
Short name	T28
Test name
Test status
Simulation time	1677576679 ps
CPU time	8.22 seconds
Started	Apr 28 12:52:16 PM PDT 24
Finished	Apr 28 12:52:25 PM PDT 24
Peak memory	209364 kb
Host	smart-f68d4161-2eeb-4579-85c1-4db51327386c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769279677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2769279677
Directory	/workspace/4.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_errors.1900274837
Short name	T754
Test name
Test status
Simulation time	1321388176 ps
CPU time	20.64 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	217772 kb
Host	smart-facf1632-dfd4-4c58-81fb-ad1f2a04c9f9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900274837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er rors.1900274837
Directory	/workspace/4.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_priority.402977753
Short name	T529
Test name
Test status
Simulation time	534252720 ps
CPU time	2.36 seconds
Started	Apr 28 12:52:16 PM PDT 24
Finished	Apr 28 12:52:19 PM PDT 24
Peak memory	216944 kb
Host	smart-d4d3bc4e-f74c-4532-b1b9-a6d7225de454
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402977753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.402977753
Directory	/workspace/4.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2680924815
Short name	T758
Test name
Test status
Simulation time	3224277365 ps
CPU time	10.27 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:52:29 PM PDT 24
Peak memory	217832 kb
Host	smart-a0717985-c4e1-493b-a5a8-901be1e9b063
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680924815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag _prog_failure.2680924815
Directory	/workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3319309033
Short name	T667
Test name
Test status
Simulation time	795957026 ps
CPU time	11.84 seconds
Started	Apr 28 12:52:20 PM PDT 24
Finished	Apr 28 12:52:33 PM PDT 24
Peak memory	212864 kb
Host	smart-3fb8720a-1751-466f-86f7-0929d447713e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319309033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_regwen_during_op.3319309033
Directory	/workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_smoke.2357983503
Short name	T607
Test name
Test status
Simulation time	1130639590 ps
CPU time	5.18 seconds
Started	Apr 28 12:52:09 PM PDT 24
Finished	Apr 28 12:52:15 PM PDT 24
Peak memory	213636 kb
Host	smart-548e5543-b3b2-49fa-bb49-80b40a839ec8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357983503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke. 2357983503
Directory	/workspace/4.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1744892901
Short name	T857
Test name
Test status
Simulation time	13167506776 ps
CPU time	72.37 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:53:29 PM PDT 24
Peak memory	271512 kb
Host	smart-dbd94d07-ea66-42f6-a48b-d761ea4bf7ce
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744892901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta g_state_failure.1744892901
Directory	/workspace/4.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1852802168
Short name	T617
Test name
Test status
Simulation time	272647359 ps
CPU time	6.27 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:52:26 PM PDT 24
Peak memory	222440 kb
Host	smart-0533a9ee-a6ad-4961-9af6-cf5d1702340d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852802168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_state_post_trans.1852802168
Directory	/workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_prog_failure.2528553405
Short name	T679
Test name
Test status
Simulation time	37760348 ps
CPU time	2.4 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:13 PM PDT 24
Peak memory	217880 kb
Host	smart-60eb6a12-cee5-4715-9758-a86b92193bbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528553405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2528553405
Directory	/workspace/4.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_regwen_during_op.1972464713
Short name	T455
Test name
Test status
Simulation time	639317633 ps
CPU time	11.48 seconds
Started	Apr 28 12:52:09 PM PDT 24
Finished	Apr 28 12:52:22 PM PDT 24
Peak memory	217560 kb
Host	smart-e89d1f07-e91f-4fbe-8346-b13372623a88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972464713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1972464713
Directory	/workspace/4.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_cm.230877043
Short name	T90
Test name
Test status
Simulation time	154776344 ps
CPU time	25.21 seconds
Started	Apr 28 12:52:14 PM PDT 24
Finished	Apr 28 12:52:40 PM PDT 24
Peak memory	269272 kb
Host	smart-383e5277-11a2-4072-817d-5018e97d51d9
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230877043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.230877043
Directory	/workspace/4.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_mubi.3859403916
Short name	T400
Test name
Test status
Simulation time	1302009561 ps
CPU time	18.69 seconds
Started	Apr 28 12:52:17 PM PDT 24
Finished	Apr 28 12:52:37 PM PDT 24
Peak memory	217712 kb
Host	smart-3935c5ad-82c9-44e8-ad87-176bf0212611
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859403916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3859403916
Directory	/workspace/4.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_digest.4149405062
Short name	T846
Test name
Test status
Simulation time	589929095 ps
CPU time	8.39 seconds
Started	Apr 28 12:52:17 PM PDT 24
Finished	Apr 28 12:52:26 PM PDT 24
Peak memory	217740 kb
Host	smart-75b96200-303f-4dfa-bcf7-ab93483536e8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149405062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di gest.4149405062
Directory	/workspace/4.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_mux.1612776489
Short name	T805
Test name
Test status
Simulation time	1649235934 ps
CPU time	9.59 seconds
Started	Apr 28 12:52:17 PM PDT 24
Finished	Apr 28 12:52:28 PM PDT 24
Peak memory	217720 kb
Host	smart-61aac349-ce7e-44e6-b490-97afeb7ee550
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612776489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1 612776489
Directory	/workspace/4.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/4.lc_ctrl_smoke.2527942237
Short name	T302
Test name
Test status
Simulation time	51007376 ps
CPU time	1.11 seconds
Started	Apr 28 12:52:10 PM PDT 24
Finished	Apr 28 12:52:12 PM PDT 24
Peak memory	211752 kb
Host	smart-c627d9cd-1e69-44e3-b8e1-9f8afbafc41d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527942237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2527942237
Directory	/workspace/4.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_failure.2430800754
Short name	T861
Test name
Test status
Simulation time	1312338125 ps
CPU time	27.13 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:43 PM PDT 24
Peak memory	250836 kb
Host	smart-e84d6f1d-1901-44be-9647-0c8f19c3f6bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430800754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2430800754
Directory	/workspace/4.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_post_trans.2872297166
Short name	T810
Test name
Test status
Simulation time	203262668 ps
CPU time	4.44 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:20 PM PDT 24
Peak memory	222216 kb
Host	smart-d8e4c948-ab78-4420-9593-3fda677b7687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872297166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2872297166
Directory	/workspace/4.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all.2241668884
Short name	T415
Test name
Test status
Simulation time	14686826012 ps
CPU time	197.73 seconds
Started	Apr 28 12:52:16 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	250948 kb
Host	smart-9fad4bd1-22e3-45b0-a5e5-36b88736a702
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241668884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.2241668884
Directory	/workspace/4.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1413691149
Short name	T110
Test name
Test status
Simulation time	28957830543 ps
CPU time	358.05 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:58:14 PM PDT 24
Peak memory	237440 kb
Host	smart-8b1a229a-fac0-46fa-9385-c50deb6ff2ef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1413691149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1413691149
Directory	/workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.875671500
Short name	T338
Test name
Test status
Simulation time	22056047 ps
CPU time	0.91 seconds
Started	Apr 28 12:52:14 PM PDT 24
Finished	Apr 28 12:52:15 PM PDT 24
Peak memory	208520 kb
Host	smart-b91b4744-f60e-4345-8f83-15a887167a61
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875671500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr l_volatile_unlock_smoke.875671500
Directory	/workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_alert_test.3803358906
Short name	T363
Test name
Test status
Simulation time	22325407 ps
CPU time	1.28 seconds
Started	Apr 28 12:54:14 PM PDT 24
Finished	Apr 28 12:54:16 PM PDT 24
Peak memory	209380 kb
Host	smart-226d6ae7-ddd7-4b44-a145-d9d0fee09d28
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803358906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3803358906
Directory	/workspace/40.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.lc_ctrl_errors.445592928
Short name	T423
Test name
Test status
Simulation time	486220227 ps
CPU time	11 seconds
Started	Apr 28 12:54:13 PM PDT 24
Finished	Apr 28 12:54:25 PM PDT 24
Peak memory	225836 kb
Host	smart-59f7be7a-e645-4a80-983a-efd71b215910
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445592928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.445592928
Directory	/workspace/40.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/40.lc_ctrl_jtag_access.2480053449
Short name	T701
Test name
Test status
Simulation time	389383653 ps
CPU time	4.95 seconds
Started	Apr 28 12:54:15 PM PDT 24
Finished	Apr 28 12:54:21 PM PDT 24
Peak memory	209352 kb
Host	smart-281db638-9ed0-45a6-ada5-e06c7cfe4d00
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480053449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2480053449
Directory	/workspace/40.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/40.lc_ctrl_prog_failure.1225827516
Short name	T12
Test name
Test status
Simulation time	56486673 ps
CPU time	1.74 seconds
Started	Apr 28 12:54:14 PM PDT 24
Finished	Apr 28 12:54:16 PM PDT 24
Peak memory	217736 kb
Host	smart-ab83d3d4-20a6-4c3a-b8d6-0736ae60f207
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225827516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1225827516
Directory	/workspace/40.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_mubi.2726943613
Short name	T167
Test name
Test status
Simulation time	540573871 ps
CPU time	15.42 seconds
Started	Apr 28 12:54:13 PM PDT 24
Finished	Apr 28 12:54:29 PM PDT 24
Peak memory	225836 kb
Host	smart-44a60a6a-4e61-474b-a3f0-a75ceb03339b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726943613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2726943613
Directory	/workspace/40.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_digest.1241030357
Short name	T630
Test name
Test status
Simulation time	1460592368 ps
CPU time	9.79 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:26 PM PDT 24
Peak memory	217792 kb
Host	smart-3b379b09-6d53-4314-80cc-86e1b1710ad4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241030357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d igest.1241030357
Directory	/workspace/40.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_mux.3127338295
Short name	T727
Test name
Test status
Simulation time	987144145 ps
CPU time	6.11 seconds
Started	Apr 28 12:54:10 PM PDT 24
Finished	Apr 28 12:54:17 PM PDT 24
Peak memory	217796 kb
Host	smart-95cc41f4-3ced-4165-9a7d-672b47ba2799
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127338295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux. 3127338295
Directory	/workspace/40.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/40.lc_ctrl_smoke.148947099
Short name	T414
Test name
Test status
Simulation time	32915602 ps
CPU time	1.22 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:18 PM PDT 24
Peak memory	213328 kb
Host	smart-08799475-1bb7-4a50-9841-304a574bac95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148947099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.148947099
Directory	/workspace/40.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_failure.4120346141
Short name	T603
Test name
Test status
Simulation time	292264198 ps
CPU time	23.29 seconds
Started	Apr 28 12:54:15 PM PDT 24
Finished	Apr 28 12:54:39 PM PDT 24
Peak memory	245568 kb
Host	smart-368d1d5a-4282-4d6a-bb72-14e92d7b9354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120346141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4120346141
Directory	/workspace/40.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_post_trans.4003975660
Short name	T325
Test name
Test status
Simulation time	134321918 ps
CPU time	9.22 seconds
Started	Apr 28 12:54:15 PM PDT 24
Finished	Apr 28 12:54:24 PM PDT 24
Peak memory	250836 kb
Host	smart-36332506-efea-45de-957c-bda18ab3b84a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003975660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.4003975660
Directory	/workspace/40.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all.1751877510
Short name	T494
Test name
Test status
Simulation time	12653624190 ps
CPU time	101.8 seconds
Started	Apr 28 12:54:12 PM PDT 24
Finished	Apr 28 12:55:54 PM PDT 24
Peak memory	283004 kb
Host	smart-9a8d4db7-5fe0-42a4-8953-e9b3b04a77d7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751877510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all.1751877510
Directory	/workspace/40.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.631952042
Short name	T149
Test name
Test status
Simulation time	22810504632 ps
CPU time	249.78 seconds
Started	Apr 28 12:54:11 PM PDT 24
Finished	Apr 28 12:58:22 PM PDT 24
Peak memory	496844 kb
Host	smart-2538384a-d6f6-4095-a038-4fae0407c448
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=631952042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.631952042
Directory	/workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1965835162
Short name	T824
Test name
Test status
Simulation time	13971331 ps
CPU time	0.81 seconds
Started	Apr 28 12:54:12 PM PDT 24
Finished	Apr 28 12:54:13 PM PDT 24
Peak memory	208420 kb
Host	smart-31b16e38-97b4-4cb9-89aa-026cbfae2107
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965835162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c trl_volatile_unlock_smoke.1965835162
Directory	/workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_alert_test.652791109
Short name	T389
Test name
Test status
Simulation time	23173762 ps
CPU time	0.95 seconds
Started	Apr 28 12:54:18 PM PDT 24
Finished	Apr 28 12:54:20 PM PDT 24
Peak memory	209340 kb
Host	smart-f16f2ed1-9150-4f08-ad55-cecf8d3ac931
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652791109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.652791109
Directory	/workspace/41.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.lc_ctrl_errors.3655101344
Short name	T405
Test name
Test status
Simulation time	5201320487 ps
CPU time	13.47 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:30 PM PDT 24
Peak memory	218288 kb
Host	smart-a1eb6a3c-5f46-4db4-a9a1-e898db9aa329
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655101344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3655101344
Directory	/workspace/41.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/41.lc_ctrl_jtag_access.1910412633
Short name	T197
Test name
Test status
Simulation time	767319975 ps
CPU time	10.56 seconds
Started	Apr 28 12:54:19 PM PDT 24
Finished	Apr 28 12:54:30 PM PDT 24
Peak memory	217104 kb
Host	smart-ac8fa097-1df5-4d53-8d44-1d1eca16b48e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910412633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1910412633
Directory	/workspace/41.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/41.lc_ctrl_prog_failure.3063989669
Short name	T606
Test name
Test status
Simulation time	189822810 ps
CPU time	2.32 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:19 PM PDT 24
Peak memory	217800 kb
Host	smart-8a3a839a-99f8-443a-9fcb-74fff587b953
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063989669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3063989669
Directory	/workspace/41.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_mubi.658514495
Short name	T746
Test name
Test status
Simulation time	896896172 ps
CPU time	19.81 seconds
Started	Apr 28 12:54:18 PM PDT 24
Finished	Apr 28 12:54:39 PM PDT 24
Peak memory	218708 kb
Host	smart-1a28f7c5-f1b8-4eba-84db-5f66a253c365
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658514495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.658514495
Directory	/workspace/41.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_digest.2542812441
Short name	T452
Test name
Test status
Simulation time	775285359 ps
CPU time	12.51 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:30 PM PDT 24
Peak memory	217832 kb
Host	smart-66e514e2-7901-40d5-99b5-21986b412cb6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542812441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d igest.2542812441
Directory	/workspace/41.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_mux.3248584183
Short name	T774
Test name
Test status
Simulation time	217547155 ps
CPU time	6.56 seconds
Started	Apr 28 12:54:17 PM PDT 24
Finished	Apr 28 12:54:25 PM PDT 24
Peak memory	217856 kb
Host	smart-68f48a41-9052-435b-974c-30126fe97f07
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248584183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux. 3248584183
Directory	/workspace/41.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/41.lc_ctrl_security_escalation.1925109893
Short name	T334
Test name
Test status
Simulation time	334212303 ps
CPU time	12.79 seconds
Started	Apr 28 12:54:17 PM PDT 24
Finished	Apr 28 12:54:31 PM PDT 24
Peak memory	217924 kb
Host	smart-ce14dea2-7d9f-4cbd-bb9e-26e007604ee7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925109893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1925109893
Directory	/workspace/41.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/41.lc_ctrl_smoke.2261122404
Short name	T244
Test name
Test status
Simulation time	274964761 ps
CPU time	1.75 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:19 PM PDT 24
Peak memory	213432 kb
Host	smart-edde5e8c-1e8c-4f34-99a2-4fd781572821
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261122404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2261122404
Directory	/workspace/41.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_failure.1811971548
Short name	T356
Test name
Test status
Simulation time	363347106 ps
CPU time	29.52 seconds
Started	Apr 28 12:54:15 PM PDT 24
Finished	Apr 28 12:54:45 PM PDT 24
Peak memory	248704 kb
Host	smart-eed9a9dd-78dd-448b-9849-248ce0492c06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811971548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1811971548
Directory	/workspace/41.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_post_trans.4061635465
Short name	T653
Test name
Test status
Simulation time	225883507 ps
CPU time	8.11 seconds
Started	Apr 28 12:54:13 PM PDT 24
Finished	Apr 28 12:54:22 PM PDT 24
Peak memory	242572 kb
Host	smart-886a220c-691b-4742-9c49-6f1afdc53e21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061635465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4061635465
Directory	/workspace/41.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all.3005709403
Short name	T195
Test name
Test status
Simulation time	2554471065 ps
CPU time	87.07 seconds
Started	Apr 28 12:54:21 PM PDT 24
Finished	Apr 28 12:55:49 PM PDT 24
Peak memory	252408 kb
Host	smart-c9d17d53-7bd4-4e39-a4dc-4a3af23cb62d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005709403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.3005709403
Directory	/workspace/41.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1270853834
Short name	T187
Test name
Test status
Simulation time	54736576 ps
CPU time	0.91 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:18 PM PDT 24
Peak memory	211460 kb
Host	smart-e942f851-9fd3-450a-a270-a380f68e6d65
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270853834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c trl_volatile_unlock_smoke.1270853834
Directory	/workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_alert_test.4205693585
Short name	T285
Test name
Test status
Simulation time	13559893 ps
CPU time	1.02 seconds
Started	Apr 28 12:54:21 PM PDT 24
Finished	Apr 28 12:54:23 PM PDT 24
Peak memory	209424 kb
Host	smart-70d52f88-9e5e-4c8c-8d0a-d5d62f4bc40e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205693585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.4205693585
Directory	/workspace/42.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.lc_ctrl_errors.3429882463
Short name	T466
Test name
Test status
Simulation time	595266044 ps
CPU time	14.6 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:32 PM PDT 24
Peak memory	225840 kb
Host	smart-7d8b6561-70fc-4ad4-ae92-73b56f6da01c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429882463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3429882463
Directory	/workspace/42.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/42.lc_ctrl_jtag_access.2545069912
Short name	T166
Test name
Test status
Simulation time	1136629019 ps
CPU time	14.36 seconds
Started	Apr 28 12:54:17 PM PDT 24
Finished	Apr 28 12:54:33 PM PDT 24
Peak memory	209392 kb
Host	smart-36b43bbc-a0c8-4acf-bb0d-84a5d85e0507
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545069912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2545069912
Directory	/workspace/42.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/42.lc_ctrl_prog_failure.3698104325
Short name	T558
Test name
Test status
Simulation time	208081854 ps
CPU time	3.62 seconds
Started	Apr 28 12:54:21 PM PDT 24
Finished	Apr 28 12:54:26 PM PDT 24
Peak memory	217908 kb
Host	smart-6c5de921-3618-4ad6-bf4f-e4471b17dd24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698104325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3698104325
Directory	/workspace/42.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_mubi.996567209
Short name	T835
Test name
Test status
Simulation time	3031060917 ps
CPU time	15.35 seconds
Started	Apr 28 12:54:20 PM PDT 24
Finished	Apr 28 12:54:36 PM PDT 24
Peak memory	219076 kb
Host	smart-90cc180e-abb2-4792-a43f-f9b321964343
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996567209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.996567209
Directory	/workspace/42.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_digest.4168586681
Short name	T439
Test name
Test status
Simulation time	241444156 ps
CPU time	7.9 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:25 PM PDT 24
Peak memory	217920 kb
Host	smart-4e8fe52f-2603-4472-9e64-5e0e6b7627dd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168586681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d igest.4168586681
Directory	/workspace/42.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_mux.2496946440
Short name	T249
Test name
Test status
Simulation time	1423760956 ps
CPU time	14.46 seconds
Started	Apr 28 12:54:21 PM PDT 24
Finished	Apr 28 12:54:36 PM PDT 24
Peak memory	217844 kb
Host	smart-6a15c752-a5b2-4ebc-9283-69e5033cf3b5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496946440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux. 2496946440
Directory	/workspace/42.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/42.lc_ctrl_security_escalation.4278938179
Short name	T798
Test name
Test status
Simulation time	243902152 ps
CPU time	10.32 seconds
Started	Apr 28 12:54:19 PM PDT 24
Finished	Apr 28 12:54:30 PM PDT 24
Peak memory	217916 kb
Host	smart-b1dee136-2893-4bfd-aba5-0f20a3e05546
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278938179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.4278938179
Directory	/workspace/42.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/42.lc_ctrl_smoke.2054160797
Short name	T98
Test name
Test status
Simulation time	292010449 ps
CPU time	1.99 seconds
Started	Apr 28 12:54:20 PM PDT 24
Finished	Apr 28 12:54:23 PM PDT 24
Peak memory	213612 kb
Host	smart-f2cf41aa-1e8d-4289-aebb-ece3a77de1d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054160797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2054160797
Directory	/workspace/42.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_failure.1436483563
Short name	T253
Test name
Test status
Simulation time	726984244 ps
CPU time	28.77 seconds
Started	Apr 28 12:54:16 PM PDT 24
Finished	Apr 28 12:54:46 PM PDT 24
Peak memory	250720 kb
Host	smart-c2c2e791-9ffd-4e42-be7d-8485f57d3035
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436483563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1436483563
Directory	/workspace/42.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_post_trans.1867223930
Short name	T686
Test name
Test status
Simulation time	345978635 ps
CPU time	3.41 seconds
Started	Apr 28 12:54:21 PM PDT 24
Finished	Apr 28 12:54:26 PM PDT 24
Peak memory	221888 kb
Host	smart-1c6b157a-19f3-4dd1-8910-0d6ef1ecb382
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867223930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1867223930
Directory	/workspace/42.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all.1658268818
Short name	T44
Test name
Test status
Simulation time	22768756885 ps
CPU time	79.79 seconds
Started	Apr 28 12:54:19 PM PDT 24
Finished	Apr 28 12:55:39 PM PDT 24
Peak memory	226084 kb
Host	smart-51a6c61f-7250-451f-8340-769517556ec9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658268818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.1658268818
Directory	/workspace/42.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1588702064
Short name	T276
Test name
Test status
Simulation time	16814173 ps
CPU time	0.81 seconds
Started	Apr 28 12:54:20 PM PDT 24
Finished	Apr 28 12:54:21 PM PDT 24
Peak memory	208380 kb
Host	smart-09c8a5bd-256c-481d-9015-c77f389067f0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588702064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c trl_volatile_unlock_smoke.1588702064
Directory	/workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_alert_test.973023638
Short name	T311
Test name
Test status
Simulation time	43226701 ps
CPU time	0.93 seconds
Started	Apr 28 12:54:22 PM PDT 24
Finished	Apr 28 12:54:23 PM PDT 24
Peak memory	209404 kb
Host	smart-bedb61e8-d75b-42ac-aa16-5864c791c347
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973023638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.973023638
Directory	/workspace/43.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.lc_ctrl_errors.325202674
Short name	T431
Test name
Test status
Simulation time	1655071432 ps
CPU time	12.64 seconds
Started	Apr 28 12:54:18 PM PDT 24
Finished	Apr 28 12:54:31 PM PDT 24
Peak memory	217704 kb
Host	smart-99d6e768-3991-4e8e-b3e2-f18694cdd01f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325202674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.325202674
Directory	/workspace/43.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/43.lc_ctrl_jtag_access.1930088862
Short name	T836
Test name
Test status
Simulation time	590631910 ps
CPU time	10.47 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 12:54:34 PM PDT 24
Peak memory	216784 kb
Host	smart-206380aa-9256-486e-a3d0-6c2e619093ae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930088862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1930088862
Directory	/workspace/43.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/43.lc_ctrl_prog_failure.3408796524
Short name	T530
Test name
Test status
Simulation time	290579173 ps
CPU time	3.66 seconds
Started	Apr 28 12:54:19 PM PDT 24
Finished	Apr 28 12:54:23 PM PDT 24
Peak memory	217720 kb
Host	smart-00234cea-8437-455d-9dd4-4b39cb6bf66c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408796524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3408796524
Directory	/workspace/43.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_mubi.2575812569
Short name	T689
Test name
Test status
Simulation time	2713491185 ps
CPU time	14 seconds
Started	Apr 28 12:54:20 PM PDT 24
Finished	Apr 28 12:54:34 PM PDT 24
Peak memory	218864 kb
Host	smart-342855b8-f213-4396-9343-93b02ac13658
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575812569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2575812569
Directory	/workspace/43.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_digest.2681680021
Short name	T678
Test name
Test status
Simulation time	301039768 ps
CPU time	10.36 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 12:54:35 PM PDT 24
Peak memory	217800 kb
Host	smart-5c323203-4e32-4368-b6d0-b89034194301
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681680021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d igest.2681680021
Directory	/workspace/43.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_mux.3940919870
Short name	T189
Test name
Test status
Simulation time	278689261 ps
CPU time	9.5 seconds
Started	Apr 28 12:54:21 PM PDT 24
Finished	Apr 28 12:54:32 PM PDT 24
Peak memory	217764 kb
Host	smart-baf90565-0f07-4d4b-a70d-9a7a0cd2d1d8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940919870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux. 3940919870
Directory	/workspace/43.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/43.lc_ctrl_security_escalation.319970063
Short name	T670
Test name
Test status
Simulation time	990195139 ps
CPU time	11.95 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 12:54:36 PM PDT 24
Peak memory	217792 kb
Host	smart-b9d80de2-ef48-4042-8908-9d79099d13bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319970063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.319970063
Directory	/workspace/43.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/43.lc_ctrl_smoke.2160480555
Short name	T392
Test name
Test status
Simulation time	486555556 ps
CPU time	3.89 seconds
Started	Apr 28 12:54:17 PM PDT 24
Finished	Apr 28 12:54:22 PM PDT 24
Peak memory	217640 kb
Host	smart-f847df40-ce25-4835-af62-3b3be7227291
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160480555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2160480555
Directory	/workspace/43.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_failure.3521383778
Short name	T161
Test name
Test status
Simulation time	1445495944 ps
CPU time	38.11 seconds
Started	Apr 28 12:54:18 PM PDT 24
Finished	Apr 28 12:54:57 PM PDT 24
Peak memory	248176 kb
Host	smart-182fdfe7-477a-4e5d-9d67-7f68d7ae9193
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521383778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3521383778
Directory	/workspace/43.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_post_trans.3730905371
Short name	T182
Test name
Test status
Simulation time	45571635 ps
CPU time	7.98 seconds
Started	Apr 28 12:54:17 PM PDT 24
Finished	Apr 28 12:54:26 PM PDT 24
Peak memory	246712 kb
Host	smart-c69628c8-9a7d-41a9-b6a7-a250cef040a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730905371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3730905371
Directory	/workspace/43.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all.991621309
Short name	T875
Test name
Test status
Simulation time	13874382965 ps
CPU time	52.09 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 12:55:16 PM PDT 24
Peak memory	250744 kb
Host	smart-30a4c221-b312-401c-ba22-7973894a36a6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991621309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.991621309
Directory	/workspace/43.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2189791918
Short name	T174
Test name
Test status
Simulation time	89409099316 ps
CPU time	827.83 seconds
Started	Apr 28 12:54:20 PM PDT 24
Finished	Apr 28 01:08:09 PM PDT 24
Peak memory	278052 kb
Host	smart-b58ccd17-95be-401d-ad29-8bf7b80d71d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2189791918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2189791918
Directory	/workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3704025125
Short name	T286
Test name
Test status
Simulation time	14078521 ps
CPU time	1.12 seconds
Started	Apr 28 12:54:17 PM PDT 24
Finished	Apr 28 12:54:19 PM PDT 24
Peak memory	211436 kb
Host	smart-c5f477b3-99c4-45c2-9c8c-5dc38ce30121
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704025125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c trl_volatile_unlock_smoke.3704025125
Directory	/workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_alert_test.1559846674
Short name	T624
Test name
Test status
Simulation time	132537323 ps
CPU time	0.97 seconds
Started	Apr 28 12:54:22 PM PDT 24
Finished	Apr 28 12:54:24 PM PDT 24
Peak memory	209512 kb
Host	smart-c300b805-c19d-404b-96fc-d8079c7a03a6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559846674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1559846674
Directory	/workspace/44.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.lc_ctrl_errors.1626354991
Short name	T639
Test name
Test status
Simulation time	991277788 ps
CPU time	14.82 seconds
Started	Apr 28 12:54:24 PM PDT 24
Finished	Apr 28 12:54:40 PM PDT 24
Peak memory	217800 kb
Host	smart-cdc91a8a-678d-4548-b306-417fded96399
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626354991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1626354991
Directory	/workspace/44.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/44.lc_ctrl_jtag_access.1111466531
Short name	T24
Test name
Test status
Simulation time	276727698 ps
CPU time	4.34 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 12:54:29 PM PDT 24
Peak memory	209384 kb
Host	smart-44be9d3f-dd74-4d34-b663-6b0157ea58fd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111466531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1111466531
Directory	/workspace/44.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/44.lc_ctrl_prog_failure.3382540281
Short name	T239
Test name
Test status
Simulation time	35139391 ps
CPU time	1.95 seconds
Started	Apr 28 12:54:22 PM PDT 24
Finished	Apr 28 12:54:24 PM PDT 24
Peak memory	217800 kb
Host	smart-3763968c-da03-4900-beb8-49f1e846386e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382540281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3382540281
Directory	/workspace/44.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_mubi.4079631201
Short name	T789
Test name
Test status
Simulation time	391647335 ps
CPU time	16.33 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 12:54:41 PM PDT 24
Peak memory	218800 kb
Host	smart-5fbbe995-bb81-40cc-9d03-5f475c0bdec0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079631201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4079631201
Directory	/workspace/44.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_digest.1623061391
Short name	T173
Test name
Test status
Simulation time	4947993120 ps
CPU time	15.14 seconds
Started	Apr 28 12:54:25 PM PDT 24
Finished	Apr 28 12:54:41 PM PDT 24
Peak memory	217896 kb
Host	smart-c61a61d9-8a65-44a7-a0d1-bede090789a9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623061391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d igest.1623061391
Directory	/workspace/44.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_mux.3758640779
Short name	T702
Test name
Test status
Simulation time	581581730 ps
CPU time	12.14 seconds
Started	Apr 28 12:54:25 PM PDT 24
Finished	Apr 28 12:54:38 PM PDT 24
Peak memory	217880 kb
Host	smart-8cb05ca3-10dc-4b0c-ab7b-b6a9e643d3cb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758640779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux. 3758640779
Directory	/workspace/44.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/44.lc_ctrl_security_escalation.1682513284
Short name	T227
Test name
Test status
Simulation time	1333344550 ps
CPU time	12.85 seconds
Started	Apr 28 12:54:24 PM PDT 24
Finished	Apr 28 12:54:38 PM PDT 24
Peak memory	217900 kb
Host	smart-70772dff-84d4-4113-b02c-22b30292696f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682513284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1682513284
Directory	/workspace/44.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/44.lc_ctrl_smoke.2542359972
Short name	T806
Test name
Test status
Simulation time	59283109 ps
CPU time	2.31 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 12:54:26 PM PDT 24
Peak memory	217916 kb
Host	smart-df443422-a2a6-49bb-a4ea-f9a2c862df84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542359972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2542359972
Directory	/workspace/44.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_failure.3650751414
Short name	T306
Test name
Test status
Simulation time	770684421 ps
CPU time	22.65 seconds
Started	Apr 28 12:54:22 PM PDT 24
Finished	Apr 28 12:54:46 PM PDT 24
Peak memory	246112 kb
Host	smart-4dae5138-7ba1-470c-94ad-6ea9235cd0ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650751414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3650751414
Directory	/workspace/44.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_post_trans.2128863364
Short name	T555
Test name
Test status
Simulation time	46941612 ps
CPU time	5.71 seconds
Started	Apr 28 12:54:24 PM PDT 24
Finished	Apr 28 12:54:31 PM PDT 24
Peak memory	242640 kb
Host	smart-bd828d68-9837-4796-a20e-df1c01ed04d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128863364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2128863364
Directory	/workspace/44.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all.4076811781
Short name	T650
Test name
Test status
Simulation time	286313257 ps
CPU time	15 seconds
Started	Apr 28 12:54:24 PM PDT 24
Finished	Apr 28 12:54:40 PM PDT 24
Peak memory	225896 kb
Host	smart-b5959f93-5be7-4b84-b5e2-15385cde3d50
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076811781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.4076811781
Directory	/workspace/44.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2001304206
Short name	T151
Test name
Test status
Simulation time	39205802781 ps
CPU time	536.73 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 01:03:20 PM PDT 24
Peak memory	332908 kb
Host	smart-c995d416-84e9-4a3a-b69a-c31d6d2d5610
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2001304206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2001304206
Directory	/workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1516708233
Short name	T812
Test name
Test status
Simulation time	43261861 ps
CPU time	0.73 seconds
Started	Apr 28 12:54:22 PM PDT 24
Finished	Apr 28 12:54:24 PM PDT 24
Peak memory	207100 kb
Host	smart-bf709fa5-d7b0-4957-8273-b449f8afe503
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516708233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c trl_volatile_unlock_smoke.1516708233
Directory	/workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_alert_test.1692241612
Short name	T427
Test name
Test status
Simulation time	26815202 ps
CPU time	1.03 seconds
Started	Apr 28 12:54:30 PM PDT 24
Finished	Apr 28 12:54:31 PM PDT 24
Peak memory	209440 kb
Host	smart-cc6500b5-4d6f-4463-96c1-45e66aa8930b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692241612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1692241612
Directory	/workspace/45.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.lc_ctrl_errors.75368076
Short name	T495
Test name
Test status
Simulation time	4537803686 ps
CPU time	16.88 seconds
Started	Apr 28 12:54:25 PM PDT 24
Finished	Apr 28 12:54:42 PM PDT 24
Peak memory	217912 kb
Host	smart-f97c890b-8b93-4ffc-9c1e-badc8a2c65dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75368076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.75368076
Directory	/workspace/45.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/45.lc_ctrl_jtag_access.3153233047
Short name	T480
Test name
Test status
Simulation time	507144647 ps
CPU time	6.34 seconds
Started	Apr 28 12:54:30 PM PDT 24
Finished	Apr 28 12:54:37 PM PDT 24
Peak memory	209380 kb
Host	smart-0d89f550-3a0d-4a3f-a741-8f8330c0eb52
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153233047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3153233047
Directory	/workspace/45.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/45.lc_ctrl_prog_failure.2889314304
Short name	T602
Test name
Test status
Simulation time	65721940 ps
CPU time	3.51 seconds
Started	Apr 28 12:54:24 PM PDT 24
Finished	Apr 28 12:54:29 PM PDT 24
Peak memory	217768 kb
Host	smart-566be793-67a9-4157-bd77-33efb2781c5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889314304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2889314304
Directory	/workspace/45.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_mubi.2016220358
Short name	T572
Test name
Test status
Simulation time	2824941962 ps
CPU time	13.56 seconds
Started	Apr 28 12:54:29 PM PDT 24
Finished	Apr 28 12:54:43 PM PDT 24
Peak memory	218832 kb
Host	smart-7c9cdd65-d0d9-42e5-b9db-7ce5cd4ef15a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016220358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2016220358
Directory	/workspace/45.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_digest.2219455788
Short name	T502
Test name
Test status
Simulation time	242208791 ps
CPU time	10.95 seconds
Started	Apr 28 12:54:27 PM PDT 24
Finished	Apr 28 12:54:38 PM PDT 24
Peak memory	217800 kb
Host	smart-d403eb2b-c872-43fe-bf04-63c806153a8a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219455788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d igest.2219455788
Directory	/workspace/45.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_mux.1644150895
Short name	T847
Test name
Test status
Simulation time	733849751 ps
CPU time	7.3 seconds
Started	Apr 28 12:54:33 PM PDT 24
Finished	Apr 28 12:54:41 PM PDT 24
Peak memory	217900 kb
Host	smart-49f83f7b-850e-4f3d-ab3f-d75a6eff773a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644150895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux. 1644150895
Directory	/workspace/45.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/45.lc_ctrl_security_escalation.1450877811
Short name	T782
Test name
Test status
Simulation time	825282618 ps
CPU time	15.38 seconds
Started	Apr 28 12:54:23 PM PDT 24
Finished	Apr 28 12:54:39 PM PDT 24
Peak memory	217788 kb
Host	smart-2b3d6760-d461-49bb-87f7-07e113bbd1ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450877811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1450877811
Directory	/workspace/45.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/45.lc_ctrl_smoke.64539353
Short name	T641
Test name
Test status
Simulation time	230155224 ps
CPU time	2.15 seconds
Started	Apr 28 12:54:20 PM PDT 24
Finished	Apr 28 12:54:23 PM PDT 24
Peak memory	213752 kb
Host	smart-7a3d0bc2-5bd1-4b63-b880-24ddfab9aacf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64539353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.64539353
Directory	/workspace/45.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_failure.3134672086
Short name	T612
Test name
Test status
Simulation time	1062937164 ps
CPU time	30.01 seconds
Started	Apr 28 12:54:25 PM PDT 24
Finished	Apr 28 12:54:55 PM PDT 24
Peak memory	250748 kb
Host	smart-b2189046-9994-47fe-9753-3ee0a5b0f380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134672086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3134672086
Directory	/workspace/45.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_post_trans.306212704
Short name	T354
Test name
Test status
Simulation time	54650296 ps
CPU time	7.55 seconds
Started	Apr 28 12:54:21 PM PDT 24
Finished	Apr 28 12:54:30 PM PDT 24
Peak memory	246176 kb
Host	smart-61adc2bb-d948-4b38-a68e-dc14215a64b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306212704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.306212704
Directory	/workspace/45.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all.520620069
Short name	T871
Test name
Test status
Simulation time	1638166522 ps
CPU time	36.11 seconds
Started	Apr 28 12:54:27 PM PDT 24
Finished	Apr 28 12:55:04 PM PDT 24
Peak memory	250720 kb
Host	smart-596bc374-c54d-4a27-b7a7-b964cdfa4f3a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520620069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.520620069
Directory	/workspace/45.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2671551444
Short name	T88
Test name
Test status
Simulation time	44103680366 ps
CPU time	1318.76 seconds
Started	Apr 28 12:54:30 PM PDT 24
Finished	Apr 28 01:16:30 PM PDT 24
Peak memory	365644 kb
Host	smart-147376a9-56f9-4ad6-8b2c-5605e4ec00dd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2671551444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2671551444
Directory	/workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2187795500
Short name	T445
Test name
Test status
Simulation time	140380252 ps
CPU time	0.92 seconds
Started	Apr 28 12:54:21 PM PDT 24
Finished	Apr 28 12:54:23 PM PDT 24
Peak memory	211476 kb
Host	smart-9bc77c03-bc4a-4b32-b18a-8b360d7f867d
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187795500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c trl_volatile_unlock_smoke.2187795500
Directory	/workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_alert_test.3620206354
Short name	T825
Test name
Test status
Simulation time	40818906 ps
CPU time	0.94 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:34 PM PDT 24
Peak memory	209420 kb
Host	smart-b90ec904-1efa-4d51-8009-654021ed0fb5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620206354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3620206354
Directory	/workspace/46.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.lc_ctrl_errors.877807075
Short name	T674
Test name
Test status
Simulation time	2058845123 ps
CPU time	14.16 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:47 PM PDT 24
Peak memory	217832 kb
Host	smart-0b78528c-7f84-4d1b-9651-e7c00d2719c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877807075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.877807075
Directory	/workspace/46.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/46.lc_ctrl_jtag_access.2171242604
Short name	T750
Test name
Test status
Simulation time	310564880 ps
CPU time	8.4 seconds
Started	Apr 28 12:54:28 PM PDT 24
Finished	Apr 28 12:54:38 PM PDT 24
Peak memory	209356 kb
Host	smart-a9d39759-5410-4dfa-b368-af0fede3aad4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171242604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2171242604
Directory	/workspace/46.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/46.lc_ctrl_prog_failure.2919494717
Short name	T601
Test name
Test status
Simulation time	22922764 ps
CPU time	1.6 seconds
Started	Apr 28 12:54:29 PM PDT 24
Finished	Apr 28 12:54:31 PM PDT 24
Peak memory	217820 kb
Host	smart-95c6ce01-9d16-4547-ad09-7857ba14397f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919494717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2919494717
Directory	/workspace/46.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_mubi.2246088135
Short name	T709
Test name
Test status
Simulation time	1931152118 ps
CPU time	14.58 seconds
Started	Apr 28 12:54:29 PM PDT 24
Finished	Apr 28 12:54:44 PM PDT 24
Peak memory	225956 kb
Host	smart-3d4c3672-f7dc-4dcb-9796-963d93f85785
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246088135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2246088135
Directory	/workspace/46.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_digest.343940160
Short name	T241
Test name
Test status
Simulation time	344570806 ps
CPU time	13.18 seconds
Started	Apr 28 12:54:28 PM PDT 24
Finished	Apr 28 12:54:42 PM PDT 24
Peak memory	217776 kb
Host	smart-35517332-2e28-4c53-ba7c-8735753bc2e9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343940160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di gest.343940160
Directory	/workspace/46.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_mux.423160231
Short name	T762
Test name
Test status
Simulation time	1121725421 ps
CPU time	10.17 seconds
Started	Apr 28 12:54:31 PM PDT 24
Finished	Apr 28 12:54:41 PM PDT 24
Peak memory	217916 kb
Host	smart-9d5ef324-9f81-4e8d-9341-bcd89983bb5e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423160231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.423160231
Directory	/workspace/46.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/46.lc_ctrl_security_escalation.1708434681
Short name	T472
Test name
Test status
Simulation time	7063991363 ps
CPU time	13.28 seconds
Started	Apr 28 12:54:31 PM PDT 24
Finished	Apr 28 12:54:45 PM PDT 24
Peak memory	217984 kb
Host	smart-642d24ac-2ec0-4af0-bf7a-58401f7787b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708434681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1708434681
Directory	/workspace/46.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/46.lc_ctrl_smoke.2858553762
Short name	T381
Test name
Test status
Simulation time	302222218 ps
CPU time	2.99 seconds
Started	Apr 28 12:54:28 PM PDT 24
Finished	Apr 28 12:54:31 PM PDT 24
Peak memory	217620 kb
Host	smart-c11be3be-789e-430e-88ec-ac2d2d3a39a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858553762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2858553762
Directory	/workspace/46.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_failure.4179726010
Short name	T14
Test name
Test status
Simulation time	2805323804 ps
CPU time	26.87 seconds
Started	Apr 28 12:54:30 PM PDT 24
Finished	Apr 28 12:54:57 PM PDT 24
Peak memory	250956 kb
Host	smart-e23e23ad-9101-485c-a227-525c572a7acb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179726010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4179726010
Directory	/workspace/46.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_post_trans.641802814
Short name	T540
Test name
Test status
Simulation time	124575660 ps
CPU time	3.32 seconds
Started	Apr 28 12:54:29 PM PDT 24
Finished	Apr 28 12:54:33 PM PDT 24
Peak memory	226220 kb
Host	smart-176e07c9-33fb-4c01-8709-b7581c8da7c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641802814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.641802814
Directory	/workspace/46.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/46.lc_ctrl_stress_all.2745878456
Short name	T407
Test name
Test status
Simulation time	25007015804 ps
CPU time	159.26 seconds
Started	Apr 28 12:54:33 PM PDT 24
Finished	Apr 28 12:57:13 PM PDT 24
Peak memory	219372 kb
Host	smart-792a6451-d762-4847-bacc-70cc05f76fc8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745878456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.2745878456
Directory	/workspace/46.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3488540364
Short name	T570
Test name
Test status
Simulation time	60420163 ps
CPU time	0.99 seconds
Started	Apr 28 12:54:29 PM PDT 24
Finished	Apr 28 12:54:31 PM PDT 24
Peak memory	211388 kb
Host	smart-c8043876-7318-47d9-a25d-6ee71d61afa4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488540364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c trl_volatile_unlock_smoke.3488540364
Directory	/workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_alert_test.1706941839
Short name	T74
Test name
Test status
Simulation time	181909297 ps
CPU time	1.16 seconds
Started	Apr 28 12:54:31 PM PDT 24
Finished	Apr 28 12:54:33 PM PDT 24
Peak memory	209324 kb
Host	smart-8a1fe7b3-15b3-4b19-ad9e-b50f7e021cb4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706941839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1706941839
Directory	/workspace/47.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.lc_ctrl_errors.808902433
Short name	T712
Test name
Test status
Simulation time	962264491 ps
CPU time	11.69 seconds
Started	Apr 28 12:54:33 PM PDT 24
Finished	Apr 28 12:54:46 PM PDT 24
Peak memory	217836 kb
Host	smart-259ce484-69c9-49c6-b472-e164c33a4f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808902433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.808902433
Directory	/workspace/47.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/47.lc_ctrl_jtag_access.2708044480
Short name	T476
Test name
Test status
Simulation time	163371604 ps
CPU time	3.74 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:36 PM PDT 24
Peak memory	209464 kb
Host	smart-0c6269e2-d432-4c1e-b9dc-888b9edbe083
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708044480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2708044480
Directory	/workspace/47.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/47.lc_ctrl_prog_failure.1453167694
Short name	T610
Test name
Test status
Simulation time	97270869 ps
CPU time	3.11 seconds
Started	Apr 28 12:54:41 PM PDT 24
Finished	Apr 28 12:54:45 PM PDT 24
Peak memory	217836 kb
Host	smart-9bb618ab-4162-46e0-8384-fdd9e0b47da4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453167694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1453167694
Directory	/workspace/47.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_mubi.1021028253
Short name	T525
Test name
Test status
Simulation time	537742147 ps
CPU time	11.88 seconds
Started	Apr 28 12:54:43 PM PDT 24
Finished	Apr 28 12:54:56 PM PDT 24
Peak memory	225864 kb
Host	smart-af1fad5d-8c72-4496-b8b0-50856eb6d623
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021028253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1021028253
Directory	/workspace/47.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_digest.1204001925
Short name	T271
Test name
Test status
Simulation time	479917960 ps
CPU time	9.37 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:42 PM PDT 24
Peak memory	217856 kb
Host	smart-3ce7e0c3-7751-4a95-a3a5-0a199acf81cb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204001925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d igest.1204001925
Directory	/workspace/47.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_mux.1100892204
Short name	T768
Test name
Test status
Simulation time	1197536973 ps
CPU time	9.04 seconds
Started	Apr 28 12:54:35 PM PDT 24
Finished	Apr 28 12:54:44 PM PDT 24
Peak memory	217824 kb
Host	smart-14744ec6-8559-4680-8897-0448ef84aa4b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100892204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux. 1100892204
Directory	/workspace/47.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/47.lc_ctrl_security_escalation.1239192808
Short name	T592
Test name
Test status
Simulation time	815262657 ps
CPU time	8.78 seconds
Started	Apr 28 12:54:35 PM PDT 24
Finished	Apr 28 12:54:44 PM PDT 24
Peak memory	217820 kb
Host	smart-3c3468ac-0a51-4b64-8dd2-905c3cba87a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239192808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1239192808
Directory	/workspace/47.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/47.lc_ctrl_smoke.3488358314
Short name	T479
Test name
Test status
Simulation time	294710567 ps
CPU time	4.48 seconds
Started	Apr 28 12:54:34 PM PDT 24
Finished	Apr 28 12:54:39 PM PDT 24
Peak memory	217724 kb
Host	smart-c29a8e6b-1f69-4625-93aa-279cfe13fa40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488358314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3488358314
Directory	/workspace/47.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_failure.1283250668
Short name	T337
Test name
Test status
Simulation time	194062553 ps
CPU time	26.76 seconds
Started	Apr 28 12:54:36 PM PDT 24
Finished	Apr 28 12:55:04 PM PDT 24
Peak memory	250764 kb
Host	smart-69103147-4948-4803-b5d0-364668b92064
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283250668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1283250668
Directory	/workspace/47.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_post_trans.4021140361
Short name	T646
Test name
Test status
Simulation time	298822356 ps
CPU time	3.48 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:36 PM PDT 24
Peak memory	226244 kb
Host	smart-cc8a035f-774b-40c3-ab29-92fa7d2a3179
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021140361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4021140361
Directory	/workspace/47.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/47.lc_ctrl_stress_all.715394718
Short name	T797
Test name
Test status
Simulation time	12292650816 ps
CPU time	68.75 seconds
Started	Apr 28 12:54:43 PM PDT 24
Finished	Apr 28 12:55:53 PM PDT 24
Peak memory	250916 kb
Host	smart-896ffa7b-4b7f-4b1c-884b-4d4e115cbf00
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715394718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.715394718
Directory	/workspace/47.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1545480277
Short name	T95
Test name
Test status
Simulation time	15968900252 ps
CPU time	246.47 seconds
Started	Apr 28 12:54:35 PM PDT 24
Finished	Apr 28 12:58:42 PM PDT 24
Peak memory	273168 kb
Host	smart-6d4e65b2-e181-49fb-b5ba-500996ac99a4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1545480277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1545480277
Directory	/workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2153850662
Short name	T854
Test name
Test status
Simulation time	22142722 ps
CPU time	1.04 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:33 PM PDT 24
Peak memory	212536 kb
Host	smart-9cc0834a-7214-485c-ac3c-be27f43989dc
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153850662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c trl_volatile_unlock_smoke.2153850662
Directory	/workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_alert_test.901983142
Short name	T438
Test name
Test status
Simulation time	34277450 ps
CPU time	0.84 seconds
Started	Apr 28 12:54:35 PM PDT 24
Finished	Apr 28 12:54:36 PM PDT 24
Peak memory	209176 kb
Host	smart-7a43dbd4-d670-42bf-b42e-8ca7849980e3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901983142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.901983142
Directory	/workspace/48.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.lc_ctrl_errors.2715414667
Short name	T587
Test name
Test status
Simulation time	343427097 ps
CPU time	13.39 seconds
Started	Apr 28 12:54:37 PM PDT 24
Finished	Apr 28 12:54:51 PM PDT 24
Peak memory	217744 kb
Host	smart-8f716bf8-b64a-4999-b792-c218ea692fab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715414667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2715414667
Directory	/workspace/48.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/48.lc_ctrl_jtag_access.1187506444
Short name	T556
Test name
Test status
Simulation time	778205893 ps
CPU time	18.24 seconds
Started	Apr 28 12:54:43 PM PDT 24
Finished	Apr 28 12:55:03 PM PDT 24
Peak memory	217116 kb
Host	smart-5d0f71a9-88f9-48f5-ab87-f86c3b40f98d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187506444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1187506444
Directory	/workspace/48.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/48.lc_ctrl_prog_failure.3914928032
Short name	T362
Test name
Test status
Simulation time	162447539 ps
CPU time	2.33 seconds
Started	Apr 28 12:54:36 PM PDT 24
Finished	Apr 28 12:54:40 PM PDT 24
Peak memory	217772 kb
Host	smart-23875a45-5791-44fb-bafc-d7174933ed2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3914928032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3914928032
Directory	/workspace/48.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_mubi.369500639
Short name	T807
Test name
Test status
Simulation time	304520733 ps
CPU time	13.84 seconds
Started	Apr 28 12:54:33 PM PDT 24
Finished	Apr 28 12:54:48 PM PDT 24
Peak memory	225952 kb
Host	smart-5359ac79-6d5d-4749-ac7b-bf7e48e75679
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369500639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.369500639
Directory	/workspace/48.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_digest.1226161773
Short name	T346
Test name
Test status
Simulation time	405985905 ps
CPU time	11.61 seconds
Started	Apr 28 12:54:34 PM PDT 24
Finished	Apr 28 12:54:46 PM PDT 24
Peak memory	217900 kb
Host	smart-ba52193b-d14a-4da3-9bde-4c7c593ebf55
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226161773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d igest.1226161773
Directory	/workspace/48.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_mux.1059834255
Short name	T345
Test name
Test status
Simulation time	388010722 ps
CPU time	9.43 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:42 PM PDT 24
Peak memory	217924 kb
Host	smart-f02f730f-8438-41de-bd78-ac9c048aae9f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059834255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux. 1059834255
Directory	/workspace/48.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/48.lc_ctrl_security_escalation.363512731
Short name	T417
Test name
Test status
Simulation time	500500350 ps
CPU time	10.58 seconds
Started	Apr 28 12:54:41 PM PDT 24
Finished	Apr 28 12:54:52 PM PDT 24
Peak memory	217832 kb
Host	smart-84f2479d-0787-41e9-9eae-2ff02d040a25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363512731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.363512731
Directory	/workspace/48.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/48.lc_ctrl_smoke.714924777
Short name	T786
Test name
Test status
Simulation time	114421884 ps
CPU time	2.04 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:35 PM PDT 24
Peak memory	213840 kb
Host	smart-cba2f14e-b6f6-4a73-8833-914a83f2f40e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714924777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.714924777
Directory	/workspace/48.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_failure.3577226666
Short name	T732
Test name
Test status
Simulation time	1506850899 ps
CPU time	28.19 seconds
Started	Apr 28 12:54:37 PM PDT 24
Finished	Apr 28 12:55:07 PM PDT 24
Peak memory	250564 kb
Host	smart-ae2697b1-ff91-4b4b-b0e1-5dc614fe061c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577226666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3577226666
Directory	/workspace/48.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_post_trans.1522797542
Short name	T387
Test name
Test status
Simulation time	93183944 ps
CPU time	6.99 seconds
Started	Apr 28 12:54:34 PM PDT 24
Finished	Apr 28 12:54:42 PM PDT 24
Peak memory	246404 kb
Host	smart-672faa6a-cae9-4a7d-b7e2-e71403fdced9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522797542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1522797542
Directory	/workspace/48.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all.189102282
Short name	T671
Test name
Test status
Simulation time	12819331914 ps
CPU time	132.08 seconds
Started	Apr 28 12:54:33 PM PDT 24
Finished	Apr 28 12:56:46 PM PDT 24
Peak memory	269668 kb
Host	smart-f52692dd-67fe-4f43-95bc-2062247b1123
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189102282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all.189102282
Directory	/workspace/48.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2704416579
Short name	T303
Test name
Test status
Simulation time	45806369 ps
CPU time	0.91 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:34 PM PDT 24
Peak memory	208456 kb
Host	smart-7b5d32f9-ab68-4e40-b543-4f8632ba04da
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704416579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c trl_volatile_unlock_smoke.2704416579
Directory	/workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_alert_test.2874142883
Short name	T878
Test name
Test status
Simulation time	15990412 ps
CPU time	0.93 seconds
Started	Apr 28 12:54:35 PM PDT 24
Finished	Apr 28 12:54:37 PM PDT 24
Peak memory	209376 kb
Host	smart-2ff9bee7-bb4e-4474-a7b3-b507bbd6fcee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874142883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2874142883
Directory	/workspace/49.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.lc_ctrl_errors.2698129534
Short name	T623
Test name
Test status
Simulation time	803594281 ps
CPU time	10.15 seconds
Started	Apr 28 12:54:37 PM PDT 24
Finished	Apr 28 12:54:48 PM PDT 24
Peak memory	217828 kb
Host	smart-c1ccca69-44df-4d1e-8dcb-7037f7c6d07a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698129534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2698129534
Directory	/workspace/49.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/49.lc_ctrl_jtag_access.2561365498
Short name	T870
Test name
Test status
Simulation time	437672503 ps
CPU time	10.51 seconds
Started	Apr 28 12:54:38 PM PDT 24
Finished	Apr 28 12:54:49 PM PDT 24
Peak memory	209412 kb
Host	smart-4b053e7e-0422-4339-96f3-9c11b823a392
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561365498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2561365498
Directory	/workspace/49.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/49.lc_ctrl_prog_failure.1117240905
Short name	T100
Test name
Test status
Simulation time	91627259 ps
CPU time	3.03 seconds
Started	Apr 28 12:54:36 PM PDT 24
Finished	Apr 28 12:54:40 PM PDT 24
Peak memory	217864 kb
Host	smart-8cf564ff-6e74-4675-9102-5da0ad8823c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117240905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1117240905
Directory	/workspace/49.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_mubi.2222248952
Short name	T355
Test name
Test status
Simulation time	323421070 ps
CPU time	9.15 seconds
Started	Apr 28 12:54:37 PM PDT 24
Finished	Apr 28 12:54:48 PM PDT 24
Peak memory	225884 kb
Host	smart-530e9961-f3fd-45b3-bf4c-3b26c47893ae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222248952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2222248952
Directory	/workspace/49.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_digest.2459666086
Short name	T380
Test name
Test status
Simulation time	1367788540 ps
CPU time	12.02 seconds
Started	Apr 28 12:54:38 PM PDT 24
Finished	Apr 28 12:54:51 PM PDT 24
Peak memory	217780 kb
Host	smart-d968d14c-dd27-49f0-a6f8-16050f40ab09
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459666086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d igest.2459666086
Directory	/workspace/49.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_mux.1767519355
Short name	T399
Test name
Test status
Simulation time	641112515 ps
CPU time	9.22 seconds
Started	Apr 28 12:54:43 PM PDT 24
Finished	Apr 28 12:54:54 PM PDT 24
Peak memory	217752 kb
Host	smart-6c46b41e-3dfc-400c-b568-79012b3dfcc8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767519355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux. 1767519355
Directory	/workspace/49.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/49.lc_ctrl_security_escalation.2837376659
Short name	T872
Test name
Test status
Simulation time	474515257 ps
CPU time	9.8 seconds
Started	Apr 28 12:54:38 PM PDT 24
Finished	Apr 28 12:54:50 PM PDT 24
Peak memory	225840 kb
Host	smart-df5583f8-a87e-42e5-8ff9-fed27df0e033
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2837376659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2837376659
Directory	/workspace/49.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/49.lc_ctrl_smoke.3127619082
Short name	T171
Test name
Test status
Simulation time	72232151 ps
CPU time	2.71 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:35 PM PDT 24
Peak memory	214260 kb
Host	smart-c8989232-096c-4a19-8897-45ad6f0e6de5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127619082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3127619082
Directory	/workspace/49.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_failure.3393503904
Short name	T301
Test name
Test status
Simulation time	194527309 ps
CPU time	22.02 seconds
Started	Apr 28 12:54:41 PM PDT 24
Finished	Apr 28 12:55:04 PM PDT 24
Peak memory	248372 kb
Host	smart-4b6e9133-a7b2-4378-badd-a97e30e6c80a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393503904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3393503904
Directory	/workspace/49.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_post_trans.110763354
Short name	T492
Test name
Test status
Simulation time	626121210 ps
CPU time	3.91 seconds
Started	Apr 28 12:54:35 PM PDT 24
Finished	Apr 28 12:54:40 PM PDT 24
Peak memory	222604 kb
Host	smart-ecabf678-51bb-4316-8b42-73675ea6ef5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110763354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.110763354
Directory	/workspace/49.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all.3020977133
Short name	T729
Test name
Test status
Simulation time	11558871623 ps
CPU time	354.11 seconds
Started	Apr 28 12:54:46 PM PDT 24
Finished	Apr 28 01:00:41 PM PDT 24
Peak memory	279076 kb
Host	smart-f67f9af5-7286-4e4f-bfe3-18a33a3322c8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020977133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.3020977133
Directory	/workspace/49.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3999147546
Short name	T177
Test name
Test status
Simulation time	36050780 ps
CPU time	0.78 seconds
Started	Apr 28 12:54:32 PM PDT 24
Finished	Apr 28 12:54:34 PM PDT 24
Peak memory	208552 kb
Host	smart-758e47eb-47c1-492d-bf90-710d3c95fb6b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999147546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c trl_volatile_unlock_smoke.3999147546
Directory	/workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_alert_test.1848969925
Short name	T636
Test name
Test status
Simulation time	49290839 ps
CPU time	1.01 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:52:21 PM PDT 24
Peak memory	209376 kb
Host	smart-2bcd5054-3a8a-4e5b-a3d9-d6fc1ce886b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848969925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1848969925
Directory	/workspace/5.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.lc_ctrl_claim_transition_if.2634300208
Short name	T823
Test name
Test status
Simulation time	9941018 ps
CPU time	0.95 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:17 PM PDT 24
Peak memory	209428 kb
Host	smart-7eb96ca8-97dd-4b96-9cd2-d1df7ed700cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634300208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2634300208
Directory	/workspace/5.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/5.lc_ctrl_errors.1863954367
Short name	T608
Test name
Test status
Simulation time	351592588 ps
CPU time	14.51 seconds
Started	Apr 28 12:52:17 PM PDT 24
Finished	Apr 28 12:52:33 PM PDT 24
Peak memory	217668 kb
Host	smart-f79ebe21-321f-4f35-b2d9-2d86755a5b5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863954367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1863954367
Directory	/workspace/5.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_access.2194037570
Short name	T25
Test name
Test status
Simulation time	223699025 ps
CPU time	3.36 seconds
Started	Apr 28 12:52:20 PM PDT 24
Finished	Apr 28 12:52:24 PM PDT 24
Peak memory	216760 kb
Host	smart-707b891e-b02b-4e00-9ce3-5854e9c4cebd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194037570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2194037570
Directory	/workspace/5.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_errors.376081877
Short name	T578
Test name
Test status
Simulation time	10793305677 ps
CPU time	72.53 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:53:39 PM PDT 24
Peak memory	218644 kb
Host	smart-2b83bb2d-e8e1-491b-8920-32e76d18ffed
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376081877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err ors.376081877
Directory	/workspace/5.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_priority.3494893709
Short name	T501
Test name
Test status
Simulation time	627013882 ps
CPU time	6.72 seconds
Started	Apr 28 12:52:20 PM PDT 24
Finished	Apr 28 12:52:27 PM PDT 24
Peak memory	216904 kb
Host	smart-c6beac47-77ef-4912-9020-c3d2de142079
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494893709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3 494893709
Directory	/workspace/5.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3135220939
Short name	T193
Test name
Test status
Simulation time	842731615 ps
CPU time	21.81 seconds
Started	Apr 28 12:52:21 PM PDT 24
Finished	Apr 28 12:52:44 PM PDT 24
Peak memory	217856 kb
Host	smart-4fc47b4c-dc8e-4900-b658-87d4dc42519e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135220939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag _prog_failure.3135220939
Directory	/workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.4221259586
Short name	T542
Test name
Test status
Simulation time	4588822157 ps
CPU time	10.89 seconds
Started	Apr 28 12:52:21 PM PDT 24
Finished	Apr 28 12:52:33 PM PDT 24
Peak memory	213508 kb
Host	smart-bdf88005-b171-4bae-8547-ca045143adfa
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221259586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_regwen_during_op.4221259586
Directory	/workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_smoke.181933932
Short name	T474
Test name
Test status
Simulation time	342149663 ps
CPU time	4.06 seconds
Started	Apr 28 12:52:17 PM PDT 24
Finished	Apr 28 12:52:22 PM PDT 24
Peak memory	213280 kb
Host	smart-41ab4f8b-0333-45e2-85e0-122638842224
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181933932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.181933932
Directory	/workspace/5.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1326849017
Short name	T104
Test name
Test status
Simulation time	2712279086 ps
CPU time	69.35 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:53:29 PM PDT 24
Peak memory	275428 kb
Host	smart-b03ae1fb-4f5b-4a84-b2fc-88cbbc4f0f90
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326849017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta g_state_failure.1326849017
Directory	/workspace/5.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.860624278
Short name	T255
Test name
Test status
Simulation time	3795899968 ps
CPU time	17.82 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:52:38 PM PDT 24
Peak memory	250568 kb
Host	smart-a244fc7f-406c-4db9-9a10-46718371ff3f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860624278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j tag_state_post_trans.860624278
Directory	/workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_prog_failure.569133555
Short name	T369
Test name
Test status
Simulation time	259396796 ps
CPU time	2.66 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:19 PM PDT 24
Peak memory	217836 kb
Host	smart-9c16cd73-8bdd-4478-93a0-2683fbb2c7cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569133555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.569133555
Directory	/workspace/5.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_regwen_during_op.3632358991
Short name	T549
Test name
Test status
Simulation time	907737331 ps
CPU time	8.47 seconds
Started	Apr 28 12:52:15 PM PDT 24
Finished	Apr 28 12:52:25 PM PDT 24
Peak memory	214144 kb
Host	smart-95285fcd-5fa1-409e-896b-915d9feac6fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632358991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3632358991
Directory	/workspace/5.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_mubi.443506378
Short name	T32
Test name
Test status
Simulation time	748028052 ps
CPU time	18.52 seconds
Started	Apr 28 12:52:24 PM PDT 24
Finished	Apr 28 12:52:43 PM PDT 24
Peak memory	225308 kb
Host	smart-a15d06f3-86e6-4032-b877-bc56ed35ec28
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443506378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.443506378
Directory	/workspace/5.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_digest.2388674983
Short name	T165
Test name
Test status
Simulation time	1050004005 ps
CPU time	11.98 seconds
Started	Apr 28 12:52:21 PM PDT 24
Finished	Apr 28 12:52:34 PM PDT 24
Peak memory	217888 kb
Host	smart-ce9938c1-042a-4106-bf64-acfd2d4481e8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388674983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di gest.2388674983
Directory	/workspace/5.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_mux.3572463102
Short name	T767
Test name
Test status
Simulation time	427858279 ps
CPU time	8.37 seconds
Started	Apr 28 12:52:21 PM PDT 24
Finished	Apr 28 12:52:30 PM PDT 24
Peak memory	217816 kb
Host	smart-11234c9a-1052-4fad-a249-f2a427283524
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572463102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3 572463102
Directory	/workspace/5.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/5.lc_ctrl_security_escalation.470128821
Short name	T713
Test name
Test status
Simulation time	497659766 ps
CPU time	6.52 seconds
Started	Apr 28 12:52:16 PM PDT 24
Finished	Apr 28 12:52:23 PM PDT 24
Peak memory	223988 kb
Host	smart-49a97726-424b-4404-8938-ac1f5856593f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470128821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.470128821
Directory	/workspace/5.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/5.lc_ctrl_smoke.2004636102
Short name	T394
Test name
Test status
Simulation time	26623293 ps
CPU time	2.1 seconds
Started	Apr 28 12:52:16 PM PDT 24
Finished	Apr 28 12:52:19 PM PDT 24
Peak memory	213596 kb
Host	smart-9026fa46-41ac-4c81-8d5e-62eeefb1fb82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004636102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2004636102
Directory	/workspace/5.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_failure.1484888701
Short name	T771
Test name
Test status
Simulation time	1440746418 ps
CPU time	19.27 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:52:38 PM PDT 24
Peak memory	250756 kb
Host	smart-2c1426b7-d7e3-423e-a043-c30bf2f03db7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484888701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1484888701
Directory	/workspace/5.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_post_trans.3248407282
Short name	T295
Test name
Test status
Simulation time	572164176 ps
CPU time	9.65 seconds
Started	Apr 28 12:52:17 PM PDT 24
Finished	Apr 28 12:52:28 PM PDT 24
Peak memory	248736 kb
Host	smart-3eda3086-ad06-4b89-bc7a-3b774f5f6ede
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248407282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3248407282
Directory	/workspace/5.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all.2020714799
Short name	T420
Test name
Test status
Simulation time	16663328873 ps
CPU time	113.84 seconds
Started	Apr 28 12:52:21 PM PDT 24
Finished	Apr 28 12:54:16 PM PDT 24
Peak memory	280200 kb
Host	smart-b9bcb127-9d15-4ae6-aab4-84c82c8afe45
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020714799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.2020714799
Directory	/workspace/5.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.767405766
Short name	T40
Test name
Test status
Simulation time	26020280 ps
CPU time	0.94 seconds
Started	Apr 28 12:52:14 PM PDT 24
Finished	Apr 28 12:52:16 PM PDT 24
Peak memory	211460 kb
Host	smart-1050efb8-898e-48e8-967d-3ac002d15f57
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767405766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr l_volatile_unlock_smoke.767405766
Directory	/workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_alert_test.3327794754
Short name	T359
Test name
Test status
Simulation time	23287230 ps
CPU time	1.22 seconds
Started	Apr 28 12:52:29 PM PDT 24
Finished	Apr 28 12:52:31 PM PDT 24
Peak memory	209292 kb
Host	smart-fe193b28-ada6-4bf7-b4b7-4a35367af79a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327794754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3327794754
Directory	/workspace/6.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.lc_ctrl_errors.2402517093
Short name	T289
Test name
Test status
Simulation time	1279025752 ps
CPU time	18.6 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:43 PM PDT 24
Peak memory	217792 kb
Host	smart-7946c36f-8cdf-4d3c-ac4d-2c5388b1ecf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402517093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2402517093
Directory	/workspace/6.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_access.2735300565
Short name	T705
Test name
Test status
Simulation time	527318218 ps
CPU time	7.81 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:32 PM PDT 24
Peak memory	217028 kb
Host	smart-6e62b6c3-4457-4c46-94e9-6c2032aa8aea
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735300565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2735300565
Directory	/workspace/6.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_errors.928460551
Short name	T541
Test name
Test status
Simulation time	2982037853 ps
CPU time	75.22 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:53:42 PM PDT 24
Peak memory	218868 kb
Host	smart-a05f7445-6c80-4f98-9087-4d58d085292e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928460551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err ors.928460551
Directory	/workspace/6.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_priority.2392269196
Short name	T790
Test name
Test status
Simulation time	606759918 ps
CPU time	2.32 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:26 PM PDT 24
Peak memory	217020 kb
Host	smart-1a4354e2-1c57-462a-8887-2ee70b4b27f4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392269196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2 392269196
Directory	/workspace/6.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.739811289
Short name	T819
Test name
Test status
Simulation time	594329806 ps
CPU time	9.41 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	217540 kb
Host	smart-85eaa808-0a92-4209-819e-074153104f58
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739811289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ prog_failure.739811289
Directory	/workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2046911165
Short name	T465
Test name
Test status
Simulation time	3285946231 ps
CPU time	12.26 seconds
Started	Apr 28 12:52:21 PM PDT 24
Finished	Apr 28 12:52:34 PM PDT 24
Peak memory	213360 kb
Host	smart-b097d7bb-8eda-41e0-bb19-e821d265879d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046911165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_regwen_during_op.2046911165
Directory	/workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_smoke.2768668714
Short name	T828
Test name
Test status
Simulation time	445459187 ps
CPU time	3.65 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:30 PM PDT 24
Peak memory	213016 kb
Host	smart-370115eb-d4ee-4e00-ac8a-0f173a45dbac
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768668714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke. 2768668714
Directory	/workspace/6.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_failure.451944232
Short name	T511
Test name
Test status
Simulation time	6799180415 ps
CPU time	102.77 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:54:03 PM PDT 24
Peak memory	276024 kb
Host	smart-03be68d1-90b1-4256-8ab6-4dbbc8dfdf83
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451944232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag _state_failure.451944232
Directory	/workspace/6.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1985266539
Short name	T559
Test name
Test status
Simulation time	3626907655 ps
CPU time	20.18 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	250828 kb
Host	smart-3e8e8d51-e60c-4592-b532-c49abc227f77
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985266539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_state_post_trans.1985266539
Directory	/workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_prog_failure.120746635
Short name	T589
Test name
Test status
Simulation time	107723611 ps
CPU time	1.73 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:28 PM PDT 24
Peak memory	217992 kb
Host	smart-b20514e2-74d2-482a-8250-0f74f612786c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120746635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.120746635
Directory	/workspace/6.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_regwen_during_op.549498346
Short name	T80
Test name
Test status
Simulation time	263041635 ps
CPU time	15.39 seconds
Started	Apr 28 12:52:21 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	214176 kb
Host	smart-1ecc668f-e001-448d-b65f-e8d78db1e035
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=549498346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.549498346
Directory	/workspace/6.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_mubi.3684394010
Short name	T335
Test name
Test status
Simulation time	469515774 ps
CPU time	11.22 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:35 PM PDT 24
Peak memory	217832 kb
Host	smart-28a94ee1-88ea-48d1-8d27-66355871d015
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684394010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3684394010
Directory	/workspace/6.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_digest.4174432950
Short name	T274
Test name
Test status
Simulation time	1236963053 ps
CPU time	14 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:40 PM PDT 24
Peak memory	217852 kb
Host	smart-c46b9d85-ddbb-45f9-92df-73bb5e229c6c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174432950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di gest.4174432950
Directory	/workspace/6.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_mux.3080200870
Short name	T788
Test name
Test status
Simulation time	1534851133 ps
CPU time	13.24 seconds
Started	Apr 28 12:52:24 PM PDT 24
Finished	Apr 28 12:52:38 PM PDT 24
Peak memory	217868 kb
Host	smart-f891437d-02a7-48e6-8e47-bf40b6d186b0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080200870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3 080200870
Directory	/workspace/6.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/6.lc_ctrl_security_escalation.2446720553
Short name	T443
Test name
Test status
Simulation time	583349366 ps
CPU time	8.38 seconds
Started	Apr 28 12:52:22 PM PDT 24
Finished	Apr 28 12:52:31 PM PDT 24
Peak memory	217876 kb
Host	smart-c2474c47-c464-47a3-8b23-4ea76bbafefd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446720553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2446720553
Directory	/workspace/6.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/6.lc_ctrl_smoke.695069192
Short name	T611
Test name
Test status
Simulation time	45550379 ps
CPU time	1.64 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:52:22 PM PDT 24
Peak memory	217656 kb
Host	smart-5fc5743f-b722-4b17-89ba-3a3424e97f7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695069192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.695069192
Directory	/workspace/6.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_failure.938979724
Short name	T781
Test name
Test status
Simulation time	226201451 ps
CPU time	28.21 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:55 PM PDT 24
Peak memory	245508 kb
Host	smart-318fe8f3-25cc-4f93-b847-e8fdcc4aebc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938979724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.938979724
Directory	/workspace/6.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_post_trans.2928609708
Short name	T230
Test name
Test status
Simulation time	56823749 ps
CPU time	5.77 seconds
Started	Apr 28 12:52:19 PM PDT 24
Finished	Apr 28 12:52:26 PM PDT 24
Peak memory	246380 kb
Host	smart-c8092258-301f-4e83-9f88-870c98b16798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2928609708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2928609708
Directory	/workspace/6.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all.2766836536
Short name	T109
Test name
Test status
Simulation time	25381789910 ps
CPU time	167.36 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:55:12 PM PDT 24
Peak memory	291516 kb
Host	smart-3f31ad92-32ca-462f-adb0-b56469ef343e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766836536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.2766836536
Directory	/workspace/6.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3380948855
Short name	T507
Test name
Test status
Simulation time	13668857 ps
CPU time	1 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:25 PM PDT 24
Peak memory	211576 kb
Host	smart-ef782e2c-6085-4f92-9b1f-b21ea25d1b68
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380948855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct rl_volatile_unlock_smoke.3380948855
Directory	/workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_alert_test.1775065053
Short name	T299
Test name
Test status
Simulation time	60882278 ps
CPU time	0.91 seconds
Started	Apr 28 12:52:27 PM PDT 24
Finished	Apr 28 12:52:29 PM PDT 24
Peak memory	209308 kb
Host	smart-76f8c45c-9a1a-4682-9989-e4b85dd1e0e4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775065053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1775065053
Directory	/workspace/7.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.lc_ctrl_errors.2846989735
Short name	T832
Test name
Test status
Simulation time	1269986084 ps
CPU time	10.22 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:37 PM PDT 24
Peak memory	217856 kb
Host	smart-a3c6a0f2-ba35-4554-96b9-5d198689a8cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846989735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2846989735
Directory	/workspace/7.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_access.1215519006
Short name	T482
Test name
Test status
Simulation time	556681518 ps
CPU time	4.64 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:31 PM PDT 24
Peak memory	209368 kb
Host	smart-489164d3-0b5b-4551-97a4-c51cdf21f013
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215519006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1215519006
Directory	/workspace/7.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_errors.2731241686
Short name	T106
Test name
Test status
Simulation time	4656358070 ps
CPU time	36.23 seconds
Started	Apr 28 12:52:24 PM PDT 24
Finished	Apr 28 12:53:01 PM PDT 24
Peak memory	218416 kb
Host	smart-5cb2eedf-68b7-4e08-b01f-aaa26ecbfb34
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731241686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er rors.2731241686
Directory	/workspace/7.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_priority.2721527071
Short name	T626
Test name
Test status
Simulation time	811864463 ps
CPU time	3.08 seconds
Started	Apr 28 12:52:24 PM PDT 24
Finished	Apr 28 12:52:29 PM PDT 24
Peak memory	216960 kb
Host	smart-bf26bcec-05dc-43c2-9697-e1063a9abcb4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721527071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2 721527071
Directory	/workspace/7.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3937073887
Short name	T839
Test name
Test status
Simulation time	2227109612 ps
CPU time	7.88 seconds
Started	Apr 28 12:52:28 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	217892 kb
Host	smart-2156c87c-f448-4aed-9449-f66202223709
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937073887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag _prog_failure.3937073887
Directory	/workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1925686260
Short name	T278
Test name
Test status
Simulation time	846029367 ps
CPU time	11.62 seconds
Started	Apr 28 12:52:28 PM PDT 24
Finished	Apr 28 12:52:40 PM PDT 24
Peak memory	213000 kb
Host	smart-212de4b7-4114-4a8d-8db8-c194d97ee349
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925686260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_regwen_during_op.1925686260
Directory	/workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_smoke.2921915345
Short name	T72
Test name
Test status
Simulation time	213744258 ps
CPU time	6.74 seconds
Started	Apr 28 12:52:24 PM PDT 24
Finished	Apr 28 12:52:32 PM PDT 24
Peak memory	213456 kb
Host	smart-4ffd0a6e-1f58-4471-90c7-4972e2077f3a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921915345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke. 2921915345
Directory	/workspace/7.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_failure.229135985
Short name	T410
Test name
Test status
Simulation time	4017068250 ps
CPU time	48.47 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:53:15 PM PDT 24
Peak memory	267016 kb
Host	smart-18e4e892-cde1-4521-b7bf-4f164eb9cdeb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229135985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag _state_failure.229135985
Directory	/workspace/7.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.988350273
Short name	T232
Test name
Test status
Simulation time	589229969 ps
CPU time	23.34 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:55 PM PDT 24
Peak memory	250768 kb
Host	smart-683ea037-8f8d-48d8-a0b3-d92ea12ab332
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988350273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j tag_state_post_trans.988350273
Directory	/workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_prog_failure.1577403554
Short name	T365
Test name
Test status
Simulation time	76863731 ps
CPU time	2.45 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:27 PM PDT 24
Peak memory	217900 kb
Host	smart-e8dafadf-84e7-4c9c-bfd6-1498a2fabf25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577403554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1577403554
Directory	/workspace/7.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_regwen_during_op.3954339450
Short name	T753
Test name
Test status
Simulation time	470698663 ps
CPU time	5.8 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:30 PM PDT 24
Peak memory	217644 kb
Host	smart-f00152fe-2b10-4172-b196-429c34b67899
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954339450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3954339450
Directory	/workspace/7.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_mubi.679465860
Short name	T464
Test name
Test status
Simulation time	1200322777 ps
CPU time	9.97 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:34 PM PDT 24
Peak memory	217820 kb
Host	smart-5eaad682-571b-4700-b5a5-511c17141195
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679465860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.679465860
Directory	/workspace/7.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_digest.32311177
Short name	T281
Test name
Test status
Simulation time	412132855 ps
CPU time	9.92 seconds
Started	Apr 28 12:52:23 PM PDT 24
Finished	Apr 28 12:52:35 PM PDT 24
Peak memory	217796 kb
Host	smart-bf15df60-539f-486a-a5ca-897eb741ed01
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32311177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dige st.32311177
Directory	/workspace/7.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_mux.41304553
Short name	T246
Test name
Test status
Simulation time	374031047 ps
CPU time	9.5 seconds
Started	Apr 28 12:52:24 PM PDT 24
Finished	Apr 28 12:52:34 PM PDT 24
Peak memory	217776 kb
Host	smart-4a72011d-fb11-48e4-9549-d36d17694540
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41304553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.41304553
Directory	/workspace/7.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/7.lc_ctrl_security_escalation.1599681662
Short name	T440
Test name
Test status
Simulation time	273763560 ps
CPU time	10.96 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:42 PM PDT 24
Peak memory	225280 kb
Host	smart-0ff895b9-7a5f-4a2c-b7e2-1b8d46e69e6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599681662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1599681662
Directory	/workspace/7.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/7.lc_ctrl_smoke.2608470765
Short name	T801
Test name
Test status
Simulation time	50425310 ps
CPU time	1.75 seconds
Started	Apr 28 12:52:29 PM PDT 24
Finished	Apr 28 12:52:32 PM PDT 24
Peak memory	217768 kb
Host	smart-ffc844dc-6525-412b-9585-6313bfc28713
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608470765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2608470765
Directory	/workspace/7.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_failure.2762694369
Short name	T283
Test name
Test status
Simulation time	150740511 ps
CPU time	18.61 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	250660 kb
Host	smart-9a596568-5e37-44f4-b8ed-c6d210a475cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762694369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2762694369
Directory	/workspace/7.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_post_trans.3402067846
Short name	T783
Test name
Test status
Simulation time	66623479 ps
CPU time	6.13 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:38 PM PDT 24
Peak memory	250288 kb
Host	smart-47706a2c-3243-4566-a48d-4dc31b328dcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402067846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3402067846
Directory	/workspace/7.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all.2754767381
Short name	T663
Test name
Test status
Simulation time	3124089536 ps
CPU time	38.11 seconds
Started	Apr 28 12:52:26 PM PDT 24
Finished	Apr 28 12:53:05 PM PDT 24
Peak memory	250908 kb
Host	smart-7cda92e4-e059-4777-8528-50dd9a074901
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754767381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.2754767381
Directory	/workspace/7.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3363224044
Short name	T96
Test name
Test status
Simulation time	174236445753 ps
CPU time	408.4 seconds
Started	Apr 28 12:52:29 PM PDT 24
Finished	Apr 28 12:59:19 PM PDT 24
Peak memory	308280 kb
Host	smart-cfee02cf-d2aa-48a0-9972-84264aeb76ec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3363224044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.3363224044
Directory	/workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3790422912
Short name	T568
Test name
Test status
Simulation time	72738644 ps
CPU time	0.93 seconds
Started	Apr 28 12:52:24 PM PDT 24
Finished	Apr 28 12:52:26 PM PDT 24
Peak memory	208652 kb
Host	smart-940882b7-8568-4658-b7ea-db481cbfa70e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790422912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_volatile_unlock_smoke.3790422912
Directory	/workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_alert_test.1576565872
Short name	T510
Test name
Test status
Simulation time	19986038 ps
CPU time	1.21 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:33 PM PDT 24
Peak memory	209456 kb
Host	smart-f8b3264e-6be9-4c86-b9e3-22bc715452aa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576565872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1576565872
Directory	/workspace/8.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.lc_ctrl_claim_transition_if.591220579
Short name	T224
Test name
Test status
Simulation time	13774769 ps
CPU time	0.84 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:33 PM PDT 24
Peak memory	209184 kb
Host	smart-9641f533-b885-4ff7-9e1f-9a85cb98835b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591220579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.591220579
Directory	/workspace/8.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/8.lc_ctrl_errors.137206674
Short name	T582
Test name
Test status
Simulation time	3244931427 ps
CPU time	20.1 seconds
Started	Apr 28 12:52:27 PM PDT 24
Finished	Apr 28 12:52:48 PM PDT 24
Peak memory	218792 kb
Host	smart-7ae9c5df-06b6-49a1-9620-8e899da6560c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137206674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.137206674
Directory	/workspace/8.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_access.1180376705
Short name	T170
Test name
Test status
Simulation time	317571449 ps
CPU time	8.1 seconds
Started	Apr 28 12:52:32 PM PDT 24
Finished	Apr 28 12:52:41 PM PDT 24
Peak memory	209320 kb
Host	smart-bbeb8d13-5074-48d5-96be-8b910a8250fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180376705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1180376705
Directory	/workspace/8.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_errors.3528957928
Short name	T56
Test name
Test status
Simulation time	2159823348 ps
CPU time	35.54 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:53:07 PM PDT 24
Peak memory	217852 kb
Host	smart-f568e9cf-a2f6-47d9-b85f-cbebca218aa0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528957928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er rors.3528957928
Directory	/workspace/8.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_priority.3812201468
Short name	T778
Test name
Test status
Simulation time	7684696435 ps
CPU time	8.76 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:44 PM PDT 24
Peak memory	217804 kb
Host	smart-7cbac6d0-11f2-4681-b394-de897a2dd494
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812201468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3 812201468
Directory	/workspace/8.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.795211782
Short name	T481
Test name
Test status
Simulation time	285196048 ps
CPU time	5.28 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	217756 kb
Host	smart-2d9990c3-c0c4-4288-841e-3e2c83ff43ac
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795211782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ prog_failure.795211782
Directory	/workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1017416801
Short name	T66
Test name
Test status
Simulation time	1196600511 ps
CPU time	15.62 seconds
Started	Apr 28 12:52:29 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	213076 kb
Host	smart-4bd20ff7-ff58-47c4-8501-64794e93b50a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017416801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_regwen_during_op.1017416801
Directory	/workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_smoke.3201732454
Short name	T340
Test name
Test status
Simulation time	1018592675 ps
CPU time	7.51 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:34 PM PDT 24
Peak memory	213560 kb
Host	smart-02a1a296-5fd7-4478-9b49-9265fd6cc451
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201732454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke. 3201732454
Directory	/workspace/8.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1423766108
Short name	T528
Test name
Test status
Simulation time	7089921698 ps
CPU time	39.02 seconds
Started	Apr 28 12:52:28 PM PDT 24
Finished	Apr 28 12:53:08 PM PDT 24
Peak memory	272384 kb
Host	smart-d16b56eb-6ad2-4f40-90ba-87644ddd65b2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423766108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta g_state_failure.1423766108
Directory	/workspace/8.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2830148903
Short name	T534
Test name
Test status
Simulation time	4549587197 ps
CPU time	7.43 seconds
Started	Apr 28 12:52:31 PM PDT 24
Finished	Apr 28 12:52:40 PM PDT 24
Peak memory	224424 kb
Host	smart-fab3952c-85f5-402f-ae27-cc6a978e387b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830148903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_state_post_trans.2830148903
Directory	/workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_prog_failure.1226202028
Short name	T675
Test name
Test status
Simulation time	441769675 ps
CPU time	4.37 seconds
Started	Apr 28 12:52:25 PM PDT 24
Finished	Apr 28 12:52:30 PM PDT 24
Peak memory	217764 kb
Host	smart-555f26bd-f023-4a9e-bdac-acac0f8249f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226202028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1226202028
Directory	/workspace/8.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_regwen_during_op.3764652730
Short name	T70
Test name
Test status
Simulation time	179742151 ps
CPU time	4.6 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	217596 kb
Host	smart-0e52052d-588c-48cc-9136-2bad05fcaaab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764652730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3764652730
Directory	/workspace/8.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_mubi.2101661985
Short name	T648
Test name
Test status
Simulation time	591345951 ps
CPU time	13.22 seconds
Started	Apr 28 12:52:31 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	218720 kb
Host	smart-4ed6a88c-c51f-4a9a-b4d0-58b7c19fa22d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101661985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2101661985
Directory	/workspace/8.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_digest.794656467
Short name	T848
Test name
Test status
Simulation time	620229195 ps
CPU time	9.55 seconds
Started	Apr 28 12:52:31 PM PDT 24
Finished	Apr 28 12:52:42 PM PDT 24
Peak memory	217752 kb
Host	smart-3a4cc9e1-c42a-4b6d-ac98-0e34748ebf08
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794656467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig est.794656467
Directory	/workspace/8.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_mux.1203227226
Short name	T264
Test name
Test status
Simulation time	924994077 ps
CPU time	9.68 seconds
Started	Apr 28 12:52:31 PM PDT 24
Finished	Apr 28 12:52:42 PM PDT 24
Peak memory	217744 kb
Host	smart-9037e951-9355-41b2-beb7-5b32c9fe6e6a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203227226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1 203227226
Directory	/workspace/8.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/8.lc_ctrl_security_escalation.3237516404
Short name	T360
Test name
Test status
Simulation time	203888513 ps
CPU time	8.29 seconds
Started	Apr 28 12:52:29 PM PDT 24
Finished	Apr 28 12:52:39 PM PDT 24
Peak memory	224864 kb
Host	smart-dfe33aeb-51ce-44ce-bbe2-161802eb31d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237516404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3237516404
Directory	/workspace/8.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/8.lc_ctrl_smoke.2562231265
Short name	T78
Test name
Test status
Simulation time	107345039 ps
CPU time	6.22 seconds
Started	Apr 28 12:52:28 PM PDT 24
Finished	Apr 28 12:52:35 PM PDT 24
Peak memory	213624 kb
Host	smart-2ce6f0bd-0591-4d68-8a59-ee0e9726a3be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562231265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2562231265
Directory	/workspace/8.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_failure.2417718433
Short name	T673
Test name
Test status
Simulation time	386824324 ps
CPU time	16.35 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:48 PM PDT 24
Peak memory	250780 kb
Host	smart-807faeee-a090-4c43-ae73-7971031b9fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417718433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2417718433
Directory	/workspace/8.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_post_trans.1574253381
Short name	T515
Test name
Test status
Simulation time	572290769 ps
CPU time	6.89 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:38 PM PDT 24
Peak memory	250616 kb
Host	smart-bd94fd63-908e-4c85-966c-588b65361d88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574253381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1574253381
Directory	/workspace/8.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_stress_all.1387066486
Short name	T396
Test name
Test status
Simulation time	14186291611 ps
CPU time	124.94 seconds
Started	Apr 28 12:52:34 PM PDT 24
Finished	Apr 28 12:54:40 PM PDT 24
Peak memory	246944 kb
Host	smart-43c8f3b9-176c-42fc-9a41-e59c7899271e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387066486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all.1387066486
Directory	/workspace/8.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.lc_ctrl_alert_test.3361869112
Short name	T68
Test name
Test status
Simulation time	40484040 ps
CPU time	0.85 seconds
Started	Apr 28 12:52:34 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	209328 kb
Host	smart-0daea49a-a035-4868-90b0-553162ceaae7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361869112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3361869112
Directory	/workspace/9.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.lc_ctrl_errors.1653264577
Short name	T384
Test name
Test status
Simulation time	2123235976 ps
CPU time	16.97 seconds
Started	Apr 28 12:52:30 PM PDT 24
Finished	Apr 28 12:52:48 PM PDT 24
Peak memory	217856 kb
Host	smart-fea3b18e-f159-4b6c-9a67-a5c542d33d72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653264577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1653264577
Directory	/workspace/9.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_access.197005082
Short name	T27
Test name
Test status
Simulation time	1609766494 ps
CPU time	9.64 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:45 PM PDT 24
Peak memory	216980 kb
Host	smart-2f35c18e-7709-4689-993c-71b5f1d8a307
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197005082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.197005082
Directory	/workspace/9.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_errors.3662719671
Short name	T662
Test name
Test status
Simulation time	4110835839 ps
CPU time	30.74 seconds
Started	Apr 28 12:52:33 PM PDT 24
Finished	Apr 28 12:53:04 PM PDT 24
Peak memory	217972 kb
Host	smart-61dfe239-d62c-4240-8d09-09701118130a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662719671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er rors.3662719671
Directory	/workspace/9.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_priority.2452437881
Short name	T497
Test name
Test status
Simulation time	2336808103 ps
CPU time	15.05 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:52 PM PDT 24
Peak memory	217832 kb
Host	smart-8b0b5e22-862a-48d4-9a47-25d31319e8a8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452437881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2 452437881
Directory	/workspace/9.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.726509369
Short name	T19
Test name
Test status
Simulation time	275140045 ps
CPU time	8.6 seconds
Started	Apr 28 12:52:28 PM PDT 24
Finished	Apr 28 12:52:38 PM PDT 24
Peak memory	217784 kb
Host	smart-a0c2502d-f8fe-4f6b-baf5-1064b7cf6954
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726509369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ prog_failure.726509369
Directory	/workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2260325153
Short name	T69
Test name
Test status
Simulation time	10344594408 ps
CPU time	20.29 seconds
Started	Apr 28 12:52:34 PM PDT 24
Finished	Apr 28 12:52:56 PM PDT 24
Peak memory	213764 kb
Host	smart-50efb651-201b-4eed-90f0-1a36bb31ebc6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260325153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_regwen_during_op.2260325153
Directory	/workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_smoke.1284072722
Short name	T711
Test name
Test status
Simulation time	145658195 ps
CPU time	1.84 seconds
Started	Apr 28 12:52:29 PM PDT 24
Finished	Apr 28 12:52:32 PM PDT 24
Peak memory	212812 kb
Host	smart-3ef15f07-0bfa-424d-bda9-71229c955cc4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284072722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke. 1284072722
Directory	/workspace/9.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1296827937
Short name	T449
Test name
Test status
Simulation time	1357311566 ps
CPU time	46.18 seconds
Started	Apr 28 12:52:32 PM PDT 24
Finished	Apr 28 12:53:20 PM PDT 24
Peak memory	270828 kb
Host	smart-ae19d02c-d67d-4af7-b8d2-9408245682a8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296827937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta g_state_failure.1296827937
Directory	/workspace/9.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4200619706
Short name	T561
Test name
Test status
Simulation time	292957021 ps
CPU time	14.56 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:50 PM PDT 24
Peak memory	242588 kb
Host	smart-0423d2ee-4f31-48aa-bbd1-753c0df280ee
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200619706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_state_post_trans.4200619706
Directory	/workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_prog_failure.1509717361
Short name	T242
Test name
Test status
Simulation time	26508570 ps
CPU time	1.94 seconds
Started	Apr 28 12:52:31 PM PDT 24
Finished	Apr 28 12:52:34 PM PDT 24
Peak memory	217864 kb
Host	smart-a41f5e16-db1e-4060-a2e5-123227d089ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1509717361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1509717361
Directory	/workspace/9.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_regwen_during_op.3496054657
Short name	T699
Test name
Test status
Simulation time	2039414226 ps
CPU time	7.51 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:43 PM PDT 24
Peak memory	214044 kb
Host	smart-0e073480-548e-42f9-a961-92be1295eafa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496054657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3496054657
Directory	/workspace/9.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_mubi.2764577889
Short name	T714
Test name
Test status
Simulation time	474053518 ps
CPU time	13.48 seconds
Started	Apr 28 12:52:33 PM PDT 24
Finished	Apr 28 12:52:47 PM PDT 24
Peak memory	225948 kb
Host	smart-26c4691e-7825-4f12-bf08-3797c89bc8fa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764577889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2764577889
Directory	/workspace/9.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_digest.507354848
Short name	T292
Test name
Test status
Simulation time	868019460 ps
CPU time	14.15 seconds
Started	Apr 28 12:52:32 PM PDT 24
Finished	Apr 28 12:52:47 PM PDT 24
Peak memory	217736 kb
Host	smart-5472ec95-7b9a-448b-b078-6242c0a07a49
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507354848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig est.507354848
Directory	/workspace/9.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_mux.4086848104
Short name	T747
Test name
Test status
Simulation time	204043324 ps
CPU time	7.27 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:44 PM PDT 24
Peak memory	217792 kb
Host	smart-2789f401-7052-42cd-b235-1a44678f8e2c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086848104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.4 086848104
Directory	/workspace/9.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/9.lc_ctrl_smoke.4033481528
Short name	T526
Test name
Test status
Simulation time	613096619 ps
CPU time	2.83 seconds
Started	Apr 28 12:52:32 PM PDT 24
Finished	Apr 28 12:52:36 PM PDT 24
Peak memory	214324 kb
Host	smart-10d426cd-5bfd-4d5c-80df-866d6fd4fc16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033481528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.4033481528
Directory	/workspace/9.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_failure.1997397016
Short name	T257
Test name
Test status
Simulation time	1503079115 ps
CPU time	19.01 seconds
Started	Apr 28 12:52:28 PM PDT 24
Finished	Apr 28 12:52:47 PM PDT 24
Peak memory	244808 kb
Host	smart-f5ed4494-65fc-4803-a262-5aafb1819920
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997397016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1997397016
Directory	/workspace/9.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_post_trans.3448508062
Short name	T491
Test name
Test status
Simulation time	89579023 ps
CPU time	3.14 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:40 PM PDT 24
Peak memory	226040 kb
Host	smart-c979022d-9cea-41a1-8510-66e3a4680ffb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448508062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3448508062
Directory	/workspace/9.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all.2273752386
Short name	T43
Test name
Test status
Simulation time	4656612209 ps
CPU time	84.08 seconds
Started	Apr 28 12:52:36 PM PDT 24
Finished	Apr 28 12:54:01 PM PDT 24
Peak memory	250900 kb
Host	smart-53cb048f-59ce-4c3b-a32d-b3781e40e275
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273752386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.2273752386
Directory	/workspace/9.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3657162004
Short name	T148
Test name
Test status
Simulation time	94432906181 ps
CPU time	776.66 seconds
Started	Apr 28 12:52:38 PM PDT 24
Finished	Apr 28 01:05:35 PM PDT 24
Peak memory	496856 kb
Host	smart-204e449f-6bca-435c-a713-8697d82a4525
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3657162004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3657162004
Directory	/workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3047535500
Short name	T353
Test name
Test status
Simulation time	19039359 ps
CPU time	0.87 seconds
Started	Apr 28 12:52:35 PM PDT 24
Finished	Apr 28 12:52:37 PM PDT 24
Peak memory	207816 kb
Host	smart-48f5bea2-5a1a-4f76-aa6b-edd67c1c6b5b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047535500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct rl_volatile_unlock_smoke.3047535500
Directory	/workspace/9.lc_ctrl_volatile_unlock_smoke/latest

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