Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1570528	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1785844

1

T2

7981

T3

97

T4

222

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3019521	1			T2	12631		T3	86		T4	209
values[0x0]	167873	1			T2	1110		T3	35		T4	106
values[0x1]	168978	1			T2	1062		T3	29		T4	81

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1247467	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2108905

1

T2

9460

T3

107

T4

252

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10324	1			T2	66		T4	4		T13	4
valid_sources[0x01]	9785	1			T2	38		T4	2		T9	5
valid_sources[0x02]	10362	1			T2	79		T4	2		T9	2
valid_sources[0x03]	13675	1			T2	42		T4	1		T13	5
valid_sources[0x04]	10502	1			T2	60		T9	12		T13	6
valid_sources[0x05]	9933	1			T2	93		T3	2		T4	1
valid_sources[0x06]	10474	1			T2	68		T9	8		T13	5
valid_sources[0x07]	10212	1			T2	65		T3	1		T4	9
valid_sources[0x08]	17736	1			T2	51		T9	7		T13	1
valid_sources[0x09]	10125	1			T2	66		T4	7		T13	6
valid_sources[0x0a]	10108	1			T2	53		T3	1		T9	5
valid_sources[0x0b]	10026	1			T2	59		T4	2		T9	8
valid_sources[0x0c]	10355	1			T2	48		T4	4		T10	61
valid_sources[0x0d]	9815	1			T2	55		T4	3		T13	3
valid_sources[0x0e]	10527	1			T2	81		T3	1		T10	16
valid_sources[0x0f]	13068	1			T2	74		T13	2		T14	9
valid_sources[0x10]	11387	1			T2	46		T4	3		T13	2
valid_sources[0x11]	39395	1			T2	57		T3	1		T13	1
valid_sources[0x12]	10419	1			T2	53		T4	2		T9	7
valid_sources[0x13]	12342	1			T2	57		T3	1		T13	2
valid_sources[0x14]	10395	1			T2	66		T4	5		T9	3
valid_sources[0x15]	24849	1			T2	55		T13	4		T14	5
valid_sources[0x16]	10498	1			T2	54		T4	1		T9	8
valid_sources[0x17]	10223	1			T2	51		T4	2		T9	4
valid_sources[0x18]	76563	1			T2	47		T12	17		T13	4
valid_sources[0x19]	9928	1			T2	61		T13	4		T15	11
valid_sources[0x1a]	11853	1			T2	64		T3	2		T4	3
valid_sources[0x1b]	9871	1			T2	72		T3	2		T9	15
valid_sources[0x1c]	10281	1			T2	56		T3	1		T9	1
valid_sources[0x1d]	9546	1			T2	62		T4	1		T7	1
valid_sources[0x1e]	9820	1			T2	50		T3	4		T4	2
valid_sources[0x1f]	10156	1			T2	49		T13	5		T14	3
valid_sources[0x20]	10108	1			T2	46		T4	1		T9	6
valid_sources[0x21]	10186	1			T2	65		T3	2		T9	8
valid_sources[0x22]	12162	1			T2	54		T4	10		T9	1
valid_sources[0x23]	10184	1			T2	47		T4	1		T9	2
valid_sources[0x24]	11087	1			T2	53		T4	5		T13	2
valid_sources[0x25]	9937	1			T2	57		T4	2		T9	4
valid_sources[0x26]	10091	1			T2	53		T9	5		T13	8
valid_sources[0x27]	9995	1			T2	58		T13	5		T14	5
valid_sources[0x28]	10065	1			T2	58		T9	1		T13	4
valid_sources[0x29]	11017	1			T2	73		T3	1		T7	1
valid_sources[0x2a]	10470	1			T2	69		T3	3		T4	1
valid_sources[0x2b]	10105	1			T2	44		T4	1		T9	5
valid_sources[0x2c]	10487	1			T2	62		T4	4		T13	3
valid_sources[0x2d]	11680	1			T2	57		T9	1		T10	47
valid_sources[0x2e]	10426	1			T2	53		T9	9		T13	6
valid_sources[0x2f]	9948	1			T2	60		T4	1		T9	6
valid_sources[0x30]	9862	1			T2	69		T4	9		T7	1
valid_sources[0x31]	9823	1			T2	55		T4	1		T9	1
valid_sources[0x32]	10256	1			T2	61		T9	5		T13	1
valid_sources[0x33]	11663	1			T2	57		T3	1		T9	11
valid_sources[0x34]	10089	1			T2	54		T3	2		T9	1
valid_sources[0x35]	13729	1			T2	72		T4	1		T9	3
valid_sources[0x36]	9825	1			T2	62		T4	5		T9	2
valid_sources[0x37]	9880	1			T2	50		T3	1		T9	3
valid_sources[0x38]	10181	1			T2	46		T9	1		T13	3
valid_sources[0x39]	12505	1			T2	58		T4	2		T9	6
valid_sources[0x3a]	10546	1			T2	49		T3	1		T9	1
valid_sources[0x3b]	9834	1			T2	47		T3	1		T4	2
valid_sources[0x3c]	10298	1			T2	39		T13	3		T14	4
valid_sources[0x3d]	10224	1			T2	68		T9	8		T13	1
valid_sources[0x3e]	10594	1			T2	42		T9	7		T13	2
valid_sources[0x3f]	10476	1			T2	59		T3	1		T9	6
valid_sources[0x40]	10509	1			T2	58		T3	2		T4	2
valid_sources[0x41]	9488	1			T2	55		T9	1		T13	5
valid_sources[0x42]	11461	1			T2	55		T3	1		T4	1
valid_sources[0x43]	9893	1			T2	51		T4	3		T9	1
valid_sources[0x44]	12166	1			T2	46		T4	2		T9	1
valid_sources[0x45]	10406	1			T2	74		T3	1		T4	2
valid_sources[0x46]	10148	1			T2	50		T3	1		T9	3
valid_sources[0x47]	9910	1			T2	55		T7	1		T9	1
valid_sources[0x48]	10349	1			T2	51		T4	3		T9	2
valid_sources[0x49]	92094	1			T2	53		T9	3		T13	3
valid_sources[0x4a]	10376	1			T2	67		T9	2		T13	2
valid_sources[0x4b]	10228	1			T2	43		T7	1		T9	5
valid_sources[0x4c]	10450	1			T2	71		T3	3		T4	2
valid_sources[0x4d]	10990	1			T2	49		T4	2		T7	1
valid_sources[0x4e]	12937	1			T2	60		T7	2		T9	4
valid_sources[0x4f]	9910	1			T2	58		T3	2		T4	1
valid_sources[0x50]	12884	1			T2	83		T9	8		T13	3
valid_sources[0x51]	9805	1			T2	79		T3	1		T4	3
valid_sources[0x52]	10193	1			T2	65		T3	1		T4	2
valid_sources[0x53]	10573	1			T2	60		T4	2		T9	6
valid_sources[0x54]	10094	1			T2	50		T4	1		T13	5
valid_sources[0x55]	10212	1			T2	47		T9	2		T13	7
valid_sources[0x56]	10075	1			T2	47		T3	1		T4	1
valid_sources[0x57]	10989	1			T2	43		T4	2		T9	1
valid_sources[0x58]	11388	1			T2	53		T9	1		T11	3
valid_sources[0x59]	17155	1			T2	70		T4	3		T9	6
valid_sources[0x5a]	10145	1			T2	74		T3	1		T9	4
valid_sources[0x5b]	10136	1			T2	52		T3	1		T4	1
valid_sources[0x5c]	10268	1			T2	81		T3	2		T4	7
valid_sources[0x5d]	11611	1			T2	58		T4	4		T9	1
valid_sources[0x5e]	10396	1			T2	59		T4	1		T13	6
valid_sources[0x5f]	10160	1			T2	52		T4	1		T9	3
valid_sources[0x60]	38995	1			T2	72		T3	1		T4	5
valid_sources[0x61]	10257	1			T2	58		T4	5		T13	6
valid_sources[0x62]	14612	1			T2	70		T4	1		T9	5
valid_sources[0x63]	12190	1			T2	55		T3	1		T4	1
valid_sources[0x64]	11193	1			T2	63		T4	2		T9	6
valid_sources[0x65]	15726	1			T2	57		T13	6		T14	3
valid_sources[0x66]	16278	1			T2	72		T3	2		T9	5
valid_sources[0x67]	13599	1			T2	67		T4	1		T9	2
valid_sources[0x68]	11848	1			T2	43		T13	3		T14	6
valid_sources[0x69]	12282	1			T2	55		T9	3		T13	3
valid_sources[0x6a]	11221	1			T2	53		T4	2		T9	5
valid_sources[0x6b]	11199	1			T2	64		T4	2		T9	7
valid_sources[0x6c]	10046	1			T2	75		T13	5		T14	3
valid_sources[0x6d]	12535	1			T2	50		T4	2		T9	5
valid_sources[0x6e]	12728	1			T2	65		T9	7		T13	9
valid_sources[0x6f]	10184	1			T2	50		T9	8		T13	2
valid_sources[0x70]	10478	1			T2	58		T4	1		T9	3
valid_sources[0x71]	9684	1			T2	36		T3	3		T10	15
valid_sources[0x72]	10045	1			T2	71		T4	6		T9	2
valid_sources[0x73]	9988	1			T2	58		T4	8		T9	2
valid_sources[0x74]	10451	1			T2	51		T9	3		T13	5
valid_sources[0x75]	14848	1			T2	60		T9	7		T10	9
valid_sources[0x76]	10094	1			T2	44		T4	2		T9	4
valid_sources[0x77]	10090	1			T2	57		T4	1		T9	1
valid_sources[0x78]	13606	1			T2	71		T4	9		T9	4
valid_sources[0x79]	9817	1			T2	59		T4	7		T13	3
valid_sources[0x7a]	10013	1			T2	60		T3	2		T9	4
valid_sources[0x7b]	10050	1			T2	58		T3	1		T4	10
valid_sources[0x7c]	10349	1			T2	53		T3	1		T4	1
valid_sources[0x7d]	9920	1			T2	46		T3	2		T4	1
valid_sources[0x7e]	11076	1			T2	57		T4	3		T9	1
valid_sources[0x7f]	10047	1			T2	52		T3	1		T9	2
valid_sources[0x80]	9908	1			T2	55		T3	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1495620

1

T2

6080

T3

45

T4

113

values[0x0]

all_enables

biggest_size

145358

1

T2

969

T3

28

T4

65

values[0x1]

all_enables

biggest_size

144866

1

T2

932

T3

24

T4

44