Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	102093725	12643	0	0
claim_transition_if_regwen_rd_A	102093725	1850	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102093725	12643	0	0
T19	34457	0	0	0
T29	963777	2	0	0
T30	576485	0	0	0
T38	31492	0	0	0
T39	29037	0	0	0
T40	0	1	0	0
T41	0	4	0	0
T57	0	4	0	0
T101	119442	0	0	0
T127	0	17	0	0
T128	0	1	0	0
T129	0	7	0	0
T130	0	2	0	0
T131	0	2	0	0
T132	0	18	0	0
T133	42022	0	0	0
T134	29651	0	0	0
T135	26763	0	0	0
T136	2941	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102093725	1850	0	0
T42	0	9	0	0
T95	0	45	0	0
T100	0	23	0	0
T130	346662	2	0	0
T131	336112	0	0	0
T137	0	7	0	0
T138	0	19	0	0
T139	0	44	0	0
T140	0	73	0	0
T141	0	14	0	0
T142	0	1	0	0
T143	12147	0	0	0
T144	26971	0	0	0
T145	311514	0	0	0
T146	1116	0	0	0
T147	22102	0	0	0
T148	6962	0	0	0
T149	3661	0	0	0
T150	212113	0	0	0