Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1607025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1825300

1

T1

499

T2

610

T3

20440

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3085734	1			T1	382		T2	544		T3	36278
values[0x0]	173653	1			T1	201		T2	244		T3	1416
values[0x1]	172938	1			T1	167		T2	228		T3	1418

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1275449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2156876

1

T1

561

T2

727

T3

24246

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10438	1			T1	9		T2	2		T3	157
valid_sources[0x01]	11966	1			T1	3		T2	1		T3	132
valid_sources[0x02]	10136	1			T2	4		T3	176		T9	12
valid_sources[0x03]	12216	1			T1	7		T2	5		T3	168
valid_sources[0x04]	11905	1			T1	4		T3	176		T9	10
valid_sources[0x05]	10750	1			T1	6		T2	13		T3	164
valid_sources[0x06]	10649	1			T1	2		T2	3		T3	127
valid_sources[0x07]	10438	1			T1	1		T2	7		T3	144
valid_sources[0x08]	12521	1			T1	3		T2	5		T3	143
valid_sources[0x09]	10362	1			T1	3		T2	4		T3	168
valid_sources[0x0a]	14736	1			T2	9		T3	136		T9	1
valid_sources[0x0b]	10691	1			T1	2		T2	1		T3	160
valid_sources[0x0c]	10070	1			T1	4		T2	5		T3	165
valid_sources[0x0d]	10877	1			T1	1		T2	6		T3	142
valid_sources[0x0e]	13495	1			T3	174		T9	4		T10	2
valid_sources[0x0f]	10709	1			T1	2		T2	1		T3	134
valid_sources[0x10]	10572	1			T1	1		T2	1		T3	181
valid_sources[0x11]	10689	1			T1	3		T2	5		T3	115
valid_sources[0x12]	11549	1			T1	2		T2	6		T3	151
valid_sources[0x13]	10794	1			T1	1		T2	3		T3	125
valid_sources[0x14]	10624	1			T2	1		T3	157		T9	3
valid_sources[0x15]	105020	1			T1	6		T2	1		T3	123
valid_sources[0x16]	10295	1			T1	3		T2	2		T3	169
valid_sources[0x17]	64645	1			T2	17		T3	141		T9	3
valid_sources[0x18]	10446	1			T2	9		T3	151		T8	79
valid_sources[0x19]	16311	1			T2	3		T3	159		T9	4
valid_sources[0x1a]	54859	1			T1	5		T2	1		T3	179
valid_sources[0x1b]	10490	1			T2	1		T3	136		T10	7
valid_sources[0x1c]	10449	1			T1	1		T3	144		T10	6
valid_sources[0x1d]	11089	1			T2	2		T3	163		T9	2
valid_sources[0x1e]	11778	1			T1	2		T2	4		T3	161
valid_sources[0x1f]	11566	1			T2	7		T3	151		T10	4
valid_sources[0x20]	10357	1			T1	5		T2	7		T3	168
valid_sources[0x21]	13906	1			T2	1		T3	175		T9	6
valid_sources[0x22]	10604	1			T2	3		T3	154		T9	5
valid_sources[0x23]	10970	1			T2	8		T3	154		T8	150
valid_sources[0x24]	10887	1			T1	5		T2	3		T3	164
valid_sources[0x25]	10713	1			T3	171		T8	145		T10	5
valid_sources[0x26]	10509	1			T1	4		T3	147		T9	2
valid_sources[0x27]	19394	1			T1	2		T3	139		T9	4
valid_sources[0x28]	14479	1			T1	3		T3	132		T10	4
valid_sources[0x29]	10598	1			T1	11		T2	2		T3	158
valid_sources[0x2a]	12208	1			T1	10		T2	2		T3	146
valid_sources[0x2b]	10536	1			T1	2		T2	3		T3	157
valid_sources[0x2c]	10786	1			T1	1		T2	4		T3	152
valid_sources[0x2d]	19039	1			T1	4		T3	132		T9	2
valid_sources[0x2e]	10739	1			T1	2		T2	2		T3	140
valid_sources[0x2f]	12098	1			T1	4		T2	17		T3	171
valid_sources[0x30]	11323	1			T1	3		T3	122		T9	8
valid_sources[0x31]	10519	1			T1	2		T2	5		T3	148
valid_sources[0x32]	11199	1			T1	3		T2	2		T3	141
valid_sources[0x33]	10805	1			T1	3		T2	14		T3	176
valid_sources[0x34]	11537	1			T2	2		T3	170		T9	3
valid_sources[0x35]	10737	1			T2	2		T3	171		T8	165
valid_sources[0x36]	10417	1			T1	17		T2	8		T3	151
valid_sources[0x37]	10305	1			T2	6		T3	167		T9	2
valid_sources[0x38]	10361	1			T1	1		T2	2		T3	141
valid_sources[0x39]	12085	1			T1	1		T2	18		T3	152
valid_sources[0x3a]	10513	1			T1	1		T2	3		T3	137
valid_sources[0x3b]	11879	1			T2	6		T3	167		T10	4
valid_sources[0x3c]	50251	1			T1	5		T3	141		T9	2
valid_sources[0x3d]	10799	1			T2	5		T3	126		T10	4
valid_sources[0x3e]	11790	1			T3	179		T9	6		T10	9
valid_sources[0x3f]	10650	1			T1	4		T2	4		T3	142
valid_sources[0x40]	10873	1			T1	1		T2	10		T3	172
valid_sources[0x41]	10561	1			T1	8		T2	2		T3	141
valid_sources[0x42]	10699	1			T1	4		T3	149		T9	3
valid_sources[0x43]	10792	1			T1	1		T2	3		T3	117
valid_sources[0x44]	10523	1			T1	1		T2	4		T3	144
valid_sources[0x45]	10680	1			T1	2		T2	5		T3	172
valid_sources[0x46]	10429	1			T1	6		T3	131		T9	6
valid_sources[0x47]	12715	1			T2	2		T3	156		T9	8
valid_sources[0x48]	11921	1			T1	5		T2	3		T3	159
valid_sources[0x49]	10607	1			T3	153		T10	2		T4	149
valid_sources[0x4a]	10747	1			T2	8		T3	139		T9	4
valid_sources[0x4b]	10736	1			T1	1		T2	4		T3	167
valid_sources[0x4c]	10643	1			T1	2		T2	4		T3	139
valid_sources[0x4d]	10591	1			T1	2		T2	2		T3	143
valid_sources[0x4e]	10504	1			T1	1		T2	6		T3	137
valid_sources[0x4f]	10527	1			T2	11		T3	125		T9	11
valid_sources[0x50]	16697	1			T2	9		T3	132		T9	7
valid_sources[0x51]	11662	1			T1	2		T2	4		T3	132
valid_sources[0x52]	34285	1			T1	1		T2	5		T3	178
valid_sources[0x53]	10688	1			T1	1		T2	4		T3	163
valid_sources[0x54]	15139	1			T1	3		T2	5		T3	184
valid_sources[0x55]	14890	1			T1	1		T2	5		T3	109
valid_sources[0x56]	10724	1			T1	5		T3	186		T9	17
valid_sources[0x57]	10773	1			T1	1		T3	165		T8	255
valid_sources[0x58]	10192	1			T1	8		T3	157		T9	1
valid_sources[0x59]	10702	1			T1	16		T2	6		T3	175
valid_sources[0x5a]	11526	1			T2	3		T3	159		T9	4
valid_sources[0x5b]	10184	1			T1	1		T2	7		T3	179
valid_sources[0x5c]	10416	1			T1	3		T2	3		T3	149
valid_sources[0x5d]	10701	1			T1	2		T2	9		T3	177
valid_sources[0x5e]	10585	1			T1	2		T2	1		T3	142
valid_sources[0x5f]	12565	1			T1	2		T2	14		T3	177
valid_sources[0x60]	10354	1			T1	7		T2	6		T3	161
valid_sources[0x61]	10594	1			T1	2		T2	7		T3	132
valid_sources[0x62]	10690	1			T1	8		T2	3		T3	148
valid_sources[0x63]	23526	1			T1	2		T2	3		T3	153
valid_sources[0x64]	10944	1			T1	8		T3	155		T9	2
valid_sources[0x65]	10755	1			T1	2		T2	1		T3	137
valid_sources[0x66]	10440	1			T1	1		T3	171		T8	88
valid_sources[0x67]	10814	1			T3	137		T9	5		T10	4
valid_sources[0x68]	10145	1			T1	7		T2	4		T3	142
valid_sources[0x69]	10804	1			T1	2		T2	2		T3	177
valid_sources[0x6a]	12201	1			T2	7		T3	154		T9	2
valid_sources[0x6b]	10377	1			T1	4		T2	2		T3	147
valid_sources[0x6c]	11869	1			T2	4		T3	161		T9	2
valid_sources[0x6d]	10327	1			T1	3		T2	10		T3	128
valid_sources[0x6e]	12859	1			T1	3		T3	170		T9	2
valid_sources[0x6f]	13104	1			T1	3		T2	9		T3	161
valid_sources[0x70]	10642	1			T1	3		T2	1		T3	158
valid_sources[0x71]	11443	1			T1	9		T2	1		T3	133
valid_sources[0x72]	10694	1			T2	13		T3	129		T9	11
valid_sources[0x73]	10138	1			T1	15		T3	151		T9	3
valid_sources[0x74]	12946	1			T1	7		T2	1		T3	139
valid_sources[0x75]	11047	1			T2	2		T3	161		T10	6
valid_sources[0x76]	10521	1			T2	2		T3	144		T9	1
valid_sources[0x77]	12901	1			T2	4		T3	173		T9	1
valid_sources[0x78]	10635	1			T1	11		T2	4		T3	156
valid_sources[0x79]	17821	1			T1	1		T2	1		T3	124
valid_sources[0x7a]	10746	1			T1	3		T2	1		T3	168
valid_sources[0x7b]	10620	1			T2	2		T3	135		T9	2
valid_sources[0x7c]	10632	1			T1	2		T2	7		T3	154
valid_sources[0x7d]	13579	1			T1	3		T2	6		T3	149
valid_sources[0x7e]	10407	1			T1	1		T2	8		T3	180
valid_sources[0x7f]	11776	1			T1	2		T2	7		T3	165
valid_sources[0x80]	12335	1			T1	2		T3	157		T8	151

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1526698

1

T1

180

T2

191

T3

17984

values[0x0]

all_enables

biggest_size

150484

1

T1

172

T2

219

T3

1208

values[0x1]

all_enables

biggest_size

148118

1

T1

147

T2

200

T3

1248