Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	111301112	13586	0	0
claim_transition_if_regwen_rd_A	111301112	1603	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111301112	13586	0	0
T45	0	3	0	0
T47	26636	0	0	0
T50	0	4	0	0
T51	0	5	0	0
T57	55473	0	0	0
T65	132841	10	0	0
T66	10804	0	0	0
T89	53397	0	0	0
T95	0	3	0	0
T96	36820	0	0	0
T142	0	6	0	0
T143	0	3	0	0
T144	0	3	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	25944	0	0	0
T148	6094	0	0	0
T149	27147	0	0	0
T150	25246	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111301112	1603	0	0
T143	389852	14	0	0
T151	0	13	0	0
T152	0	7	0	0
T153	0	15	0	0
T154	0	5	0	0
T155	0	21	0	0
T156	0	17	0	0
T157	0	8	0	0
T158	0	241	0	0
T159	0	63	0	0
T160	24639	0	0	0
T161	46814	0	0	0
T162	1961	0	0	0
T163	37711	0	0	0
T164	32856	0	0	0
T165	1935	0	0	0
T166	28683	0	0	0
T167	34378	0	0	0
T168	26163	0	0	0