Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1398418	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1610640

1

T1

620

T2

718

T3

1252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2681718	1			T1	585		T2	331		T3	1126
values[0x0]	163176	1			T1	193		T2	342		T3	391
values[0x1]	164164	1			T1	215		T2	306		T3	401

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1109220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1899838

1

T1

702

T2

787

T3

1415

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21379	1			T1	6		T2	4		T3	7
valid_sources[0x01]	14568	1			T1	5		T2	3		T3	5
valid_sources[0x02]	21046	1			T1	1		T2	8		T3	7
valid_sources[0x03]	12307	1			T1	3		T2	1		T3	5
valid_sources[0x04]	8854	1			T1	8		T2	5		T3	4
valid_sources[0x05]	8205	1			T1	1		T3	6		T10	2
valid_sources[0x06]	8620	1			T1	3		T2	1		T3	7
valid_sources[0x07]	8835	1			T1	3		T3	10		T12	10
valid_sources[0x08]	8294	1			T1	5		T2	1		T3	3
valid_sources[0x09]	8384	1			T1	3		T2	1		T3	13
valid_sources[0x0a]	8801	1			T1	4		T2	3		T3	7
valid_sources[0x0b]	8808	1			T1	7		T2	4		T3	8
valid_sources[0x0c]	9962	1			T1	2		T2	15		T3	7
valid_sources[0x0d]	8403	1			T1	1		T2	2		T3	10
valid_sources[0x0e]	8165	1			T2	3		T3	9		T12	1
valid_sources[0x0f]	8521	1			T1	4		T2	6		T3	10
valid_sources[0x10]	8609	1			T1	3		T2	1		T3	7
valid_sources[0x11]	9590	1			T1	1		T2	6		T3	8
valid_sources[0x12]	8397	1			T1	3		T2	5		T3	8
valid_sources[0x13]	9337	1			T1	1		T2	11		T3	5
valid_sources[0x14]	8969	1			T1	3		T2	1		T3	9
valid_sources[0x15]	8438	1			T1	5		T2	8		T3	8
valid_sources[0x16]	8332	1			T1	3		T2	3		T3	8
valid_sources[0x17]	9132	1			T1	6		T2	7		T3	7
valid_sources[0x18]	8389	1			T1	4		T2	3		T3	5
valid_sources[0x19]	8191	1			T1	4		T2	1		T3	7
valid_sources[0x1a]	8502	1			T1	4		T2	5		T3	6
valid_sources[0x1b]	9445	1			T1	1		T3	7		T12	9
valid_sources[0x1c]	8498	1			T1	1		T2	1		T3	5
valid_sources[0x1d]	9212	1			T1	2		T2	9		T3	7
valid_sources[0x1e]	8617	1			T1	4		T2	12		T3	5
valid_sources[0x1f]	8405	1			T1	5		T2	2		T3	7
valid_sources[0x20]	8518	1			T1	1		T2	1		T3	6
valid_sources[0x21]	8389	1			T1	4		T2	4		T3	6
valid_sources[0x22]	8298	1			T1	5		T3	4		T12	3
valid_sources[0x23]	8829	1			T1	2		T2	8		T3	8
valid_sources[0x24]	18382	1			T1	3		T2	1		T3	3
valid_sources[0x25]	8652	1			T1	2		T3	4		T12	4
valid_sources[0x26]	8943	1			T1	4		T2	2		T3	5
valid_sources[0x27]	8406	1			T2	1		T3	5		T12	3
valid_sources[0x28]	9944	1			T1	1		T2	3		T3	10
valid_sources[0x29]	8592	1			T1	3		T2	3		T3	5
valid_sources[0x2a]	9896	1			T1	5		T2	2		T3	3
valid_sources[0x2b]	9960	1			T1	5		T2	4		T3	4
valid_sources[0x2c]	20016	1			T3	5		T10	1		T12	3
valid_sources[0x2d]	8445	1			T1	4		T2	3		T3	5
valid_sources[0x2e]	8313	1			T1	1		T2	1		T3	7
valid_sources[0x2f]	8565	1			T1	14		T2	11		T3	2
valid_sources[0x30]	9620	1			T1	3		T2	5		T3	10
valid_sources[0x31]	8456	1			T1	5		T2	5		T3	4
valid_sources[0x32]	8534	1			T1	6		T2	1		T3	9
valid_sources[0x33]	8676	1			T1	4		T3	3		T12	9
valid_sources[0x34]	9359	1			T1	5		T2	1		T3	7
valid_sources[0x35]	8738	1			T1	6		T3	8		T10	1
valid_sources[0x36]	8498	1			T1	5		T3	13		T12	4
valid_sources[0x37]	8390	1			T1	4		T2	3		T3	2
valid_sources[0x38]	8533	1			T1	5		T2	1		T3	4
valid_sources[0x39]	10100	1			T1	2		T2	10		T3	6
valid_sources[0x3a]	8604	1			T1	5		T2	5		T3	5
valid_sources[0x3b]	32403	1			T1	3		T2	20		T3	4
valid_sources[0x3c]	8742	1			T1	4		T3	12		T12	7
valid_sources[0x3d]	10486	1			T1	1		T3	4		T10	1
valid_sources[0x3e]	8790	1			T1	5		T3	8		T10	4
valid_sources[0x3f]	10926	1			T1	3		T2	12		T3	7
valid_sources[0x40]	12286	1			T1	8		T2	5		T3	1
valid_sources[0x41]	8216	1			T1	4		T3	9		T10	4
valid_sources[0x42]	16080	1			T1	7		T3	9		T10	2
valid_sources[0x43]	8507	1			T1	1		T3	7		T10	2
valid_sources[0x44]	10390	1			T1	6		T2	9		T3	6
valid_sources[0x45]	8398	1			T1	5		T2	1		T3	6
valid_sources[0x46]	8530	1			T1	7		T2	7		T3	8
valid_sources[0x47]	9815	1			T2	12		T3	10		T12	5
valid_sources[0x48]	11213	1			T1	5		T2	8		T3	9
valid_sources[0x49]	8288	1			T1	6		T3	8		T12	5
valid_sources[0x4a]	8616	1			T1	9		T2	1		T3	6
valid_sources[0x4b]	10851	1			T2	3		T3	6		T12	3
valid_sources[0x4c]	8493	1			T1	5		T3	8		T12	10
valid_sources[0x4d]	26638	1			T1	7		T2	4		T3	6
valid_sources[0x4e]	9893	1			T1	7		T2	7		T3	7
valid_sources[0x4f]	8280	1			T1	7		T2	5		T3	6
valid_sources[0x50]	8404	1			T1	3		T2	3		T3	10
valid_sources[0x51]	8234	1			T1	2		T2	2		T3	8
valid_sources[0x52]	8476	1			T1	5		T3	5		T10	1
valid_sources[0x53]	8697	1			T1	6		T3	6		T5	3
valid_sources[0x54]	8296	1			T1	6		T2	5		T3	9
valid_sources[0x55]	9673	1			T1	1		T3	6		T10	2
valid_sources[0x56]	8544	1			T1	5		T2	2		T3	13
valid_sources[0x57]	9328	1			T1	3		T2	16		T3	11
valid_sources[0x58]	8146	1			T1	5		T2	3		T3	9
valid_sources[0x59]	8345	1			T1	4		T3	13		T10	6
valid_sources[0x5a]	8778	1			T1	1		T2	6		T3	3
valid_sources[0x5b]	9756	1			T1	7		T2	1		T3	11
valid_sources[0x5c]	9017	1			T1	2		T2	7		T3	6
valid_sources[0x5d]	13662	1			T3	9		T12	6		T13	5
valid_sources[0x5e]	11821	1			T1	6		T3	13		T12	4
valid_sources[0x5f]	8331	1			T2	2		T3	14		T10	1
valid_sources[0x60]	8236	1			T2	3		T3	12		T10	1
valid_sources[0x61]	8240	1			T1	5		T3	13		T10	1
valid_sources[0x62]	8705	1			T1	5		T2	6		T3	10
valid_sources[0x63]	8895	1			T1	2		T2	6		T3	6
valid_sources[0x64]	21347	1			T1	8		T2	2		T3	13
valid_sources[0x65]	8567	1			T1	10		T2	2		T3	6
valid_sources[0x66]	36418	1			T1	3		T2	6		T3	10
valid_sources[0x67]	8247	1			T1	5		T2	4		T3	12
valid_sources[0x68]	9356	1			T1	9		T2	3		T3	14
valid_sources[0x69]	8518	1			T1	7		T3	3		T12	2
valid_sources[0x6a]	8499	1			T1	6		T2	10		T3	3
valid_sources[0x6b]	8557	1			T1	2		T2	4		T3	11
valid_sources[0x6c]	8411	1			T3	9		T10	1		T12	6
valid_sources[0x6d]	20346	1			T1	9		T2	7		T3	7
valid_sources[0x6e]	8752	1			T1	3		T3	7		T10	1
valid_sources[0x6f]	8826	1			T1	3		T2	2		T3	3
valid_sources[0x70]	9929	1			T1	2		T3	10		T10	1
valid_sources[0x71]	8691	1			T1	3		T2	1		T3	7
valid_sources[0x72]	9384	1			T1	3		T2	5		T3	11
valid_sources[0x73]	8958	1			T1	4		T2	2		T3	11
valid_sources[0x74]	8320	1			T1	4		T2	1		T3	6
valid_sources[0x75]	8490	1			T1	3		T2	10		T3	10
valid_sources[0x76]	9714	1			T1	9		T3	5		T12	4
valid_sources[0x77]	8774	1			T1	3		T2	4		T3	7
valid_sources[0x78]	11911	1			T1	6		T3	10		T12	1
valid_sources[0x79]	9267	1			T1	3		T3	6		T12	4
valid_sources[0x7a]	8156	1			T1	5		T2	5		T3	8
valid_sources[0x7b]	10531	1			T1	5		T2	2		T3	4
valid_sources[0x7c]	10730	1			T1	5		T2	8		T3	5
valid_sources[0x7d]	24982	1			T1	3		T3	7		T12	5
valid_sources[0x7e]	8679	1			T1	5		T3	8		T10	4
valid_sources[0x7f]	11929	1			T1	1		T2	3		T3	9
valid_sources[0x80]	9555	1			T1	2		T2	16		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1328260

1

T1

266

T2

154

T3

561

values[0x0]

all_enables

biggest_size

141590

1

T1

168

T2

301

T3

347

values[0x1]

all_enables

biggest_size

140790

1

T1

186

T2

263

T3

344