Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95457926	15540	0	0
claim_transition_if_regwen_rd_A	95457926	1595	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95457926	15540	0	0
T18	171949	2	0	0
T19	16658	0	0	0
T37	1161	0	0	0
T42	84651	0	0	0
T48	0	8	0	0
T65	0	4	0	0
T90	17847	0	0	0
T91	1076	0	0	0
T93	0	1	0	0
T114	0	10	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	6	0	0
T157	1772	0	0	0
T158	36020	0	0	0
T159	28003	0	0	0
T160	7533	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95457926	1595	0	0
T118	0	35	0	0
T121	0	2	0	0
T153	645989	4	0	0
T155	0	13	0	0
T161	0	6	0	0
T162	0	9	0	0
T163	0	6	0	0
T164	0	6	0	0
T165	0	27	0	0
T166	0	5	0	0
T167	41999	0	0	0
T168	5798	0	0	0
T169	763	0	0	0
T170	9777	0	0	0
T171	84284	0	0	0
T172	21986	0	0	0
T173	1545	0	0	0
T174	7352	0	0	0
T175	7334	0	0	0