Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1692846	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1910141

1

T1

4

T3

526

T11

28804

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3260702	1			T3	466		T11	51837		T12	12735
values[0x0]	170149	1			T1	12		T3	188		T11	1676
values[0x1]	172136	1			T1	16		T3	220		T11	1779

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1345500	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2257487

1

T1

8

T3

609

T11

34393

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8153	1			T12	35		T17	4		T18	9
valid_sources[0x01]	8525	1			T1	7		T12	45		T17	11
valid_sources[0x02]	24690	1			T12	52		T17	3		T18	17
valid_sources[0x03]	8702	1			T12	48		T17	8		T18	18
valid_sources[0x04]	8961	1			T12	56		T17	4		T18	21
valid_sources[0x05]	9385	1			T12	67		T17	2		T18	18
valid_sources[0x06]	101053	1			T12	44		T17	4		T18	10
valid_sources[0x07]	9016	1			T12	46		T17	4		T18	7
valid_sources[0x08]	10583	1			T12	55		T14	2		T16	1138
valid_sources[0x09]	8973	1			T12	50		T17	9		T18	12
valid_sources[0x0a]	9286	1			T12	64		T14	1		T17	5
valid_sources[0x0b]	8798	1			T12	44		T17	10		T18	16
valid_sources[0x0c]	27982	1			T12	69		T17	1		T18	14
valid_sources[0x0d]	9170	1			T12	60		T17	2		T18	18
valid_sources[0x0e]	13056	1			T12	42		T14	1		T17	3
valid_sources[0x0f]	10647	1			T12	49		T17	7		T18	12
valid_sources[0x10]	8784	1			T12	46		T17	5		T18	26
valid_sources[0x11]	8943	1			T12	51		T17	6		T18	21
valid_sources[0x12]	9185	1			T12	47		T14	1		T17	7
valid_sources[0x13]	10846	1			T12	45		T18	6		T6	4
valid_sources[0x14]	8688	1			T12	49		T17	3		T18	16
valid_sources[0x15]	24746	1			T12	74		T17	5		T18	16
valid_sources[0x16]	9713	1			T12	30		T17	6		T18	15
valid_sources[0x17]	8850	1			T12	53		T17	6		T18	17
valid_sources[0x18]	10159	1			T12	45		T17	7		T18	11
valid_sources[0x19]	9118	1			T12	37		T17	3		T18	22
valid_sources[0x1a]	9169	1			T12	81		T17	6		T18	19
valid_sources[0x1b]	8627	1			T12	70		T17	5		T18	31
valid_sources[0x1c]	8926	1			T12	38		T17	3		T18	8
valid_sources[0x1d]	28522	1			T12	53		T17	7		T18	14
valid_sources[0x1e]	8896	1			T12	42		T17	7		T18	19
valid_sources[0x1f]	8705	1			T12	60		T17	7		T18	13
valid_sources[0x20]	9996	1			T11	17		T12	67		T17	5
valid_sources[0x21]	9031	1			T12	61		T14	1		T18	25
valid_sources[0x22]	11217	1			T12	27		T17	6		T18	18
valid_sources[0x23]	9168	1			T12	66		T14	2		T17	1
valid_sources[0x24]	8566	1			T12	22		T17	8		T18	13
valid_sources[0x25]	9974	1			T12	34		T17	9		T18	30
valid_sources[0x26]	194840	1			T12	43		T14	1		T17	5
valid_sources[0x27]	9579	1			T12	26		T17	7		T18	9
valid_sources[0x28]	10463	1			T12	75		T17	5		T18	9
valid_sources[0x29]	11471	1			T12	46		T17	2		T18	11
valid_sources[0x2a]	11905	1			T12	42		T17	7		T18	16
valid_sources[0x2b]	8652	1			T12	42		T14	1		T17	15
valid_sources[0x2c]	8916	1			T12	40		T14	1		T17	3
valid_sources[0x2d]	8857	1			T12	53		T14	1		T17	3
valid_sources[0x2e]	8807	1			T12	62		T17	3		T18	10
valid_sources[0x2f]	8654	1			T1	2		T12	75		T17	6
valid_sources[0x30]	8963	1			T12	44		T17	7		T18	19
valid_sources[0x31]	15832	1			T12	32		T17	9		T18	26
valid_sources[0x32]	8727	1			T12	35		T14	1		T17	5
valid_sources[0x33]	9079	1			T12	19		T17	7		T18	7
valid_sources[0x34]	9765	1			T12	43		T17	9		T18	15
valid_sources[0x35]	18187	1			T12	56		T17	11		T18	6
valid_sources[0x36]	8490	1			T12	33		T17	4		T18	19
valid_sources[0x37]	9069	1			T12	32		T17	5		T18	14
valid_sources[0x38]	9238	1			T12	33		T17	4		T18	16
valid_sources[0x39]	8922	1			T12	43		T17	7		T18	9
valid_sources[0x3a]	11791	1			T12	57		T17	7		T18	20
valid_sources[0x3b]	8781	1			T11	17		T12	50		T17	5
valid_sources[0x3c]	8738	1			T12	49		T17	3		T18	15
valid_sources[0x3d]	8857	1			T12	77		T14	2		T17	9
valid_sources[0x3e]	8713	1			T12	57		T17	11		T18	28
valid_sources[0x3f]	8861	1			T12	58		T17	6		T18	12
valid_sources[0x40]	132538	1			T1	2		T12	33		T17	10
valid_sources[0x41]	9154	1			T12	52		T17	6		T18	26
valid_sources[0x42]	18130	1			T12	42		T14	1		T17	3
valid_sources[0x43]	95821	1			T12	58		T17	3		T18	8
valid_sources[0x44]	9665	1			T12	46		T17	10		T18	13
valid_sources[0x45]	12090	1			T11	1376		T12	56		T17	9
valid_sources[0x46]	18781	1			T12	47		T17	1		T18	12
valid_sources[0x47]	8954	1			T12	44		T17	6		T18	8
valid_sources[0x48]	8926	1			T1	5		T12	22		T17	7
valid_sources[0x49]	10083	1			T12	49		T17	5		T18	12
valid_sources[0x4a]	9105	1			T12	76		T14	1		T17	8
valid_sources[0x4b]	10762	1			T12	58		T17	3		T18	31
valid_sources[0x4c]	8580	1			T12	39		T17	6		T18	6
valid_sources[0x4d]	8455	1			T12	30		T17	4		T18	19
valid_sources[0x4e]	8717	1			T12	35		T14	1		T17	2
valid_sources[0x4f]	8951	1			T12	48		T17	1		T18	9
valid_sources[0x50]	8846	1			T12	67		T17	5		T18	9
valid_sources[0x51]	9086	1			T12	40		T17	9		T18	12
valid_sources[0x52]	8896	1			T12	58		T17	2		T18	13
valid_sources[0x53]	9058	1			T11	7		T12	49		T14	1
valid_sources[0x54]	62685	1			T11	53258		T12	63		T17	5
valid_sources[0x55]	8803	1			T12	67		T17	3		T18	22
valid_sources[0x56]	8881	1			T12	53		T17	5		T18	20
valid_sources[0x57]	9024	1			T12	39		T17	6		T18	23
valid_sources[0x58]	9442	1			T12	69		T17	10		T18	17
valid_sources[0x59]	9147	1			T12	69		T17	3		T18	17
valid_sources[0x5a]	9807	1			T12	89		T17	8		T18	14
valid_sources[0x5b]	9733	1			T12	47		T14	1		T17	4
valid_sources[0x5c]	8807	1			T12	33		T17	5		T18	17
valid_sources[0x5d]	10801	1			T1	2		T12	39		T17	7
valid_sources[0x5e]	9004	1			T12	43		T14	1		T17	5
valid_sources[0x5f]	8962	1			T12	35		T14	1		T17	4
valid_sources[0x60]	9068	1			T12	46		T17	4		T18	9
valid_sources[0x61]	8655	1			T12	28		T14	1		T17	4
valid_sources[0x62]	8992	1			T12	48		T17	4		T18	7
valid_sources[0x63]	15151	1			T12	73		T17	6		T18	12
valid_sources[0x64]	9622	1			T11	542		T12	43		T17	5
valid_sources[0x65]	8761	1			T12	58		T17	7		T18	11
valid_sources[0x66]	8804	1			T12	65		T14	2		T17	8
valid_sources[0x67]	257515	1			T12	46		T17	4		T18	11
valid_sources[0x68]	8852	1			T12	58		T17	11		T18	17
valid_sources[0x69]	8523	1			T12	27		T17	7		T18	19
valid_sources[0x6a]	9082	1			T12	76		T17	10		T18	11
valid_sources[0x6b]	9154	1			T11	17		T12	33		T17	4
valid_sources[0x6c]	8997	1			T12	33		T17	9		T18	24
valid_sources[0x6d]	8692	1			T12	53		T17	10		T18	31
valid_sources[0x6e]	8820	1			T12	49		T17	7		T18	24
valid_sources[0x6f]	9912	1			T12	37		T14	1		T17	4
valid_sources[0x70]	8848	1			T12	61		T17	3		T18	28
valid_sources[0x71]	8724	1			T12	43		T17	6		T18	6
valid_sources[0x72]	8701	1			T12	45		T17	4		T18	21
valid_sources[0x73]	8400	1			T12	48		T17	2		T18	22
valid_sources[0x74]	8834	1			T12	60		T14	1		T17	4
valid_sources[0x75]	8952	1			T12	45		T17	7		T18	16
valid_sources[0x76]	8998	1			T1	5		T12	58		T17	1
valid_sources[0x77]	8913	1			T12	46		T17	4		T18	11
valid_sources[0x78]	10098	1			T12	43		T17	9		T18	14
valid_sources[0x79]	8820	1			T12	48		T14	1		T17	2
valid_sources[0x7a]	8827	1			T12	63		T17	2		T18	26
valid_sources[0x7b]	8772	1			T12	40		T13	4		T14	2
valid_sources[0x7c]	10271	1			T12	49		T17	1		T18	18
valid_sources[0x7d]	10475	1			T12	49		T17	10		T18	13
valid_sources[0x7e]	8881	1			T12	38		T14	1		T17	5
valid_sources[0x7f]	8571	1			T12	56		T17	6		T18	20
valid_sources[0x80]	8647	1			T12	67		T17	5		T18	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1614945

1

T3

169

T11

25805

T12

6408

values[0x0]

all_enables

biggest_size

147525

1

T1

1

T3

166

T11

1458

values[0x1]

all_enables

biggest_size

147671

1

T1

3

T3

191

T11

1541