Unified Coverage Report :: Module :: lc_ctrl_kmac_if

Module : lc_ctrl_kmac_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	100.00		83.33	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_kmac_if	96.67	100.00	100.00		83.33	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	100.00		83.33	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	99.10	100.00		83.33	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_flop_2sync	100.00	100.00				100.00
u_prim_sync_reqack_data_in	98.41	98.18	100.00			95.45	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl_kmac_if

	Line No.	Total	Covered	Percent
TOTAL		41	41	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
ALWAYS	88	8	8	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
ALWAYS	159	21	21	100.00
ALWAYS	203	3	3	100.00
ALWAYS	206	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
81	1	1
88	1	1
89	1	1
90	1	1
91	1	1
93	1	1
95	1	1
96	1	1
97	1	1
			MISSING_ELSE
102	1	1
103	1	1
104	1	1
107	1	1
159	1	1
160	1	1
161	1	1
162	1	1
164	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
			MISSING_ELSE
			MISSING_ELSE
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
			MISSING_ELSE
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
196	1	1
203	3	3
206	1	1
207	1	1
209	1	1

---

Cond Coverage for Module : lc_ctrl_kmac_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (token_hash_req_i && token_hash_ack_d)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T116
1	0	Covered	T2,T11,T12
1	1	Covered	T2,T11,T12

 LINE       107
 EXPRESSION (token_hash_req_i & ((~token_hash_ack_q)))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T12
1	1	Covered	T2,T11,T12

---

FSM Coverage for Module : lc_ctrl_kmac_if

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DoneSt	191	Covered	T2,T11,T12
FirstSt	203	Covered	T1,T2,T3
SecondSt	173	Covered	T2,T11,T12
WaitSt	184	Covered	T2,T11,T12

transitions	Line No.	Covered	Tests
DoneSt->FirstSt	203	Covered	T2,T11,T12
FirstSt->SecondSt	173	Covered	T2,T11,T12
SecondSt->FirstSt	203	Not Covered
SecondSt->WaitSt	184	Covered	T2,T11,T12
WaitSt->DoneSt	191	Covered	T2,T11,T12
WaitSt->FirstSt	203	Covered	T19,T117,T118

---

Branch Coverage for Module : lc_ctrl_kmac_if

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	3	3	100.00
CASE	164	9	9	100.00
IF	203	2	2	100.00
IF	206	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	95	if ((token_hash_req_i && token_hash_ack_d))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T11,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	case (state_q)
-2-:	168	if (kmac_req)
-3-:	172	if (kmac_data_i.ready)
-4-:	183	if (kmac_data_i.ready)
-5-:	189	if (kmac_data_i.done)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
FirstSt	1	1	-	-	Covered	T2,T11,T12
FirstSt	1	0	-	-	Covered	T16,T18,T29
FirstSt	0	-	-	-	Covered	T1,T2,T3
SecondSt	-	-	1	-	Covered	T2,T11,T12
SecondSt	-	-	0	-	Covered	T16,T18,T29
WaitSt	-	-	-	1	Covered	T2,T11,T12
WaitSt	-	-	-	0	Covered	T2,T11,T12
DoneSt	-	-	-	-	Covered	T2,T11,T12
default	-	-	-	-	Covered	T3,T5,T11

	LineNo.	Expression
-1-:	203	if ((!rst_kmac_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_kmac_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl_kmac_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataStable_A	106615367	45135907	0	0
u_state_regs_A	103827777	99734483	0	0

DataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106615367	45135907	0	0
T2	76756	61744	0	0
T3	23110	0	0	0
T4	21002	0	0	0
T5	154085	0	0	0
T11	253805	114986	0	0
T12	26973	25109	0	0
T13	1115	0	0	0
T14	2049	0	0	0
T15	79315	0	0	0
T16	33364	1578	0	0
T17	0	840	0	0
T18	0	4887	0	0
T29	0	1439	0	0
T46	0	803	0	0
T47	0	562	0	0
T61	0	31	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103827777	99734483	0	0
T1	1728	1631	0	0
T2	76756	76310	0	0
T3	18252	13776	0	0
T4	21002	20182	0	0
T5	141220	135654	0	0
T11	245049	239020	0	0
T12	26973	26462	0	0
T13	1115	1062	0	0
T14	2049	1951	0	0
T15	79315	77988	0	0