Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108631965	14673	0	0
claim_transition_if_regwen_rd_A	108631965	1958	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108631965	14673	0	0
T11	253805	2	0	0
T12	26973	0	0	0
T13	1115	0	0	0
T14	2049	0	0	0
T15	79315	0	0	0
T16	33364	0	0	0
T17	38546	0	0	0
T18	49953	0	0	0
T46	25943	0	0	0
T47	21261	0	0	0
T49	0	2	0	0
T50	0	3	0	0
T60	0	11	0	0
T84	0	3	0	0
T95	0	4	0	0
T120	0	9	0	0
T159	0	1	0	0
T160	0	3	0	0
T161	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108631965	1958	0	0
T27	32375	0	0	0
T28	43395	0	0	0
T49	262140	5	0	0
T73	216848	0	0	0
T85	0	9	0	0
T96	0	9	0	0
T123	0	87	0	0
T124	0	11	0	0
T151	0	2	0	0
T162	0	2	0	0
T163	0	10	0	0
T164	0	40	0	0
T165	0	446	0	0
T166	6563	0	0	0
T167	1889	0	0	0
T168	46367	0	0	0
T169	22599	0	0	0
T170	41836	0	0	0
T171	9877	0	0	0