Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1661060	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1883583

1

T1

2063

T2

39

T3

959

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3197662	1			T1	2815		T2	158		T3	1112
values[0x0]	172769	1			T1	414		T3	259		T4	1759
values[0x1]	174212	1			T1	386		T3	237		T4	1779

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1318987	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2225656

1

T1

2400

T2

67

T3

1091

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9817	1			T1	19		T2	1		T4	154
valid_sources[0x01]	12328	1			T1	5		T4	135		T12	5
valid_sources[0x02]	13150	1			T1	6		T4	149		T14	3
valid_sources[0x03]	10080	1			T1	12		T2	1		T4	130
valid_sources[0x04]	11072	1			T1	21		T4	112		T14	3
valid_sources[0x05]	10409	1			T1	10		T4	125		T13	2
valid_sources[0x06]	11489	1			T1	20		T4	123		T14	5
valid_sources[0x07]	11093	1			T1	7		T4	135		T14	4
valid_sources[0x08]	10234	1			T1	14		T2	10		T4	129
valid_sources[0x09]	10675	1			T1	25		T4	137		T14	4
valid_sources[0x0a]	9999	1			T1	31		T4	123		T14	4
valid_sources[0x0b]	9719	1			T1	20		T4	144		T12	3
valid_sources[0x0c]	10627	1			T1	9		T4	155		T14	2
valid_sources[0x0d]	14258	1			T1	10		T4	136		T14	3
valid_sources[0x0e]	10089	1			T1	16		T4	141		T12	1
valid_sources[0x0f]	10638	1			T1	23		T4	154		T14	5
valid_sources[0x10]	10559	1			T1	6		T4	134		T14	4
valid_sources[0x11]	9992	1			T1	14		T4	138		T14	7
valid_sources[0x12]	9995	1			T1	10		T4	128		T14	6
valid_sources[0x13]	17026	1			T1	14		T2	2		T4	146
valid_sources[0x14]	38026	1			T1	5		T4	128		T14	3
valid_sources[0x15]	9489	1			T1	16		T4	135		T14	9
valid_sources[0x16]	10149	1			T1	7		T4	124		T14	3
valid_sources[0x17]	13112	1			T1	15		T4	150		T11	1253
valid_sources[0x18]	34282	1			T1	6		T2	4		T4	142
valid_sources[0x19]	10576	1			T1	15		T4	129		T14	2
valid_sources[0x1a]	10695	1			T1	13		T4	160		T13	1
valid_sources[0x1b]	10212	1			T1	7		T4	135		T12	5
valid_sources[0x1c]	10442	1			T1	3		T4	135		T14	9
valid_sources[0x1d]	10296	1			T1	8		T4	108		T12	8
valid_sources[0x1e]	11891	1			T1	20		T4	123		T14	4
valid_sources[0x1f]	10643	1			T1	14		T4	133		T14	5
valid_sources[0x20]	12149	1			T1	20		T4	119		T14	6
valid_sources[0x21]	10390	1			T1	13		T4	158		T14	4
valid_sources[0x22]	33087	1			T1	5		T2	5		T4	129
valid_sources[0x23]	10660	1			T1	30		T4	123		T14	3
valid_sources[0x24]	9900	1			T1	8		T2	4		T4	136
valid_sources[0x25]	10420	1			T1	9		T4	118		T14	5
valid_sources[0x26]	57707	1			T1	22		T2	1		T4	124
valid_sources[0x27]	10543	1			T1	26		T2	5		T4	159
valid_sources[0x28]	11843	1			T1	44		T4	112		T12	6
valid_sources[0x29]	9832	1			T1	5		T4	127		T14	5
valid_sources[0x2a]	22107	1			T1	14		T4	125		T14	6
valid_sources[0x2b]	9767	1			T1	16		T2	3		T4	133
valid_sources[0x2c]	10655	1			T1	10		T2	9		T4	124
valid_sources[0x2d]	15788	1			T1	8		T4	146		T12	6
valid_sources[0x2e]	9705	1			T1	27		T2	1		T4	156
valid_sources[0x2f]	10760	1			T1	21		T4	129		T14	2
valid_sources[0x30]	14403	1			T1	24		T4	127		T14	10
valid_sources[0x31]	10687	1			T1	19		T2	1		T4	135
valid_sources[0x32]	11427	1			T1	16		T4	164		T14	7
valid_sources[0x33]	10161	1			T1	1		T4	126		T12	2
valid_sources[0x34]	10006	1			T1	20		T4	147		T14	3
valid_sources[0x35]	10204	1			T1	21		T4	152		T13	2
valid_sources[0x36]	11526	1			T1	16		T4	135		T14	7
valid_sources[0x37]	11124	1			T1	23		T4	134		T12	1
valid_sources[0x38]	31606	1			T1	8		T4	119		T14	6
valid_sources[0x39]	11526	1			T1	8		T2	1		T4	128
valid_sources[0x3a]	9820	1			T1	10		T4	131		T12	1
valid_sources[0x3b]	9891	1			T1	12		T4	121		T14	8
valid_sources[0x3c]	9551	1			T1	10		T4	113		T14	5
valid_sources[0x3d]	10890	1			T1	24		T2	1		T4	119
valid_sources[0x3e]	9410	1			T1	9		T4	130		T14	3
valid_sources[0x3f]	10276	1			T1	9		T4	135		T14	7
valid_sources[0x40]	10271	1			T1	13		T4	137		T14	4
valid_sources[0x41]	9831	1			T1	3		T4	113		T14	3
valid_sources[0x42]	10736	1			T1	2		T4	128		T14	7
valid_sources[0x43]	12319	1			T1	19		T4	124		T14	9
valid_sources[0x44]	14588	1			T1	13		T2	4		T4	127
valid_sources[0x45]	11012	1			T1	5		T2	1		T4	116
valid_sources[0x46]	9389	1			T1	1		T4	130		T14	9
valid_sources[0x47]	10280	1			T1	8		T4	130		T14	9
valid_sources[0x48]	10809	1			T1	19		T4	137		T14	7
valid_sources[0x49]	16349	1			T1	13		T2	4		T4	109
valid_sources[0x4a]	40546	1			T1	27		T4	126		T14	7
valid_sources[0x4b]	9826	1			T1	4		T4	133		T12	6
valid_sources[0x4c]	10605	1			T1	21		T4	136		T12	5
valid_sources[0x4d]	15428	1			T1	11		T4	112		T14	5
valid_sources[0x4e]	12136	1			T1	13		T4	117		T14	1
valid_sources[0x4f]	10480	1			T1	33		T2	1		T4	144
valid_sources[0x50]	12808	1			T1	11		T4	144		T12	1
valid_sources[0x51]	12719	1			T1	8		T4	128		T14	10
valid_sources[0x52]	9948	1			T1	25		T4	131		T14	3
valid_sources[0x53]	13204	1			T1	11		T4	118		T13	35
valid_sources[0x54]	53571	1			T1	10		T2	2		T4	142
valid_sources[0x55]	10497	1			T1	18		T4	121		T13	5
valid_sources[0x56]	15216	1			T1	13		T2	5		T4	140
valid_sources[0x57]	10446	1			T1	17		T4	123		T14	6
valid_sources[0x58]	10119	1			T1	25		T4	138		T14	9
valid_sources[0x59]	10222	1			T1	9		T4	123		T14	3
valid_sources[0x5a]	10302	1			T1	26		T4	123		T14	6
valid_sources[0x5b]	10167	1			T1	9		T4	125		T14	5
valid_sources[0x5c]	10429	1			T1	4		T4	108		T12	1
valid_sources[0x5d]	10060	1			T1	11		T4	149		T12	1
valid_sources[0x5e]	10345	1			T1	10		T4	131		T12	1
valid_sources[0x5f]	10236	1			T1	26		T4	127		T14	5
valid_sources[0x60]	9985	1			T1	12		T4	127		T14	4
valid_sources[0x61]	9913	1			T1	20		T2	6		T4	107
valid_sources[0x62]	10165	1			T1	14		T2	1		T4	135
valid_sources[0x63]	10261	1			T1	18		T4	129		T14	3
valid_sources[0x64]	12156	1			T1	12		T4	89		T14	7
valid_sources[0x65]	10663	1			T1	14		T4	125		T12	8
valid_sources[0x66]	10233	1			T1	15		T4	121		T14	5
valid_sources[0x67]	9597	1			T1	15		T4	129		T14	9
valid_sources[0x68]	10022	1			T1	32		T4	142		T12	2
valid_sources[0x69]	12668	1			T1	14		T4	103		T14	8
valid_sources[0x6a]	10547	1			T1	13		T4	141		T12	1
valid_sources[0x6b]	11476	1			T1	7		T4	124		T14	6
valid_sources[0x6c]	9902	1			T1	10		T4	128		T12	3
valid_sources[0x6d]	10167	1			T1	12		T2	6		T4	133
valid_sources[0x6e]	10598	1			T1	17		T4	146		T14	12
valid_sources[0x6f]	10304	1			T1	17		T2	1		T4	151
valid_sources[0x70]	10263	1			T1	15		T4	150		T14	4
valid_sources[0x71]	14143	1			T1	8		T4	121		T14	7
valid_sources[0x72]	11357	1			T1	15		T4	125		T14	5
valid_sources[0x73]	10354	1			T1	15		T4	149		T12	3
valid_sources[0x74]	10059	1			T1	13		T4	120		T12	1
valid_sources[0x75]	14147	1			T1	26		T4	116		T14	2
valid_sources[0x76]	9997	1			T1	7		T4	96		T14	11
valid_sources[0x77]	10488	1			T1	17		T4	152		T14	9
valid_sources[0x78]	10761	1			T1	18		T2	3		T4	129
valid_sources[0x79]	12473	1			T1	12		T3	1608		T4	141
valid_sources[0x7a]	10379	1			T1	37		T4	132		T15	723
valid_sources[0x7b]	10202	1			T1	5		T4	109		T14	7
valid_sources[0x7c]	10079	1			T1	9		T4	115		T14	6
valid_sources[0x7d]	10098	1			T1	8		T4	140		T14	8
valid_sources[0x7e]	10568	1			T1	3		T4	134		T14	9
valid_sources[0x7f]	10520	1			T1	19		T4	114		T14	5
valid_sources[0x80]	27854	1			T1	18		T4	149		T12	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1584384

1

T1

1370

T2

39

T3

526

values[0x0]

all_enables

biggest_size

149835

1

T1

358

T3

224

T4

1541

values[0x1]

all_enables

biggest_size

149364

1

T1

335

T3

209

T4

1544