Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	101320485	16330	0	0
claim_transition_if_regwen_rd_A	101320485	1485	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101320485	16330	0	0
T4	108562	1	0	0
T5	35336	0	0	0
T6	36213	0	0	0
T11	30957	0	0	0
T12	4465	0	0	0
T13	2557	0	0	0
T14	32330	0	0	0
T15	171489	9	0	0
T22	25795	0	0	0
T23	40762	0	0	0
T50	0	13	0	0
T51	0	6	0	0
T91	0	2	0	0
T99	0	20	0	0
T102	0	5	0	0
T103	0	2	0	0
T144	0	11	0	0
T145	0	17	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101320485	1485	0	0
T79	33278	0	0	0
T110	0	21	0	0
T120	0	34	0	0
T124	0	13	0	0
T146	105927	4	0	0
T147	0	6	0	0
T148	0	15	0	0
T149	0	8	0	0
T150	0	1	0	0
T151	0	26	0	0
T152	0	2	0	0
T153	1290	0	0	0
T154	21383	0	0	0
T155	61587	0	0	0
T156	40764	0	0	0
T157	47219	0	0	0
T158	2235	0	0	0
T159	11220	0	0	0
T160	30762	0	0	0