Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1687691	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1905528

1

T1

1899

T2

11

T3

839

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3247993	1			T1	2583		T3	756		T4	6181
values[0x0]	171932	1			T1	367		T2	22		T3	271
values[0x1]	173294	1			T1	369		T2	20		T3	289

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1341120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2252099

1

T1

2188

T2

12

T3

949

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9066	1			T1	15		T3	5		T59	15
valid_sources[0x01]	9531	1			T1	20		T2	2		T3	4
valid_sources[0x02]	9739	1			T1	17		T16	5		T59	16
valid_sources[0x03]	12423	1			T1	15		T3	7		T16	10
valid_sources[0x04]	9927	1			T1	18		T16	5		T59	14
valid_sources[0x05]	9239	1			T1	7		T16	2		T59	15
valid_sources[0x06]	9026	1			T1	10		T3	1		T12	1
valid_sources[0x07]	8993	1			T1	10		T16	9		T59	16
valid_sources[0x08]	9841	1			T1	15		T59	15		T37	7
valid_sources[0x09]	13438	1			T1	10		T3	19		T14	3
valid_sources[0x0a]	9383	1			T1	14		T14	2		T59	16
valid_sources[0x0b]	10701	1			T1	14		T3	22		T16	1
valid_sources[0x0c]	9353	1			T1	14		T14	1		T16	8
valid_sources[0x0d]	9034	1			T1	12		T3	9		T59	22
valid_sources[0x0e]	9655	1			T1	11		T3	1		T8	2
valid_sources[0x0f]	9550	1			T1	3		T2	1		T3	2
valid_sources[0x10]	9230	1			T1	8		T3	1		T14	3
valid_sources[0x11]	100248	1			T1	13		T3	23		T16	1
valid_sources[0x12]	9707	1			T1	20		T3	3		T16	9
valid_sources[0x13]	9085	1			T1	15		T3	9		T12	2
valid_sources[0x14]	9713	1			T1	13		T3	1		T16	7
valid_sources[0x15]	9556	1			T1	14		T16	3		T59	11
valid_sources[0x16]	10358	1			T1	13		T3	2		T16	1
valid_sources[0x17]	9339	1			T1	11		T3	10		T16	9
valid_sources[0x18]	8935	1			T1	13		T59	13		T37	1
valid_sources[0x19]	16110	1			T1	5		T3	12		T59	13
valid_sources[0x1a]	9355	1			T1	15		T16	20		T59	19
valid_sources[0x1b]	9247	1			T1	8		T12	3		T21	3
valid_sources[0x1c]	9317	1			T1	12		T3	2		T14	4
valid_sources[0x1d]	10079	1			T1	11		T16	6		T59	19
valid_sources[0x1e]	9571	1			T1	15		T3	10		T8	1
valid_sources[0x1f]	9780	1			T1	13		T16	4		T59	18
valid_sources[0x20]	8991	1			T1	15		T59	16		T60	2
valid_sources[0x21]	9589	1			T1	5		T16	1		T59	17
valid_sources[0x22]	20563	1			T1	18		T16	11		T59	22
valid_sources[0x23]	10857	1			T1	12		T3	6		T14	1
valid_sources[0x24]	9520	1			T1	8		T3	13		T16	3
valid_sources[0x25]	64115	1			T1	24		T3	5		T16	14
valid_sources[0x26]	11209	1			T1	14		T3	2		T16	2
valid_sources[0x27]	9455	1			T1	14		T3	13		T14	3
valid_sources[0x28]	9104	1			T1	15		T16	6		T59	25
valid_sources[0x29]	9260	1			T1	20		T3	8		T16	2
valid_sources[0x2a]	9339	1			T1	12		T14	6		T16	7
valid_sources[0x2b]	9570	1			T1	4		T14	4		T16	4
valid_sources[0x2c]	9667	1			T1	14		T3	3		T21	4
valid_sources[0x2d]	9922	1			T1	14		T3	5		T14	5
valid_sources[0x2e]	9199	1			T1	8		T16	2		T59	18
valid_sources[0x2f]	12410	1			T1	7		T16	1		T59	19
valid_sources[0x30]	9382	1			T1	27		T3	1		T14	1
valid_sources[0x31]	9354	1			T1	8		T3	7		T16	3
valid_sources[0x32]	9423	1			T1	23		T14	1		T16	5
valid_sources[0x33]	25605	1			T1	15		T14	4		T59	16
valid_sources[0x34]	10320	1			T1	15		T3	10		T14	1
valid_sources[0x35]	9196	1			T1	20		T3	1		T16	1
valid_sources[0x36]	9197	1			T1	7		T3	5		T14	1
valid_sources[0x37]	20817	1			T1	6		T14	5		T16	5
valid_sources[0x38]	9419	1			T1	21		T3	39		T16	2
valid_sources[0x39]	9169	1			T1	13		T3	8		T14	3
valid_sources[0x3a]	9692	1			T1	12		T3	23		T14	2
valid_sources[0x3b]	8754	1			T1	14		T12	1		T14	7
valid_sources[0x3c]	8668	1			T1	5		T14	2		T16	5
valid_sources[0x3d]	8931	1			T1	14		T12	1		T14	5
valid_sources[0x3e]	9710	1			T1	10		T3	4		T14	2
valid_sources[0x3f]	9507	1			T1	9		T2	1		T3	12
valid_sources[0x40]	16053	1			T1	15		T3	14		T4	6901
valid_sources[0x41]	9838	1			T1	13		T3	5		T21	2
valid_sources[0x42]	8690	1			T1	13		T3	1		T14	4
valid_sources[0x43]	42685	1			T1	16		T59	19		T60	2
valid_sources[0x44]	9109	1			T1	9		T16	16		T59	25
valid_sources[0x45]	9023	1			T1	11		T3	6		T16	1
valid_sources[0x46]	18084	1			T1	11		T3	6		T12	1
valid_sources[0x47]	8635	1			T1	13		T3	7		T8	1
valid_sources[0x48]	9496	1			T1	15		T59	18		T37	6
valid_sources[0x49]	9058	1			T1	16		T16	5		T59	15
valid_sources[0x4a]	73493	1			T1	15		T3	13		T14	3
valid_sources[0x4b]	9282	1			T1	10		T3	4		T14	1
valid_sources[0x4c]	9479	1			T1	16		T3	3		T16	5
valid_sources[0x4d]	10486	1			T1	11		T3	4		T16	12
valid_sources[0x4e]	9520	1			T1	11		T3	19		T12	1
valid_sources[0x4f]	9185	1			T1	13		T14	3		T16	5
valid_sources[0x50]	10689	1			T1	22		T14	3		T16	19
valid_sources[0x51]	10435	1			T1	9		T3	10		T16	7
valid_sources[0x52]	11630	1			T1	19		T3	2		T16	5
valid_sources[0x53]	29292	1			T1	16		T3	6		T14	2
valid_sources[0x54]	13770	1			T1	14		T3	5		T59	17
valid_sources[0x55]	13554	1			T1	25		T16	1		T59	29
valid_sources[0x56]	9467	1			T1	6		T3	11		T14	5
valid_sources[0x57]	12375	1			T1	17		T3	4		T14	2
valid_sources[0x58]	9380	1			T1	4		T16	1		T59	20
valid_sources[0x59]	9406	1			T1	9		T3	4		T16	12
valid_sources[0x5a]	9306	1			T1	15		T2	3		T59	20
valid_sources[0x5b]	8965	1			T1	13		T3	7		T14	3
valid_sources[0x5c]	9473	1			T1	12		T3	1		T16	8
valid_sources[0x5d]	10687	1			T1	21		T3	5		T14	5
valid_sources[0x5e]	10785	1			T1	13		T2	1		T3	2
valid_sources[0x5f]	9211	1			T1	11		T3	17		T16	1
valid_sources[0x60]	9911	1			T1	6		T14	2		T59	27
valid_sources[0x61]	14535	1			T1	14		T14	5		T16	7
valid_sources[0x62]	9340	1			T1	3		T3	1		T16	10
valid_sources[0x63]	9845	1			T1	14		T3	8		T14	4
valid_sources[0x64]	9623	1			T1	14		T16	15		T59	25
valid_sources[0x65]	9085	1			T1	10		T3	3		T16	5
valid_sources[0x66]	9466	1			T1	5		T59	16		T37	3
valid_sources[0x67]	99470	1			T1	21		T3	16		T16	1
valid_sources[0x68]	9119	1			T1	9		T3	12		T14	4
valid_sources[0x69]	46976	1			T1	7		T3	2		T14	4
valid_sources[0x6a]	9095	1			T1	18		T14	4		T59	17
valid_sources[0x6b]	9209	1			T1	23		T3	37		T14	9
valid_sources[0x6c]	10318	1			T1	9		T3	7		T16	2
valid_sources[0x6d]	8853	1			T1	4		T16	1		T59	17
valid_sources[0x6e]	10465	1			T1	13		T14	6		T16	12
valid_sources[0x6f]	9297	1			T1	8		T14	1		T21	4
valid_sources[0x70]	9372	1			T1	14		T16	1		T59	18
valid_sources[0x71]	10527	1			T1	11		T14	1		T16	7
valid_sources[0x72]	9067	1			T1	11		T3	2		T14	2
valid_sources[0x73]	9416	1			T1	15		T14	7		T16	5
valid_sources[0x74]	9644	1			T1	26		T16	9		T59	13
valid_sources[0x75]	9368	1			T1	11		T16	4		T59	12
valid_sources[0x76]	9498	1			T1	12		T14	6		T59	15
valid_sources[0x77]	9130	1			T1	8		T3	5		T16	4
valid_sources[0x78]	9502	1			T1	17		T14	2		T16	7
valid_sources[0x79]	9434	1			T1	15		T14	2		T16	8
valid_sources[0x7a]	27020	1			T1	12		T3	10		T16	7
valid_sources[0x7b]	19082	1			T1	12		T3	20		T16	2
valid_sources[0x7c]	9109	1			T1	14		T3	8		T14	1
valid_sources[0x7d]	9358	1			T1	10		T3	13		T59	17
valid_sources[0x7e]	9121	1			T1	11		T14	7		T16	4
valid_sources[0x7f]	10778	1			T1	7		T16	9		T59	34
valid_sources[0x80]	8999	1			T1	21		T2	6		T16	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1607854

1

T1

1264

T3

350

T4

2976

values[0x0]

all_enables

biggest_size

149077

1

T1

308

T2

5

T3

235

values[0x1]

all_enables

biggest_size

148597

1

T1

327

T2

6

T3

254