Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	116020044	16548	0	0
claim_transition_if_regwen_rd_A	116020044	1583	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116020044	16548	0	0
T22	50537	0	0	0
T35	1493	0	0	0
T42	58245	0	0	0
T82	546292	3	0	0
T83	1972	0	0	0
T92	0	2	0	0
T93	0	2	0	0
T107	0	2	0	0
T112	0	9	0	0
T122	0	3	0	0
T161	0	5	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	3141	0	0	0
T166	46535	0	0	0
T167	919	0	0	0
T168	8828	0	0	0
T169	54875	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116020044	1583	0	0
T75	11969	0	0	0
T107	152738	5	0	0
T108	5283	0	0	0
T109	19004	0	0	0
T110	30179	0	0	0
T111	62980	0	0	0
T112	182504	0	0	0
T113	46509	0	0	0
T114	1524	0	0	0
T119	0	9	0	0
T122	0	16	0	0
T125	0	42	0	0
T126	0	58	0	0
T127	0	19	0	0
T144	0	13	0	0
T170	0	4	0	0
T171	0	11	0	0
T172	0	12	0	0
T173	474867	0	0	0