Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1508836 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1737588 1 T1 277 T2 1862 T9 530



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 2893683 1 T1 223 T2 2599 T9 452
values[0x0] 175979 1 T1 102 T2 335 T9 202
values[0x1] 176762 1 T1 90 T2 361 T9 206



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1197875 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2048549 1 T1 305 T2 2171 T9 615



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 11636 1 T2 9 T9 2 T11 17
valid_sources[0x01] 11447 1 T2 5 T9 4 T11 15
valid_sources[0x02] 11117 1 T2 5 T9 9 T11 11
valid_sources[0x03] 11740 1 T2 31 T9 3 T11 20
valid_sources[0x04] 10890 1 T2 14 T9 6 T11 10
valid_sources[0x05] 10468 1 T2 8 T9 3 T11 20
valid_sources[0x06] 14420 1 T2 10 T9 2 T11 14
valid_sources[0x07] 11934 1 T2 1 T9 6 T11 17
valid_sources[0x08] 11160 1 T9 3 T11 23 T4 6
valid_sources[0x09] 10984 1 T2 31 T9 4 T11 13
valid_sources[0x0a] 10813 1 T2 9 T9 7 T11 19
valid_sources[0x0b] 10804 1 T2 6 T9 2 T10 9
valid_sources[0x0c] 10840 1 T2 10 T9 1 T11 15
valid_sources[0x0d] 10668 1 T2 2 T9 4 T11 11
valid_sources[0x0e] 22648 1 T2 18 T11 17 T4 7
valid_sources[0x0f] 11101 1 T2 8 T9 4 T11 19
valid_sources[0x10] 12660 1 T2 14 T9 1 T11 18
valid_sources[0x11] 10652 1 T2 19 T11 12 T4 12
valid_sources[0x12] 11138 1 T2 2 T9 3 T11 15
valid_sources[0x13] 11366 1 T2 3 T9 2 T11 11
valid_sources[0x14] 10498 1 T2 21 T9 5 T11 13
valid_sources[0x15] 19804 1 T2 12 T9 7 T11 15
valid_sources[0x16] 11104 1 T2 18 T9 1 T11 8
valid_sources[0x17] 10751 1 T2 16 T9 1 T10 3
valid_sources[0x18] 11362 1 T2 3 T9 2 T11 16
valid_sources[0x19] 12003 1 T2 8 T9 4 T11 16
valid_sources[0x1a] 10849 1 T2 10 T9 3 T11 16
valid_sources[0x1b] 14799 1 T2 3 T9 5 T11 17
valid_sources[0x1c] 11069 1 T2 10 T9 9 T11 14
valid_sources[0x1d] 11026 1 T2 11 T9 4 T11 18
valid_sources[0x1e] 12772 1 T2 1 T9 2 T11 14
valid_sources[0x1f] 11546 1 T2 29 T9 3 T11 14
valid_sources[0x20] 10647 1 T2 12 T9 3 T11 11
valid_sources[0x21] 11245 1 T2 7 T9 1 T11 18
valid_sources[0x22] 13779 1 T9 3 T11 19 T4 10
valid_sources[0x23] 11213 1 T2 3 T9 5 T11 18
valid_sources[0x24] 12058 1 T2 28 T9 5 T11 17
valid_sources[0x25] 11386 1 T2 32 T9 2 T10 1
valid_sources[0x26] 12947 1 T2 10 T9 3 T11 10
valid_sources[0x27] 10749 1 T2 11 T9 2 T11 16
valid_sources[0x28] 10939 1 T2 4 T9 3 T11 18
valid_sources[0x29] 11695 1 T2 9 T9 4 T11 15
valid_sources[0x2a] 10992 1 T2 5 T9 1 T11 17
valid_sources[0x2b] 11523 1 T2 35 T9 10 T11 17
valid_sources[0x2c] 11379 1 T2 11 T9 1 T11 13
valid_sources[0x2d] 10756 1 T2 19 T9 5 T11 15
valid_sources[0x2e] 63639 1 T2 7 T11 14 T4 8
valid_sources[0x2f] 11518 1 T2 4 T9 2 T11 11
valid_sources[0x30] 11044 1 T2 19 T9 10 T11 15
valid_sources[0x31] 15798 1 T2 7 T9 3 T11 12
valid_sources[0x32] 11575 1 T2 14 T9 2 T11 22
valid_sources[0x33] 11895 1 T2 16 T9 1 T11 10
valid_sources[0x34] 10856 1 T2 19 T9 1 T11 22
valid_sources[0x35] 12178 1 T2 22 T9 3 T11 22
valid_sources[0x36] 11049 1 T2 22 T11 21 T4 5
valid_sources[0x37] 10698 1 T2 3 T9 3 T11 13
valid_sources[0x38] 10926 1 T2 7 T9 5 T11 16
valid_sources[0x39] 10891 1 T2 19 T11 10 T4 11
valid_sources[0x3a] 11220 1 T2 5 T9 9 T11 14
valid_sources[0x3b] 11876 1 T2 8 T9 5 T11 16
valid_sources[0x3c] 12595 1 T2 24 T9 4 T11 13
valid_sources[0x3d] 11099 1 T2 8 T9 4 T11 12
valid_sources[0x3e] 10924 1 T2 14 T9 4 T11 14
valid_sources[0x3f] 10804 1 T2 9 T9 4 T11 14
valid_sources[0x40] 11309 1 T2 13 T9 5 T11 27
valid_sources[0x41] 10712 1 T2 8 T9 4 T11 15
valid_sources[0x42] 11105 1 T2 1 T9 2 T11 12
valid_sources[0x43] 11338 1 T2 18 T9 6 T11 16
valid_sources[0x44] 11509 1 T2 21 T9 9 T11 20
valid_sources[0x45] 13496 1 T2 11 T9 5 T11 16
valid_sources[0x46] 10990 1 T2 7 T9 4 T11 12
valid_sources[0x47] 11378 1 T2 9 T9 10 T11 10
valid_sources[0x48] 11074 1 T2 20 T9 2 T11 18
valid_sources[0x49] 10827 1 T2 14 T9 2 T11 13
valid_sources[0x4a] 11533 1 T2 10 T11 17 T4 13
valid_sources[0x4b] 11285 1 T2 19 T9 3 T11 19
valid_sources[0x4c] 12158 1 T2 13 T9 3 T11 21
valid_sources[0x4d] 11037 1 T2 10 T11 10 T4 6
valid_sources[0x4e] 12409 1 T2 3 T9 3 T11 12
valid_sources[0x4f] 12275 1 T2 8 T9 2 T11 10
valid_sources[0x50] 11504 1 T2 31 T9 7 T11 13
valid_sources[0x51] 10920 1 T2 15 T9 1 T11 13
valid_sources[0x52] 10774 1 T2 19 T9 2 T11 15
valid_sources[0x53] 11048 1 T2 13 T9 3 T11 17
valid_sources[0x54] 11231 1 T2 12 T9 3 T11 16
valid_sources[0x55] 11069 1 T2 14 T9 3 T11 19
valid_sources[0x56] 11113 1 T2 8 T9 8 T11 21
valid_sources[0x57] 11429 1 T2 18 T9 1 T11 24
valid_sources[0x58] 15294 1 T2 6 T9 4 T11 10
valid_sources[0x59] 11289 1 T2 6 T9 1 T11 7
valid_sources[0x5a] 15036 1 T2 22 T9 4 T11 15
valid_sources[0x5b] 11084 1 T2 10 T9 4 T11 13
valid_sources[0x5c] 11033 1 T2 5 T9 5 T11 11
valid_sources[0x5d] 11019 1 T2 24 T9 7 T11 15
valid_sources[0x5e] 10910 1 T2 40 T9 4 T11 10
valid_sources[0x5f] 10985 1 T2 18 T9 3 T11 12
valid_sources[0x60] 14059 1 T2 13 T9 2 T11 11
valid_sources[0x61] 17582 1 T2 9 T9 7 T11 13
valid_sources[0x62] 18177 1 T9 2 T11 7 T4 17
valid_sources[0x63] 11384 1 T2 23 T9 2 T11 13
valid_sources[0x64] 14347 1 T2 11 T9 5 T11 14
valid_sources[0x65] 12797 1 T2 26 T9 9 T11 14
valid_sources[0x66] 13453 1 T2 1 T9 4 T11 12
valid_sources[0x67] 11147 1 T2 7 T9 6 T11 14
valid_sources[0x68] 14147 1 T2 6 T9 3 T11 21
valid_sources[0x69] 14011 1 T2 3 T9 1 T11 18
valid_sources[0x6a] 13190 1 T2 11 T11 15 T4 10
valid_sources[0x6b] 11264 1 T2 7 T9 2 T11 12
valid_sources[0x6c] 11106 1 T2 31 T9 1 T11 17
valid_sources[0x6d] 10562 1 T2 9 T11 9 T4 9
valid_sources[0x6e] 10935 1 T2 10 T9 3 T11 12
valid_sources[0x6f] 12065 1 T2 7 T10 2 T11 12
valid_sources[0x70] 10691 1 T2 12 T9 4 T11 14
valid_sources[0x71] 11723 1 T2 13 T9 3 T11 14
valid_sources[0x72] 11013 1 T2 13 T11 18 T4 3
valid_sources[0x73] 14996 1 T2 6 T9 1 T11 18
valid_sources[0x74] 11550 1 T2 6 T9 5 T11 10
valid_sources[0x75] 12400 1 T2 15 T9 1 T11 7
valid_sources[0x76] 11015 1 T2 9 T9 9 T11 17
valid_sources[0x77] 14545 1 T2 3 T9 2 T11 11
valid_sources[0x78] 11035 1 T2 11 T9 6 T11 14
valid_sources[0x79] 14143 1 T2 17 T9 7 T11 14
valid_sources[0x7a] 10667 1 T2 8 T9 5 T11 19
valid_sources[0x7b] 10985 1 T2 22 T9 2 T11 10
valid_sources[0x7c] 11333 1 T2 18 T9 2 T11 8
valid_sources[0x7d] 11923 1 T2 9 T9 5 T11 17
valid_sources[0x7e] 10615 1 T2 22 T9 6 T11 14
valid_sources[0x7f] 11392 1 T2 25 T9 2 T11 4
valid_sources[0x80] 12233 1 T2 28 T11 10 T4 5



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 1433287 1 T1 109 T2 1256 T9 164
values[0x0] all_enables biggest_size 152818 1 T1 90 T2 287 T9 181
values[0x1] all_enables biggest_size 151483 1 T1 78 T2 319 T9 185

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%