Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	115764449	18019	0	0
claim_transition_if_regwen_rd_A	115764449	779	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115764449	18019	0	0
T40	40314	0	0	0
T48	45185	0	0	0
T56	18218	0	0	0
T89	114795	6	0	0
T92	0	5	0	0
T93	0	1	0	0
T94	146413	0	0	0
T156	0	5	0	0
T159	0	1	0	0
T160	0	19	0	0
T161	0	1	0	0
T162	0	4	0	0
T163	0	16	0	0
T164	0	4	0	0
T165	63384	0	0	0
T166	16969	0	0	0
T167	31354	0	0	0
T168	22686	0	0	0
T169	24190	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115764449	779	0	0
T81	3890	0	0	0
T91	20988	0	0	0
T95	0	6	0	0
T127	0	35	0	0
T128	0	63	0	0
T130	0	4	0	0
T162	223736	6	0	0
T164	0	18	0	0
T170	0	7	0	0
T171	0	5	0	0
T172	0	14	0	0
T173	0	4	0	0
T174	29241	0	0	0
T175	36012	0	0	0
T176	7190	0	0	0
T177	1374	0	0	0
T178	5397	0	0	0
T179	19098	0	0	0
T180	42361	0	0	0