Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1434292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1653268

1

T2

1552

T3

212

T9

2420

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2751910	1			T2	2866		T3	327		T9	4655
values[0x0]	167920	1			T2	77		T3	38		T9	70
values[0x1]	167730	1			T2	84		T3	41		T9	81

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1137870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1949690

1

T2

1869

T3

249

T9

2905

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9554	1			T2	14		T3	8		T10	3
valid_sources[0x01]	9506	1			T2	33		T3	4		T10	6
valid_sources[0x02]	8922	1			T2	6		T10	2		T14	5
valid_sources[0x03]	9414	1			T2	4		T3	5		T10	8
valid_sources[0x04]	9023	1			T2	2		T3	1		T10	7
valid_sources[0x05]	14219	1			T2	23		T10	12		T13	4
valid_sources[0x06]	10528	1			T2	6		T10	14		T14	5
valid_sources[0x07]	9716	1			T2	30		T10	6		T11	2
valid_sources[0x08]	8783	1			T2	29		T10	5		T14	1
valid_sources[0x09]	9441	1			T2	2		T10	5		T14	2
valid_sources[0x0a]	16513	1			T2	8		T10	6		T11	3
valid_sources[0x0b]	9346	1			T2	13		T10	3		T11	1
valid_sources[0x0c]	9220	1			T2	9		T3	7		T10	8
valid_sources[0x0d]	9652	1			T2	1		T10	6		T14	3
valid_sources[0x0e]	28361	1			T2	8		T10	9		T11	10
valid_sources[0x0f]	9613	1			T2	11		T10	8		T4	2
valid_sources[0x10]	155885	1			T2	2		T10	6		T11	10
valid_sources[0x11]	9066	1			T2	6		T10	4		T11	6
valid_sources[0x12]	9447	1			T2	31		T10	7		T14	3
valid_sources[0x13]	9691	1			T2	8		T10	4		T13	1
valid_sources[0x14]	12314	1			T2	24		T10	10		T4	1
valid_sources[0x15]	9425	1			T2	8		T10	11		T14	3
valid_sources[0x16]	9924	1			T2	22		T3	2		T10	9
valid_sources[0x17]	9163	1			T2	22		T10	8		T4	1
valid_sources[0x18]	10553	1			T2	13		T10	6		T13	6
valid_sources[0x19]	60547	1			T2	8		T3	7		T10	3
valid_sources[0x1a]	9218	1			T2	4		T10	15		T13	18
valid_sources[0x1b]	10845	1			T2	8		T9	17		T10	5
valid_sources[0x1c]	15731	1			T2	12		T10	8		T11	6
valid_sources[0x1d]	9153	1			T2	13		T3	2		T10	5
valid_sources[0x1e]	9095	1			T2	17		T3	5		T10	11
valid_sources[0x1f]	9457	1			T2	4		T3	15		T10	8
valid_sources[0x20]	10227	1			T2	17		T10	3		T14	3
valid_sources[0x21]	9398	1			T2	14		T10	5		T11	5
valid_sources[0x22]	9766	1			T2	3		T3	17		T10	10
valid_sources[0x23]	11304	1			T2	19		T10	5		T14	2
valid_sources[0x24]	9149	1			T2	5		T3	9		T10	7
valid_sources[0x25]	10460	1			T2	7		T10	8		T30	7
valid_sources[0x26]	12988	1			T2	16		T10	11		T14	3
valid_sources[0x27]	14501	1			T2	7		T9	4653		T10	6
valid_sources[0x28]	11781	1			T2	15		T3	1		T10	7
valid_sources[0x29]	9087	1			T2	8		T10	8		T14	1
valid_sources[0x2a]	11135	1			T2	8		T9	17		T10	10
valid_sources[0x2b]	9144	1			T2	21		T3	5		T10	4
valid_sources[0x2c]	9493	1			T2	15		T3	4		T10	6
valid_sources[0x2d]	9290	1			T2	10		T10	10		T11	1
valid_sources[0x2e]	9330	1			T2	9		T3	5		T10	8
valid_sources[0x2f]	9544	1			T2	22		T10	13		T11	3
valid_sources[0x30]	10491	1			T2	19		T3	9		T10	8
valid_sources[0x31]	9263	1			T2	4		T3	1		T10	6
valid_sources[0x32]	12712	1			T2	11		T10	5		T14	3
valid_sources[0x33]	9194	1			T2	13		T10	9		T14	4
valid_sources[0x34]	10880	1			T2	13		T3	4		T10	2
valid_sources[0x35]	10036	1			T2	11		T3	1		T10	11
valid_sources[0x36]	9619	1			T2	16		T3	8		T10	6
valid_sources[0x37]	9316	1			T2	18		T10	7		T11	4
valid_sources[0x38]	9408	1			T2	7		T10	3		T11	2
valid_sources[0x39]	37281	1			T2	10		T3	4		T10	9
valid_sources[0x3a]	9377	1			T2	6		T10	8		T11	1
valid_sources[0x3b]	9685	1			T2	19		T10	10		T11	1
valid_sources[0x3c]	10446	1			T2	17		T10	9		T13	10
valid_sources[0x3d]	10292	1			T2	6		T3	3		T10	5
valid_sources[0x3e]	20181	1			T2	14		T3	3		T10	11
valid_sources[0x3f]	9378	1			T2	7		T3	1		T10	7
valid_sources[0x40]	9127	1			T2	2		T3	6		T10	4
valid_sources[0x41]	9935	1			T2	26		T3	1		T10	8
valid_sources[0x42]	9211	1			T2	37		T10	6		T14	2
valid_sources[0x43]	8778	1			T2	9		T10	13		T14	2
valid_sources[0x44]	9326	1			T2	1		T10	4		T4	1
valid_sources[0x45]	9067	1			T2	10		T3	7		T10	5
valid_sources[0x46]	9349	1			T2	19		T10	8		T11	2
valid_sources[0x47]	11714	1			T2	9		T3	6		T10	7
valid_sources[0x48]	9378	1			T2	4		T3	8		T10	5
valid_sources[0x49]	10099	1			T2	4		T10	3		T13	17
valid_sources[0x4a]	10574	1			T2	2		T10	6		T14	4
valid_sources[0x4b]	10115	1			T2	23		T3	14		T10	2
valid_sources[0x4c]	15051	1			T2	8		T10	18		T11	2
valid_sources[0x4d]	9356	1			T2	15		T10	3		T14	2
valid_sources[0x4e]	9545	1			T2	15		T3	16		T10	7
valid_sources[0x4f]	9274	1			T2	16		T10	6		T14	1
valid_sources[0x50]	9536	1			T2	9		T3	4		T10	10
valid_sources[0x51]	17319	1			T2	9		T3	2		T10	3
valid_sources[0x52]	9180	1			T2	15		T10	10		T13	7
valid_sources[0x53]	12514	1			T2	3		T3	1		T10	5
valid_sources[0x54]	9287	1			T2	18		T10	6		T14	1
valid_sources[0x55]	9376	1			T2	25		T10	9		T14	5
valid_sources[0x56]	9430	1			T2	5		T3	4		T10	12
valid_sources[0x57]	39267	1			T2	18		T3	9		T10	7
valid_sources[0x58]	26552	1			T2	4		T3	3		T10	8
valid_sources[0x59]	9116	1			T2	10		T10	6		T11	7
valid_sources[0x5a]	9580	1			T2	30		T3	6		T10	8
valid_sources[0x5b]	10010	1			T2	30		T10	3		T14	3
valid_sources[0x5c]	9711	1			T2	8		T3	5		T10	10
valid_sources[0x5d]	63539	1			T2	6		T10	9		T14	3
valid_sources[0x5e]	10119	1			T2	6		T10	7		T13	14
valid_sources[0x5f]	9285	1			T2	14		T10	4		T11	1
valid_sources[0x60]	9422	1			T2	9		T3	1		T10	11
valid_sources[0x61]	9510	1			T2	13		T10	11		T13	9
valid_sources[0x62]	9282	1			T2	14		T10	2		T13	1
valid_sources[0x63]	9543	1			T2	20		T10	4		T11	2
valid_sources[0x64]	9548	1			T2	4		T10	5		T14	6
valid_sources[0x65]	8969	1			T2	14		T10	2		T14	1
valid_sources[0x66]	9278	1			T2	2		T10	3		T14	1
valid_sources[0x67]	10715	1			T10	11		T13	9		T14	2
valid_sources[0x68]	9146	1			T2	22		T10	8		T11	10
valid_sources[0x69]	11023	1			T2	6		T10	3		T14	7
valid_sources[0x6a]	8899	1			T2	8		T10	2		T14	2
valid_sources[0x6b]	9154	1			T2	18		T3	5		T10	8
valid_sources[0x6c]	8979	1			T2	6		T10	17		T11	1
valid_sources[0x6d]	9578	1			T2	14		T3	7		T10	12
valid_sources[0x6e]	9464	1			T2	24		T10	10		T11	2
valid_sources[0x6f]	9355	1			T2	19		T3	1		T10	6
valid_sources[0x70]	9326	1			T2	12		T3	1		T10	7
valid_sources[0x71]	9214	1			T2	8		T10	7		T14	3
valid_sources[0x72]	9004	1			T2	9		T10	6		T13	13
valid_sources[0x73]	9658	1			T2	8		T10	18		T14	2
valid_sources[0x74]	9750	1			T2	5		T3	4		T10	5
valid_sources[0x75]	17023	1			T2	8		T10	3		T11	1
valid_sources[0x76]	8975	1			T2	17		T10	6		T13	4
valid_sources[0x77]	9629	1			T2	4		T3	7		T10	5
valid_sources[0x78]	9230	1			T2	16		T3	2		T10	3
valid_sources[0x79]	9918	1			T2	10		T3	8		T10	7
valid_sources[0x7a]	8867	1			T3	6		T10	8		T4	2
valid_sources[0x7b]	10600	1			T2	3		T10	11		T14	3
valid_sources[0x7c]	48876	1			T2	14		T3	5		T10	3
valid_sources[0x7d]	10517	1			T2	10		T10	10		T14	5
valid_sources[0x7e]	10751	1			T2	13		T10	4		T14	2
valid_sources[0x7f]	8720	1			T2	16		T10	9		T29	17
valid_sources[0x80]	11262	1			T2	12		T10	5		T14	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1363805

1

T2

1414

T3

151

T9

2292

values[0x0]

all_enables

biggest_size

145700

1

T2

67

T3

29

T9

56

values[0x1]

all_enables

biggest_size

143763

1

T2

71

T3

32

T9

72