Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	104971936	13673	0	0
claim_transition_if_regwen_rd_A	104971936	1185	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104971936	13673	0	0
T46	869	0	0	0
T50	445714	1	0	0
T51	886807	0	0	0
T57	38568	0	0	0
T93	0	5	0	0
T96	148601	0	0	0
T109	0	11	0	0
T114	0	8	0	0
T155	0	3	0	0
T156	0	3	0	0
T157	0	4	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	0	5	0	0
T161	205053	0	0	0
T162	35322	0	0	0
T163	19571	0	0	0
T164	36937	0	0	0
T165	13957	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104971936	1185	0	0
T46	869	0	0	0
T50	445714	6	0	0
T51	886807	0	0	0
T52	0	11	0	0
T57	38568	0	0	0
T96	148601	0	0	0
T97	0	5	0	0
T157	0	20	0	0
T159	0	9	0	0
T161	205053	0	0	0
T162	35322	0	0	0
T163	19571	0	0	0
T164	36937	0	0	0
T165	13957	0	0	0
T166	0	2	0	0
T167	0	4	0	0
T168	0	9	0	0
T169	0	1	0	0
T170	0	27	0	0