Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1412574	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1612685

1

T1

2007

T2

130

T10

1083

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2710297	1			T1	3932		T2	113		T10	1012
values[0x0]	157510	1			T1	54		T2	48		T10	364
values[0x1]	157452	1			T1	46		T2	40		T10	356

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1121653	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1903606

1

T1

2410

T2

141

T10

1209

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9232	1			T1	20		T10	2		T11	13
valid_sources[0x01]	9437	1			T11	22		T12	4		T4	484
valid_sources[0x02]	9416	1			T1	20		T10	10		T11	12
valid_sources[0x03]	9294	1			T1	3		T10	11		T11	13
valid_sources[0x04]	9602	1			T10	2		T11	9		T12	2
valid_sources[0x05]	27331	1			T1	9		T10	7		T11	12
valid_sources[0x06]	9147	1			T1	40		T2	6		T10	7
valid_sources[0x07]	11639	1			T1	8		T10	6		T11	8
valid_sources[0x08]	9207	1			T1	47		T10	10		T11	13
valid_sources[0x09]	9448	1			T1	12		T2	4		T11	18
valid_sources[0x0a]	11765	1			T1	73		T10	14		T11	7
valid_sources[0x0b]	15992	1			T1	18		T10	2		T11	14
valid_sources[0x0c]	10948	1			T1	7		T10	8		T11	17
valid_sources[0x0d]	9388	1			T1	1		T10	4		T11	14
valid_sources[0x0e]	12241	1			T10	6		T11	12		T4	328
valid_sources[0x0f]	9121	1			T1	21		T10	9		T11	9
valid_sources[0x10]	9513	1			T1	16		T10	12		T11	12
valid_sources[0x11]	9144	1			T1	15		T10	8		T11	11
valid_sources[0x12]	9344	1			T1	5		T10	26		T11	12
valid_sources[0x13]	19951	1			T1	11		T10	2		T11	8
valid_sources[0x14]	9442	1			T10	8		T11	12		T4	344
valid_sources[0x15]	9516	1			T1	35		T11	15		T12	6
valid_sources[0x16]	9833	1			T1	2		T10	5		T11	4
valid_sources[0x17]	33595	1			T1	3		T10	2		T11	11
valid_sources[0x18]	95662	1			T1	8		T10	14		T11	12
valid_sources[0x19]	11853	1			T1	7		T11	8		T4	403
valid_sources[0x1a]	9409	1			T1	4		T2	64		T10	9
valid_sources[0x1b]	14380	1			T10	6		T11	13		T12	5
valid_sources[0x1c]	9405	1			T1	17		T10	6		T11	16
valid_sources[0x1d]	9417	1			T1	7		T10	20		T11	7
valid_sources[0x1e]	9651	1			T1	16		T10	26		T11	11
valid_sources[0x1f]	43905	1			T1	16		T10	1		T11	16
valid_sources[0x20]	9259	1			T10	11		T11	11		T12	2
valid_sources[0x21]	9775	1			T10	13		T11	10		T12	2
valid_sources[0x22]	10062	1			T1	31		T10	7		T11	14
valid_sources[0x23]	12221	1			T1	4		T10	6		T11	11
valid_sources[0x24]	10364	1			T1	39		T10	9		T11	9
valid_sources[0x25]	9519	1			T1	4		T10	6		T11	7
valid_sources[0x26]	9699	1			T1	24		T10	10		T11	5
valid_sources[0x27]	9396	1			T1	27		T10	3		T11	15
valid_sources[0x28]	11473	1			T10	6		T11	7		T4	403
valid_sources[0x29]	10896	1			T1	1		T10	11		T11	12
valid_sources[0x2a]	9187	1			T1	15		T10	5		T11	13
valid_sources[0x2b]	9543	1			T10	3		T11	8		T12	9
valid_sources[0x2c]	9197	1			T1	9		T10	6		T11	16
valid_sources[0x2d]	9511	1			T1	19		T10	5		T11	8
valid_sources[0x2e]	9591	1			T1	73		T10	1		T11	11
valid_sources[0x2f]	9311	1			T1	30		T10	4		T11	15
valid_sources[0x30]	11248	1			T1	14		T10	11		T11	17
valid_sources[0x31]	9609	1			T1	58		T10	5		T11	14
valid_sources[0x32]	9485	1			T1	77		T10	16		T11	13
valid_sources[0x33]	9005	1			T1	9		T10	10		T11	23
valid_sources[0x34]	9266	1			T10	1		T11	9		T12	9
valid_sources[0x35]	9335	1			T1	13		T10	13		T11	12
valid_sources[0x36]	9147	1			T10	7		T11	8		T4	419
valid_sources[0x37]	8931	1			T1	15		T10	6		T11	14
valid_sources[0x38]	13106	1			T10	4		T11	8		T12	2
valid_sources[0x39]	10858	1			T1	6		T10	5		T11	8
valid_sources[0x3a]	16042	1			T1	17		T10	8		T11	10
valid_sources[0x3b]	9163	1			T1	6		T10	1		T11	15
valid_sources[0x3c]	11010	1			T1	6		T10	8		T11	7
valid_sources[0x3d]	9579	1			T1	29		T10	15		T11	9
valid_sources[0x3e]	9260	1			T1	21		T10	6		T11	19
valid_sources[0x3f]	10403	1			T1	3		T10	10		T11	9
valid_sources[0x40]	24750	1			T1	35		T10	6		T11	10
valid_sources[0x41]	9379	1			T1	13		T10	7		T11	3
valid_sources[0x42]	9358	1			T1	31		T10	16		T11	13
valid_sources[0x43]	9776	1			T1	14		T10	10		T11	12
valid_sources[0x44]	10023	1			T10	3		T11	16		T4	403
valid_sources[0x45]	14737	1			T1	2		T10	9		T11	14
valid_sources[0x46]	9447	1			T1	6		T10	1		T11	11
valid_sources[0x47]	9345	1			T1	5		T10	3		T11	18
valid_sources[0x48]	9095	1			T1	6		T10	5		T11	6
valid_sources[0x49]	9316	1			T1	20		T10	6		T11	6
valid_sources[0x4a]	9439	1			T1	16		T10	12		T11	17
valid_sources[0x4b]	9608	1			T1	2		T10	8		T11	5
valid_sources[0x4c]	9383	1			T1	15		T10	3		T11	15
valid_sources[0x4d]	9165	1			T1	4		T10	4		T11	13
valid_sources[0x4e]	9420	1			T1	22		T10	5		T11	7
valid_sources[0x4f]	11112	1			T10	7		T11	11		T4	323
valid_sources[0x50]	9403	1			T1	5		T11	10		T12	10
valid_sources[0x51]	9235	1			T1	26		T10	6		T11	9
valid_sources[0x52]	9474	1			T1	13		T10	7		T11	27
valid_sources[0x53]	11509	1			T1	26		T10	8		T11	14
valid_sources[0x54]	9805	1			T1	30		T10	5		T11	12
valid_sources[0x55]	9647	1			T1	4		T10	5		T11	7
valid_sources[0x56]	9559	1			T1	7		T10	1		T11	17
valid_sources[0x57]	9624	1			T1	5		T10	16		T11	9
valid_sources[0x58]	11787	1			T1	12		T10	2		T11	11
valid_sources[0x59]	10366	1			T1	22		T10	1		T11	17
valid_sources[0x5a]	9342	1			T10	1		T11	9		T4	444
valid_sources[0x5b]	9309	1			T1	52		T10	2		T11	10
valid_sources[0x5c]	9827	1			T1	1		T11	13		T12	2
valid_sources[0x5d]	9841	1			T1	11		T10	16		T11	6
valid_sources[0x5e]	9477	1			T1	1		T10	7		T11	7
valid_sources[0x5f]	9716	1			T1	25		T10	4		T11	12
valid_sources[0x60]	9667	1			T1	12		T10	9		T11	7
valid_sources[0x61]	9372	1			T1	2		T10	4		T11	11
valid_sources[0x62]	9053	1			T1	30		T10	4		T11	14
valid_sources[0x63]	9274	1			T1	31		T10	8		T11	11
valid_sources[0x64]	10955	1			T1	13		T10	14		T11	14
valid_sources[0x65]	10066	1			T1	30		T10	3		T11	12
valid_sources[0x66]	12041	1			T2	14		T10	10		T11	12
valid_sources[0x67]	10305	1			T1	10		T10	6		T11	15
valid_sources[0x68]	9243	1			T1	13		T10	6		T11	20
valid_sources[0x69]	9173	1			T11	9		T12	10		T4	453
valid_sources[0x6a]	9242	1			T1	45		T10	2		T11	11
valid_sources[0x6b]	9341	1			T1	24		T10	10		T11	10
valid_sources[0x6c]	33642	1			T1	17		T10	1		T11	10
valid_sources[0x6d]	9071	1			T1	38		T10	1		T11	18
valid_sources[0x6e]	16665	1			T1	54		T10	4		T11	3
valid_sources[0x6f]	9797	1			T1	18		T10	6		T11	12
valid_sources[0x70]	9430	1			T1	26		T10	1		T11	13
valid_sources[0x71]	26601	1			T10	3		T11	14		T12	3
valid_sources[0x72]	12241	1			T1	6		T10	2		T11	20
valid_sources[0x73]	9251	1			T1	12		T10	1		T11	11
valid_sources[0x74]	11777	1			T1	10		T10	5		T11	18
valid_sources[0x75]	9222	1			T10	8		T11	23		T4	464
valid_sources[0x76]	9546	1			T10	7		T11	10		T12	5
valid_sources[0x77]	9154	1			T10	15		T11	7		T12	2
valid_sources[0x78]	9722	1			T1	13		T10	10		T11	16
valid_sources[0x79]	9253	1			T1	12		T10	1		T11	2
valid_sources[0x7a]	13830	1			T1	29		T10	7		T11	17
valid_sources[0x7b]	9305	1			T10	7		T11	15		T4	367
valid_sources[0x7c]	9419	1			T1	32		T10	4		T11	8
valid_sources[0x7d]	10330	1			T1	2		T2	4		T10	7
valid_sources[0x7e]	10419	1			T1	38		T10	9		T11	9
valid_sources[0x7f]	9895	1			T10	3		T11	9		T4	426
valid_sources[0x80]	14389	1			T1	25		T10	7		T11	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1341861

1

T1

1924

T2

51

T10

456

values[0x0]

all_enables

biggest_size

136284

1

T1

43

T2

45

T10

310

values[0x1]

all_enables

biggest_size

134540

1

T1

40

T2

34

T10

317