Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	89085211	12626	0	0
claim_transition_if_regwen_rd_A	89085211	1318	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89085211	12626	0	0
T26	36992	0	0	0
T50	297485	4	0	0
T55	51048	0	0	0
T91	0	4	0	0
T92	0	8	0	0
T102	0	1	0	0
T107	0	7	0	0
T140	0	3	0	0
T141	0	6	0	0
T142	0	16	0	0
T143	0	3	0	0
T144	0	11	0	0
T145	25446	0	0	0
T146	1483	0	0	0
T147	19391	0	0	0
T148	4427	0	0	0
T149	6027	0	0	0
T150	145466	0	0	0
T151	18983	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89085211	1318	0	0
T106	0	7	0	0
T108	0	9	0	0
T152	306035	4	0	0
T153	0	3	0	0
T154	0	83	0	0
T155	0	20	0	0
T156	0	287	0	0
T157	0	17	0	0
T158	0	5	0	0
T159	0	233	0	0
T160	18563	0	0	0
T161	6656	0	0	0
T162	192860	0	0	0
T163	938	0	0	0
T164	37194	0	0	0
T165	1961	0	0	0
T166	60891	0	0	0
T167	3341	0	0	0
T168	42954	0	0	0